arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Device Tree file for LX2162A Clearfog
   4 //
   5 // Copyright 2023 Josua Mayer <josua@solid-run.com>
   6
   7 /dts-v1/;
   8
   9 #include "fsl-lx2160a.dtsi"
  10 #include "fsl-lx2162a-sr-som.dtsi"
  11
  12 / {
  13         model = "SolidRun LX2162A Clearfog";
  14         compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
  15
  16         aliases {
  17                 crypto = &crypto;
  18                 i2c0 = &i2c0;
  19                 i2c1 = &i2c2;
  20                 i2c2 = &i2c4;
  21                 i2c3 = &sfp_i2c0;
  22                 i2c4 = &sfp_i2c1;
  23                 i2c5 = &sfp_i2c2;
  24                 i2c6 = &sfp_i2c3;
  25                 i2c7 = &mpcie1_i2c;
  26                 i2c8 = &mpcie0_i2c;
  27                 i2c9 = &pcieclk_i2c;
  28                 mmc0 = &esdhc0;
  29                 mmc1 = &esdhc1;
  30                 serial0 = &uart0;
  31         };
  32
  33         chosen {
  34                 stdout-path = "serial0:115200n8";
  35         };
  36
  37         leds {
  38                 compatible = "gpio-leds";
  39
  40                 led_sfp_at: led-sfp-at {
  41                         gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
  42                         default-state = "off";
  43                 };
  44
  45                 led_sfp_ab: led-sfp-ab {
  46                         gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
  47                         default-state = "off";
  48                 };
  49
  50                 led_sfp_bt: led-sfp-bt {
  51                         gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
  52                         default-state = "off";
  53                 };
  54
  55                 led_sfp_bb: led-sfp-bb {
  56                         gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
  57                         default-state = "off";
  58                 };
  59         };
  60
  61         sfp_at: sfp-at {
  62                 compatible = "sff,sfp";
  63                 i2c-bus = <&sfp_i2c0>;
  64                 mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
  65                 maximum-power-milliwatt = <2000>;
  66         };
  67
  68         sfp_ab: sfp-ab {
  69                 compatible = "sff,sfp";
  70                 i2c-bus = <&sfp_i2c1>;
  71                 mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
  72                 maximum-power-milliwatt = <2000>;
  73         };
  74
  75         sfp_bt: sfp-bt {
  76                 compatible = "sff,sfp";
  77                 i2c-bus = <&sfp_i2c2>;
  78                 mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
  79                 maximum-power-milliwatt = <2000>;
  80         };
  81
  82         sfp_bb: sfp-bb {
  83                 compatible = "sff,sfp";
  84                 i2c-bus = <&sfp_i2c3>;
  85                 mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
  86                 maximum-power-milliwatt = <2000>;
  87         };
  88 };
  89
  90 &dpmac3 {
  91         sfp = <&sfp_at>;
  92         managed = "in-band-status";
  93         phys = <&serdes_1 7>;
  94 };
  95
  96 &dpmac4 {
  97         sfp = <&sfp_ab>;
  98         managed = "in-band-status";
  99         phys = <&serdes_1 6>;
 100 };
 101
 102 &dpmac5 {
 103         sfp = <&sfp_bt>;
 104         managed = "in-band-status";
 105         phys = <&serdes_1 5>;
 106 };
 107
 108 &dpmac6 {
 109         sfp = <&sfp_bb>;
 110         managed = "in-band-status";
 111         phys = <&serdes_1 4>;
 112 };
 113
 114 &dpmac11 {
 115         phys = <&serdes_2 0>;
 116         phy-handle = <&ethernet_phy3>;
 117         phy-connection-type = "sgmii";
 118         status = "okay";
 119 };
 120
 121 &dpmac12 {
 122         phys = <&serdes_2 1>;
 123         phy-handle = <&ethernet_phy1>;
 124         phy-connection-type = "sgmii";
 125         status = "okay";
 126 };
 127
 128 &dpmac13 {
 129         phys = <&serdes_2 6>;
 130         phy-handle = <&ethernet_phy6>;
 131         phy-connection-type = "sgmii";
 132         status = "okay";
 133 };
 134
 135 &dpmac14 {
 136         phys = <&serdes_2 7>;
 137         phy-handle = <&ethernet_phy8>;
 138         phy-connection-type = "sgmii";
 139         status = "okay";
 140 };
 141
 142 &dpmac15 {
 143         phys = <&serdes_2 4>;
 144         phy-handle = <&ethernet_phy4>;
 145         phy-connection-type = "sgmii";
 146         status = "okay";
 147 };
 148
 149 &dpmac16 {
 150         phys = <&serdes_2 5>;
 151         phy-handle = <&ethernet_phy2>;
 152         phy-connection-type = "sgmii";
 153         status = "okay";
 154 };
 155
 156 &dpmac17 {
 157         /* override connection to on-SoM phy */
 158         /delete-property/ phy-handle;
 159         /delete-property/ phy-connection-type;
 160
 161         phys = <&serdes_2 2>;
 162         phy-handle = <&ethernet_phy5>;
 163         phy-connection-type = "sgmii";
 164         status = "okay";
 165 };
 166
 167 &dpmac18 {
 168         phys = <&serdes_2 3>;
 169         phy-handle = <&ethernet_phy7>;
 170         phy-connection-type = "sgmii";
 171         status = "okay";
 172 };
 173
 174 &emdio1 {
 175         ethernet_phy1: ethernet-phy@8 {
 176                 compatible = "ethernet-phy-ieee802.3-c45";
 177                 reg = <8>;
 178                 max-speed = <1000>;
 179         };
 180
 181         ethernet_phy2: ethernet-phy@9 {
 182                 compatible = "ethernet-phy-ieee802.3-c45";
 183                 reg = <9>;
 184                 max-speed = <1000>;
 185         };
 186
 187         ethernet_phy3: ethernet-phy@10 {
 188                 compatible = "ethernet-phy-ieee802.3-c45";
 189                 reg = <10>;
 190                 max-speed = <1000>;
 191         };
 192
 193         ethernet_phy4: ethernet-phy@11 {
 194                 compatible = "ethernet-phy-ieee802.3-c45";
 195                 reg = <11>;
 196                 max-speed = <1000>;
 197         };
 198
 199         ethernet_phy5: ethernet-phy@12 {
 200                 compatible = "ethernet-phy-ieee802.3-c45";
 201                 reg = <12>;
 202                 max-speed = <1000>;
 203         };
 204
 205         ethernet_phy6: ethernet-phy@13 {
 206                 compatible = "ethernet-phy-ieee802.3-c45";
 207                 reg = <13>;
 208                 max-speed = <1000>;
 209         };
 210
 211         ethernet_phy7: ethernet-phy@14 {
 212                 compatible = "ethernet-phy-ieee802.3-c45";
 213                 reg = <14>;
 214                 max-speed = <1000>;
 215         };
 216
 217         ethernet_phy8: ethernet-phy@15 {
 218                 compatible = "ethernet-phy-ieee802.3-c45";
 219                 reg = <15>;
 220                 max-speed = <1000>;
 221         };
 222 };
 223
 224 &esdhc0 {
 225         sd-uhs-sdr104;
 226         sd-uhs-sdr50;
 227         sd-uhs-sdr25;
 228         sd-uhs-sdr12;
 229         status = "okay";
 230 };
 231
 232 &ethernet_phy0 {
 233         /*
 234          * SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
 235          * It competes for WRIOP MAC17, and no connector has been wired.
 236          */
 237         status = "disabled";
 238 };
 239
 240 &i2c2 {
 241         status = "okay";
 242
 243         /* retimer@18 */
 244
 245         i2c-mux@70 {
 246                 compatible = "nxp,pca9546";
 247                 reg = <0x70>;
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250                 i2c-mux-idle-disconnect;
 251
 252                 sfp_i2c0: i2c@0 {
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                         reg = <0>;
 256                 };
 257
 258                 sfp_i2c1: i2c@1 {
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         reg = <1>;
 262                 };
 263
 264                 sfp_i2c2: i2c@2 {
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         reg = <2>;
 268                 };
 269
 270                 sfp_i2c3: i2c@3 {
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273                         reg = <3>;
 274                 };
 275         };
 276
 277         i2c-mux@71 {
 278                 compatible = "nxp,pca9546";
 279                 reg = <0x71>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 i2c-mux-idle-disconnect;
 283
 284                 mpcie1_i2c: i2c@0 {
 285                         #address-cells = <1>;
 286                         #size-cells = <0>;
 287                         reg = <0>;
 288                 };
 289
 290                 mpcie0_i2c: i2c@1 {
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         reg = <1>;
 294                 };
 295
 296                 pcieclk_i2c: i2c@2 {
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                         reg = <2>;
 300
 301                         /* clock-controller@6b */
 302                 };
 303         };
 304 };
 305
 306 &pcie3 {
 307         status = "disabled";
 308 };
 309
 310 &pcie4 {
 311         status = "disabled";
 312 };
 313
 314 &pcs_mdio3 {
 315         status = "okay";
 316 };
 317
 318 &pcs_mdio4 {
 319         status = "okay";
 320 };
 321
 322 &pcs_mdio5 {
 323         status = "okay";
 324 };
 325
 326 &pcs_mdio6 {
 327         status = "okay";
 328 };
 329
 330 &pcs_mdio11 {
 331         status = "okay";
 332 };
 333
 334 &pcs_mdio12 {
 335         status = "okay";
 336 };
 337
 338 &pcs_mdio13 {
 339         status = "okay";
 340 };
 341
 342 &pcs_mdio14 {
 343         status = "okay";
 344 };
 345
 346 &pcs_mdio15 {
 347         status = "okay";
 348 };
 349
 350 &pcs_mdio16 {
 351         status = "okay";
 352 };
 353
 354 &pcs_mdio17 {
 355         status = "okay";
 356 };
 357
 358 &pcs_mdio18 {
 359         status = "okay";
 360 };
 361
 362 &serdes_1 {
 363         status = "okay";
 364 };
 365
 366 &serdes_2 {
 367         status = "okay";
 368 };
 369
 370 &uart0 {
 371         status = "okay";
 372 };
 373
 374 &usb0 {
 375         status = "okay";
 376 };