1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 /memreserve/ 0x80000000 0x00010000;
15 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>;
28 // 8 clusters having 2 Cortex-A72 cores each
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <64>;
38 i-cache-size = <0xC000>;
39 i-cache-line-size = <64>;
41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cpu_pw15>;
48 compatible = "arm,cortex-a72";
49 enable-method = "psci";
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
55 i-cache-size = <0xC000>;
56 i-cache-line-size = <64>;
58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cpu_pw15>;
65 compatible = "arm,cortex-a72";
66 enable-method = "psci";
68 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
69 d-cache-size = <0x8000>;
70 d-cache-line-size = <64>;
72 i-cache-size = <0xC000>;
73 i-cache-line-size = <64>;
75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cpu_pw15>;
82 compatible = "arm,cortex-a72";
83 enable-method = "psci";
85 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
89 i-cache-size = <0xC000>;
90 i-cache-line-size = <64>;
92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cpu_pw15>;
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
102 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
103 d-cache-size = <0x8000>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <192>;
109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a72";
117 enable-method = "psci";
119 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <192>;
126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a72";
134 enable-method = "psci";
136 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
137 d-cache-size = <0x8000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a72";
151 enable-method = "psci";
153 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <192>;
160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>;
167 compatible = "arm,cortex-a72";
168 enable-method = "psci";
170 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <192>;
177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>;
184 compatible = "arm,cortex-a72";
185 enable-method = "psci";
187 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
188 d-cache-size = <0x8000>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000>;
192 i-cache-line-size = <64>;
193 i-cache-sets = <192>;
194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>;
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
204 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>;
218 compatible = "arm,cortex-a72";
219 enable-method = "psci";
221 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
222 d-cache-size = <0x8000>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <192>;
228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>;
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
238 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>;
252 compatible = "arm,cortex-a72";
253 enable-method = "psci";
255 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
256 d-cache-size = <0x8000>;
257 d-cache-line-size = <64>;
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000>;
260 i-cache-line-size = <64>;
261 i-cache-sets = <192>;
262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>;
269 compatible = "arm,cortex-a72";
270 enable-method = "psci";
272 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
273 d-cache-size = <0x8000>;
274 d-cache-line-size = <64>;
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000>;
277 i-cache-line-size = <64>;
278 i-cache-sets = <192>;
279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>;
286 compatible = "arm,cortex-a72";
287 enable-method = "psci";
289 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
290 d-cache-size = <0x8000>;
291 d-cache-line-size = <64>;
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000>;
294 i-cache-line-size = <64>;
295 i-cache-sets = <192>;
296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>;
301 cluster0_l2: l2-cache0 {
302 compatible = "cache";
304 cache-size = <0x100000>;
305 cache-line-size = <64>;
310 cluster1_l2: l2-cache1 {
311 compatible = "cache";
313 cache-size = <0x100000>;
314 cache-line-size = <64>;
319 cluster2_l2: l2-cache2 {
320 compatible = "cache";
322 cache-size = <0x100000>;
323 cache-line-size = <64>;
328 cluster3_l2: l2-cache3 {
329 compatible = "cache";
331 cache-size = <0x100000>;
332 cache-line-size = <64>;
337 cluster4_l2: l2-cache4 {
338 compatible = "cache";
340 cache-size = <0x100000>;
341 cache-line-size = <64>;
346 cluster5_l2: l2-cache5 {
347 compatible = "cache";
349 cache-size = <0x100000>;
350 cache-line-size = <64>;
355 cluster6_l2: l2-cache6 {
356 compatible = "cache";
358 cache-size = <0x100000>;
359 cache-line-size = <64>;
364 cluster7_l2: l2-cache7 {
365 compatible = "cache";
367 cache-size = <0x100000>;
368 cache-line-size = <64>;
374 compatible = "arm,idle-state";
375 idle-state-name = "PW15";
376 arm,psci-suspend-param = <0x0>;
377 entry-latency-us = <2000>;
378 exit-latency-us = <2000>;
379 min-residency-us = <6000>;
383 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3";
385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
388 <0x0 0x0c0c0000 0 0x2000>, // GICC
389 <0x0 0x0c0d0000 0 0x1000>, // GICH
390 <0x0 0x0c0e0000 0 0x20000>; // GICV
391 #interrupt-cells = <3>;
392 #address-cells = <2>;
395 interrupt-controller;
396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
398 its: msi-controller@6020000 {
399 compatible = "arm,gic-v3-its";
401 reg = <0x0 0x6020000 0 0x20000>;
406 compatible = "arm,armv8-timer";
407 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
414 compatible = "arm,cortex-a72-pmu";
415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
419 compatible = "arm,psci-0.2";
424 // DRAM space - 1, size : 2 GB DRAM
425 device_type = "memory";
426 reg = <0x00000000 0x80000000 0 0x80000000>;
429 ddr1: memory-controller@1080000 {
430 compatible = "fsl,qoriq-memory-controller";
431 reg = <0x0 0x1080000 0x0 0x1000>;
432 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
436 ddr2: memory-controller@1090000 {
437 compatible = "fsl,qoriq-memory-controller";
438 reg = <0x0 0x1090000 0x0 0x1000>;
439 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
443 // One clock unit-sysclk node which bootloader require during DT fix-up
445 compatible = "fixed-clock";
447 clock-frequency = <100000000>; // fixed up by bootloader
448 clock-output-names = "sysclk";
453 polling-delay-passive = <1000>;
454 polling-delay = <5000>;
455 thermal-sensors = <&tmu 0>;
458 cluster6_7_alert: cluster6-7-alert {
459 temperature = <85000>;
464 cluster6_7_crit: cluster6-7-crit {
465 temperature = <95000>;
473 trip = <&cluster6_7_alert>;
475 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
476 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
477 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
478 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
479 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
480 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
481 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
482 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
483 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
484 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
485 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
486 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
487 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
488 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
489 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
490 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
496 polling-delay-passive = <1000>;
497 polling-delay = <5000>;
498 thermal-sensors = <&tmu 1>;
502 temperature = <85000>;
508 temperature = <95000>;
516 polling-delay-passive = <1000>;
517 polling-delay = <5000>;
518 thermal-sensors = <&tmu 2>;
522 temperature = <85000>;
528 temperature = <95000>;
536 polling-delay-passive = <1000>;
537 polling-delay = <5000>;
538 thermal-sensors = <&tmu 3>;
542 temperature = <85000>;
548 temperature = <95000>;
556 polling-delay-passive = <1000>;
557 polling-delay = <5000>;
558 thermal-sensors = <&tmu 4>;
562 temperature = <85000>;
568 temperature = <95000>;
576 polling-delay-passive = <1000>;
577 polling-delay = <5000>;
578 thermal-sensors = <&tmu 5>;
582 temperature = <85000>;
588 temperature = <95000>;
596 polling-delay-passive = <1000>;
597 polling-delay = <5000>;
598 thermal-sensors = <&tmu 6>;
602 temperature = <85000>;
608 temperature = <95000>;
617 compatible = "simple-bus";
618 #address-cells = <2>;
621 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
623 serdes_1: phy@1ea0000 {
624 compatible = "fsl,lynx-28g";
625 reg = <0x0 0x1ea0000 0x0 0x1e30>;
629 serdes_2: phy@1eb0000 {
630 compatible = "fsl,lynx-28g";
631 reg = <0x0 0x1eb0000 0x0 0x1e30>;
636 crypto: crypto@8000000 {
637 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
639 #address-cells = <1>;
641 ranges = <0x0 0x00 0x8000000 0x100000>;
642 reg = <0x00 0x8000000 0x0 0x100000>;
643 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
648 compatible = "fsl,sec-v5.0-job-ring",
649 "fsl,sec-v4.0-job-ring";
650 reg = <0x10000 0x10000>;
651 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
655 compatible = "fsl,sec-v5.0-job-ring",
656 "fsl,sec-v4.0-job-ring";
657 reg = <0x20000 0x10000>;
658 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
662 compatible = "fsl,sec-v5.0-job-ring",
663 "fsl,sec-v4.0-job-ring";
664 reg = <0x30000 0x10000>;
665 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
669 compatible = "fsl,sec-v5.0-job-ring",
670 "fsl,sec-v4.0-job-ring";
671 reg = <0x40000 0x10000>;
672 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
676 clockgen: clock-controller@1300000 {
677 compatible = "fsl,lx2160a-clockgen";
678 reg = <0 0x1300000 0 0xa0000>;
683 dcfg: syscon@1e00000 {
684 compatible = "fsl,lx2160a-dcfg", "syscon";
685 reg = <0x0 0x1e00000 0x0 0x10000>;
690 compatible = "fsl,ls1028a-sfp";
691 reg = <0x0 0x1e80000 0x0 0x10000>;
692 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
693 QORIQ_CLK_PLL_DIV(4)>;
697 isc: syscon@1f70000 {
698 compatible = "fsl,lx2160a-isc", "syscon";
699 reg = <0x0 0x1f70000 0x0 0x10000>;
701 #address-cells = <1>;
703 ranges = <0x0 0x0 0x1f70000 0x10000>;
705 extirq: interrupt-controller@14 {
706 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
707 #interrupt-cells = <2>;
708 #address-cells = <0>;
709 interrupt-controller;
712 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
713 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
714 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
715 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
716 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
717 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
718 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
719 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
720 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
721 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
722 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
723 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-map-mask = <0xf 0x0>;
729 compatible = "fsl,qoriq-tmu";
730 reg = <0x0 0x1f80000 0x0 0x10000>;
731 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
732 fsl,tmu-range = <0x800000e6 0x8001017d>;
733 fsl,tmu-calibration =
734 /* Calibration data group 1 */
735 <0x00000000 0x00000035
736 /* Calibration data group 2 */
737 0x00000001 0x00000154>;
739 #thermal-sensor-cells = <1>;
743 compatible = "fsl,vf610-i2c";
744 #address-cells = <1>;
746 reg = <0x0 0x2000000 0x0 0x10000>;
747 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
750 QORIQ_CLK_PLL_DIV(16)>;
751 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
756 compatible = "fsl,vf610-i2c";
757 #address-cells = <1>;
759 reg = <0x0 0x2010000 0x0 0x10000>;
760 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
763 QORIQ_CLK_PLL_DIV(16)>;
768 compatible = "fsl,vf610-i2c";
769 #address-cells = <1>;
771 reg = <0x0 0x2020000 0x0 0x10000>;
772 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
775 QORIQ_CLK_PLL_DIV(16)>;
780 compatible = "fsl,vf610-i2c";
781 #address-cells = <1>;
783 reg = <0x0 0x2030000 0x0 0x10000>;
784 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
787 QORIQ_CLK_PLL_DIV(16)>;
792 compatible = "fsl,vf610-i2c";
793 #address-cells = <1>;
795 reg = <0x0 0x2040000 0x0 0x10000>;
796 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
799 QORIQ_CLK_PLL_DIV(16)>;
800 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
805 compatible = "fsl,vf610-i2c";
806 #address-cells = <1>;
808 reg = <0x0 0x2050000 0x0 0x10000>;
809 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
812 QORIQ_CLK_PLL_DIV(16)>;
817 compatible = "fsl,vf610-i2c";
818 #address-cells = <1>;
820 reg = <0x0 0x2060000 0x0 0x10000>;
821 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
824 QORIQ_CLK_PLL_DIV(16)>;
829 compatible = "fsl,vf610-i2c";
830 #address-cells = <1>;
832 reg = <0x0 0x2070000 0x0 0x10000>;
833 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
836 QORIQ_CLK_PLL_DIV(16)>;
841 compatible = "nxp,lx2160a-fspi";
842 #address-cells = <1>;
844 reg = <0x0 0x20c0000 0x0 0x10000>,
845 <0x0 0x20000000 0x0 0x10000000>;
846 reg-names = "fspi_base", "fspi_mmap";
847 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
849 QORIQ_CLK_PLL_DIV(4)>,
850 <&clockgen QORIQ_CLK_PLATFORM_PLL
851 QORIQ_CLK_PLL_DIV(4)>;
852 clock-names = "fspi_en", "fspi";
857 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
858 #address-cells = <1>;
860 reg = <0x0 0x2100000 0x0 0x10000>;
861 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
863 QORIQ_CLK_PLL_DIV(8)>;
864 clock-names = "dspi";
865 spi-num-chipselects = <5>;
871 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
872 #address-cells = <1>;
874 reg = <0x0 0x2110000 0x0 0x10000>;
875 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
877 QORIQ_CLK_PLL_DIV(8)>;
878 clock-names = "dspi";
879 spi-num-chipselects = <5>;
885 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
886 #address-cells = <1>;
888 reg = <0x0 0x2120000 0x0 0x10000>;
889 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
891 QORIQ_CLK_PLL_DIV(8)>;
892 clock-names = "dspi";
893 spi-num-chipselects = <5>;
898 esdhc0: esdhc@2140000 {
899 compatible = "fsl,esdhc";
900 reg = <0x0 0x2140000 0x0 0x10000>;
901 interrupts = <0 28 0x4>; /* Level high type */
902 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
903 QORIQ_CLK_PLL_DIV(2)>;
905 voltage-ranges = <1800 1800 3300 3300>;
912 esdhc1: esdhc@2150000 {
913 compatible = "fsl,esdhc";
914 reg = <0x0 0x2150000 0x0 0x10000>;
915 interrupts = <0 63 0x4>; /* Level high type */
916 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
917 QORIQ_CLK_PLL_DIV(2)>;
919 voltage-ranges = <1800 1800 3300 3300>;
928 compatible = "fsl,lx2160ar1-flexcan";
929 reg = <0x0 0x2180000 0x0 0x10000>;
930 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
932 QORIQ_CLK_PLL_DIV(8)>,
933 <&clockgen QORIQ_CLK_SYSCLK 0>;
934 clock-names = "ipg", "per";
935 fsl,clk-source = /bits/ 8 <0>;
940 compatible = "fsl,lx2160ar1-flexcan";
941 reg = <0x0 0x2190000 0x0 0x10000>;
942 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
944 QORIQ_CLK_PLL_DIV(8)>,
945 <&clockgen QORIQ_CLK_SYSCLK 0>;
946 clock-names = "ipg", "per";
947 fsl,clk-source = /bits/ 8 <0>;
951 uart0: serial@21c0000 {
952 compatible = "arm,sbsa-uart","arm,pl011";
953 reg = <0x0 0x21c0000 0x0 0x1000>;
954 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
955 current-speed = <115200>;
959 uart1: serial@21d0000 {
960 compatible = "arm,sbsa-uart","arm,pl011";
961 reg = <0x0 0x21d0000 0x0 0x1000>;
962 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
963 current-speed = <115200>;
967 uart2: serial@21e0000 {
968 compatible = "arm,sbsa-uart","arm,pl011";
969 reg = <0x0 0x21e0000 0x0 0x1000>;
970 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
971 current-speed = <115200>;
975 uart3: serial@21f0000 {
976 compatible = "arm,sbsa-uart","arm,pl011";
977 reg = <0x0 0x21f0000 0x0 0x1000>;
978 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
979 current-speed = <115200>;
983 gpio0: gpio@2300000 {
984 compatible = "fsl,qoriq-gpio";
985 reg = <0x0 0x2300000 0x0 0x10000>;
986 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
990 interrupt-controller;
991 #interrupt-cells = <2>;
994 gpio1: gpio@2310000 {
995 compatible = "fsl,qoriq-gpio";
996 reg = <0x0 0x2310000 0x0 0x10000>;
997 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1001 interrupt-controller;
1002 #interrupt-cells = <2>;
1005 gpio2: gpio@2320000 {
1006 compatible = "fsl,qoriq-gpio";
1007 reg = <0x0 0x2320000 0x0 0x10000>;
1008 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1012 interrupt-controller;
1013 #interrupt-cells = <2>;
1016 gpio3: gpio@2330000 {
1017 compatible = "fsl,qoriq-gpio";
1018 reg = <0x0 0x2330000 0x0 0x10000>;
1019 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1023 interrupt-controller;
1024 #interrupt-cells = <2>;
1028 compatible = "arm,sbsa-gwdt";
1029 reg = <0x0 0x23a0000 0 0x1000>,
1030 <0x0 0x2390000 0 0x1000>;
1031 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1035 rcpm: power-controller@1e34040 {
1036 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1037 reg = <0x0 0x1e34040 0x0 0x1c>;
1038 #fsl,rcpm-wakeup-cells = <7>;
1042 ftm_alarm0: timer@2800000 {
1043 compatible = "fsl,lx2160a-ftm-alarm";
1044 reg = <0x0 0x2800000 0x0 0x10000>;
1045 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1046 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1050 compatible = "snps,dwc3";
1051 reg = <0x0 0x3100000 0x0 0x10000>;
1052 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1054 snps,quirk-frame-length-adjustment = <0x20>;
1056 snps,dis_rxdet_inp3_quirk;
1057 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1058 status = "disabled";
1062 compatible = "snps,dwc3";
1063 reg = <0x0 0x3110000 0x0 0x10000>;
1064 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1066 snps,quirk-frame-length-adjustment = <0x20>;
1068 snps,dis_rxdet_inp3_quirk;
1069 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1070 status = "disabled";
1073 sata0: sata@3200000 {
1074 compatible = "fsl,lx2160a-ahci";
1075 reg = <0x0 0x3200000 0x0 0x10000>,
1076 <0x7 0x100520 0x0 0x4>;
1077 reg-names = "ahci", "sata-ecc";
1078 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1080 QORIQ_CLK_PLL_DIV(4)>;
1082 status = "disabled";
1085 sata1: sata@3210000 {
1086 compatible = "fsl,lx2160a-ahci";
1087 reg = <0x0 0x3210000 0x0 0x10000>,
1088 <0x7 0x100520 0x0 0x4>;
1089 reg-names = "ahci", "sata-ecc";
1090 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1092 QORIQ_CLK_PLL_DIV(4)>;
1094 status = "disabled";
1097 sata2: sata@3220000 {
1098 compatible = "fsl,lx2160a-ahci";
1099 reg = <0x0 0x3220000 0x0 0x10000>,
1100 <0x7 0x100520 0x0 0x4>;
1101 reg-names = "ahci", "sata-ecc";
1102 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1104 QORIQ_CLK_PLL_DIV(4)>;
1106 status = "disabled";
1109 sata3: sata@3230000 {
1110 compatible = "fsl,lx2160a-ahci";
1111 reg = <0x0 0x3230000 0x0 0x10000>,
1112 <0x7 0x100520 0x0 0x4>;
1113 reg-names = "ahci", "sata-ecc";
1114 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1115 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1116 QORIQ_CLK_PLL_DIV(4)>;
1118 status = "disabled";
1121 pcie1: pcie@3400000 {
1122 compatible = "fsl,lx2160a-pcie";
1123 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
1124 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1125 reg-names = "csr_axi_slave", "config_axi_slave";
1126 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1127 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1128 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1129 interrupt-names = "aer", "pme", "intr";
1130 #address-cells = <3>;
1132 device_type = "pci";
1136 bus-range = <0x0 0xff>;
1137 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1138 msi-parent = <&its>;
1139 #interrupt-cells = <1>;
1140 interrupt-map-mask = <0 0 0 7>;
1141 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1142 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1143 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1144 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1145 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1146 status = "disabled";
1149 pcie2: pcie@3500000 {
1150 compatible = "fsl,lx2160a-pcie";
1151 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
1152 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1153 reg-names = "csr_axi_slave", "config_axi_slave";
1154 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1155 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1156 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1157 interrupt-names = "aer", "pme", "intr";
1158 #address-cells = <3>;
1160 device_type = "pci";
1164 bus-range = <0x0 0xff>;
1165 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1166 msi-parent = <&its>;
1167 #interrupt-cells = <1>;
1168 interrupt-map-mask = <0 0 0 7>;
1169 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1170 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1171 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1172 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1173 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1174 status = "disabled";
1177 pcie3: pcie@3600000 {
1178 compatible = "fsl,lx2160a-pcie";
1179 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
1180 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1181 reg-names = "csr_axi_slave", "config_axi_slave";
1182 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1183 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1184 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1185 interrupt-names = "aer", "pme", "intr";
1186 #address-cells = <3>;
1188 device_type = "pci";
1192 bus-range = <0x0 0xff>;
1193 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1194 msi-parent = <&its>;
1195 #interrupt-cells = <1>;
1196 interrupt-map-mask = <0 0 0 7>;
1197 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1198 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1199 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1200 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1201 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1202 status = "disabled";
1205 pcie4: pcie@3700000 {
1206 compatible = "fsl,lx2160a-pcie";
1207 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
1208 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1209 reg-names = "csr_axi_slave", "config_axi_slave";
1210 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1211 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1212 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1213 interrupt-names = "aer", "pme", "intr";
1214 #address-cells = <3>;
1216 device_type = "pci";
1220 bus-range = <0x0 0xff>;
1221 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1222 msi-parent = <&its>;
1223 #interrupt-cells = <1>;
1224 interrupt-map-mask = <0 0 0 7>;
1225 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1226 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1227 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1228 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1229 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1230 status = "disabled";
1233 pcie5: pcie@3800000 {
1234 compatible = "fsl,lx2160a-pcie";
1235 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
1236 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1237 reg-names = "csr_axi_slave", "config_axi_slave";
1238 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1239 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1240 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1241 interrupt-names = "aer", "pme", "intr";
1242 #address-cells = <3>;
1244 device_type = "pci";
1248 bus-range = <0x0 0xff>;
1249 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1250 msi-parent = <&its>;
1251 #interrupt-cells = <1>;
1252 interrupt-map-mask = <0 0 0 7>;
1253 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1254 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1255 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1256 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1257 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1258 status = "disabled";
1261 pcie6: pcie@3900000 {
1262 compatible = "fsl,lx2160a-pcie";
1263 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
1264 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1265 reg-names = "csr_axi_slave", "config_axi_slave";
1266 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1267 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1268 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1269 interrupt-names = "aer", "pme", "intr";
1270 #address-cells = <3>;
1272 device_type = "pci";
1276 bus-range = <0x0 0xff>;
1277 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1278 msi-parent = <&its>;
1279 #interrupt-cells = <1>;
1280 interrupt-map-mask = <0 0 0 7>;
1281 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1282 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1283 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1284 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1285 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1286 status = "disabled";
1289 smmu: iommu@5000000 {
1290 compatible = "arm,mmu-500";
1291 reg = <0 0x5000000 0 0x800000>;
1293 #global-interrupts = <14>;
1294 // global secure fault
1295 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1298 // global non-secure fault
1299 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1300 // combined non-secure
1301 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1302 // performance counter interrupts 0-9
1303 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1305 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1306 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1307 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1308 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1309 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1310 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1312 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1313 // per context interrupt, 64 interrupts
1314 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1315 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1382 compatible = "fsl,dpaa2-console";
1383 reg = <0x00000000 0x08340020 0 0x2>;
1387 compatible = "fsl,dpaa2-ptp";
1388 reg = <0x0 0x8b95000 0x0 0x100>;
1389 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1390 QORIQ_CLK_PLL_DIV(2)>;
1395 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1396 emdio1: mdio@8b96000 {
1397 compatible = "fsl,fman-memac-mdio";
1398 reg = <0x0 0x8b96000 0x0 0x1000>;
1399 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1400 #address-cells = <1>;
1403 clock-frequency = <2500000>;
1404 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1405 QORIQ_CLK_PLL_DIV(2)>;
1406 status = "disabled";
1409 emdio2: mdio@8b97000 {
1410 compatible = "fsl,fman-memac-mdio";
1411 reg = <0x0 0x8b97000 0x0 0x1000>;
1412 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1414 #address-cells = <1>;
1416 clock-frequency = <2500000>;
1417 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1418 QORIQ_CLK_PLL_DIV(2)>;
1419 status = "disabled";
1422 pcs_mdio1: mdio@8c07000 {
1423 compatible = "fsl,fman-memac-mdio";
1424 reg = <0x0 0x8c07000 0x0 0x1000>;
1426 #address-cells = <1>;
1428 status = "disabled";
1430 pcs1: ethernet-phy@0 {
1435 pcs_mdio2: mdio@8c0b000 {
1436 compatible = "fsl,fman-memac-mdio";
1437 reg = <0x0 0x8c0b000 0x0 0x1000>;
1439 #address-cells = <1>;
1441 status = "disabled";
1443 pcs2: ethernet-phy@0 {
1448 pcs_mdio3: mdio@8c0f000 {
1449 compatible = "fsl,fman-memac-mdio";
1450 reg = <0x0 0x8c0f000 0x0 0x1000>;
1452 #address-cells = <1>;
1454 status = "disabled";
1456 pcs3: ethernet-phy@0 {
1461 pcs_mdio4: mdio@8c13000 {
1462 compatible = "fsl,fman-memac-mdio";
1463 reg = <0x0 0x8c13000 0x0 0x1000>;
1465 #address-cells = <1>;
1467 status = "disabled";
1469 pcs4: ethernet-phy@0 {
1474 pcs_mdio5: mdio@8c17000 {
1475 compatible = "fsl,fman-memac-mdio";
1476 reg = <0x0 0x8c17000 0x0 0x1000>;
1478 #address-cells = <1>;
1480 status = "disabled";
1482 pcs5: ethernet-phy@0 {
1487 pcs_mdio6: mdio@8c1b000 {
1488 compatible = "fsl,fman-memac-mdio";
1489 reg = <0x0 0x8c1b000 0x0 0x1000>;
1491 #address-cells = <1>;
1493 status = "disabled";
1495 pcs6: ethernet-phy@0 {
1500 pcs_mdio7: mdio@8c1f000 {
1501 compatible = "fsl,fman-memac-mdio";
1502 reg = <0x0 0x8c1f000 0x0 0x1000>;
1504 #address-cells = <1>;
1506 status = "disabled";
1508 pcs7: ethernet-phy@0 {
1513 pcs_mdio8: mdio@8c23000 {
1514 compatible = "fsl,fman-memac-mdio";
1515 reg = <0x0 0x8c23000 0x0 0x1000>;
1517 #address-cells = <1>;
1519 status = "disabled";
1521 pcs8: ethernet-phy@0 {
1526 pcs_mdio9: mdio@8c27000 {
1527 compatible = "fsl,fman-memac-mdio";
1528 reg = <0x0 0x8c27000 0x0 0x1000>;
1530 #address-cells = <1>;
1532 status = "disabled";
1534 pcs9: ethernet-phy@0 {
1539 pcs_mdio10: mdio@8c2b000 {
1540 compatible = "fsl,fman-memac-mdio";
1541 reg = <0x0 0x8c2b000 0x0 0x1000>;
1543 #address-cells = <1>;
1545 status = "disabled";
1547 pcs10: ethernet-phy@0 {
1552 pcs_mdio11: mdio@8c2f000 {
1553 compatible = "fsl,fman-memac-mdio";
1554 reg = <0x0 0x8c2f000 0x0 0x1000>;
1556 #address-cells = <1>;
1558 status = "disabled";
1560 pcs11: ethernet-phy@0 {
1565 pcs_mdio12: mdio@8c33000 {
1566 compatible = "fsl,fman-memac-mdio";
1567 reg = <0x0 0x8c33000 0x0 0x1000>;
1569 #address-cells = <1>;
1571 status = "disabled";
1573 pcs12: ethernet-phy@0 {
1578 pcs_mdio13: mdio@8c37000 {
1579 compatible = "fsl,fman-memac-mdio";
1580 reg = <0x0 0x8c37000 0x0 0x1000>;
1582 #address-cells = <1>;
1584 status = "disabled";
1586 pcs13: ethernet-phy@0 {
1591 pcs_mdio14: mdio@8c3b000 {
1592 compatible = "fsl,fman-memac-mdio";
1593 reg = <0x0 0x8c3b000 0x0 0x1000>;
1595 #address-cells = <1>;
1597 status = "disabled";
1599 pcs14: ethernet-phy@0 {
1604 pcs_mdio15: mdio@8c3f000 {
1605 compatible = "fsl,fman-memac-mdio";
1606 reg = <0x0 0x8c3f000 0x0 0x1000>;
1608 #address-cells = <1>;
1610 status = "disabled";
1612 pcs15: ethernet-phy@0 {
1617 pcs_mdio16: mdio@8c43000 {
1618 compatible = "fsl,fman-memac-mdio";
1619 reg = <0x0 0x8c43000 0x0 0x1000>;
1621 #address-cells = <1>;
1623 status = "disabled";
1625 pcs16: ethernet-phy@0 {
1630 pcs_mdio17: mdio@8c47000 {
1631 compatible = "fsl,fman-memac-mdio";
1632 reg = <0x0 0x8c47000 0x0 0x1000>;
1634 #address-cells = <1>;
1636 status = "disabled";
1638 pcs17: ethernet-phy@0 {
1643 pcs_mdio18: mdio@8c4b000 {
1644 compatible = "fsl,fman-memac-mdio";
1645 reg = <0x0 0x8c4b000 0x0 0x1000>;
1647 #address-cells = <1>;
1649 status = "disabled";
1651 pcs18: ethernet-phy@0 {
1656 fsl_mc: fsl-mc@80c000000 {
1657 compatible = "fsl,qoriq-mc";
1658 reg = <0x00000008 0x0c000000 0 0x40>,
1659 <0x00000000 0x08340000 0 0x40000>;
1660 msi-parent = <&its>;
1661 /* iommu-map property is fixed up by u-boot */
1662 iommu-map = <0 &smmu 0 0>;
1664 #address-cells = <3>;
1668 * Region type 0x0 - MC portals
1669 * Region type 0x1 - QBMAN portals
1671 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1672 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1675 * Define the maximum number of MACs present on the SoC.
1678 #address-cells = <1>;
1681 dpmac1: ethernet@1 {
1682 compatible = "fsl,qoriq-mc-dpmac";
1684 pcs-handle = <&pcs1>;
1687 dpmac2: ethernet@2 {
1688 compatible = "fsl,qoriq-mc-dpmac";
1690 pcs-handle = <&pcs2>;
1693 dpmac3: ethernet@3 {
1694 compatible = "fsl,qoriq-mc-dpmac";
1696 pcs-handle = <&pcs3>;
1699 dpmac4: ethernet@4 {
1700 compatible = "fsl,qoriq-mc-dpmac";
1702 pcs-handle = <&pcs4>;
1705 dpmac5: ethernet@5 {
1706 compatible = "fsl,qoriq-mc-dpmac";
1708 pcs-handle = <&pcs5>;
1711 dpmac6: ethernet@6 {
1712 compatible = "fsl,qoriq-mc-dpmac";
1714 pcs-handle = <&pcs6>;
1717 dpmac7: ethernet@7 {
1718 compatible = "fsl,qoriq-mc-dpmac";
1720 pcs-handle = <&pcs7>;
1723 dpmac8: ethernet@8 {
1724 compatible = "fsl,qoriq-mc-dpmac";
1726 pcs-handle = <&pcs8>;
1729 dpmac9: ethernet@9 {
1730 compatible = "fsl,qoriq-mc-dpmac";
1732 pcs-handle = <&pcs9>;
1735 dpmac10: ethernet@a {
1736 compatible = "fsl,qoriq-mc-dpmac";
1738 pcs-handle = <&pcs10>;
1741 dpmac11: ethernet@b {
1742 compatible = "fsl,qoriq-mc-dpmac";
1744 pcs-handle = <&pcs11>;
1747 dpmac12: ethernet@c {
1748 compatible = "fsl,qoriq-mc-dpmac";
1750 pcs-handle = <&pcs12>;
1753 dpmac13: ethernet@d {
1754 compatible = "fsl,qoriq-mc-dpmac";
1756 pcs-handle = <&pcs13>;
1759 dpmac14: ethernet@e {
1760 compatible = "fsl,qoriq-mc-dpmac";
1762 pcs-handle = <&pcs14>;
1765 dpmac15: ethernet@f {
1766 compatible = "fsl,qoriq-mc-dpmac";
1768 pcs-handle = <&pcs15>;
1771 dpmac16: ethernet@10 {
1772 compatible = "fsl,qoriq-mc-dpmac";
1774 pcs-handle = <&pcs16>;
1777 dpmac17: ethernet@11 {
1778 compatible = "fsl,qoriq-mc-dpmac";
1780 pcs-handle = <&pcs17>;
1783 dpmac18: ethernet@12 {
1784 compatible = "fsl,qoriq-mc-dpmac";
1786 pcs-handle = <&pcs18>;
1794 compatible = "linaro,optee-tz";
1796 status = "disabled";