1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2016 Freescale Semiconductor, Inc.
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 compatible = "fsl,ls2080a";
17 interrupt-parent = <&gic>;
33 device_type = "memory";
34 reg = <0x00000000 0x80000000 0 0x80000000>;
35 /* DRAM space - 1, size : 2 GB DRAM */
39 compatible = "fixed-clock";
41 clock-frequency = <100000000>;
42 clock-output-names = "sysclk";
45 gic: interrupt-controller@6000000 {
46 compatible = "arm,gic-v3";
47 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
48 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
49 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
50 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
51 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
52 #interrupt-cells = <3>;
57 interrupts = <1 9 0x4>;
59 its: gic-its@6020000 {
60 compatible = "arm,gic-v3-its";
62 reg = <0x0 0x6020000 0 0x20000>;
66 rstcr: syscon@1e60000 {
67 compatible = "fsl,ls2080a-rstcr", "syscon";
68 reg = <0x0 0x1e60000 0x0 0x4>;
72 compatible ="syscon-reboot";
79 cpu_thermal: cpu-thermal {
80 polling-delay-passive = <1000>;
81 polling-delay = <5000>;
83 thermal-sensors = <&tmu 4>;
86 cpu_alert: cpu-alert {
87 temperature = <75000>;
92 temperature = <85000>;
102 <&cpu0 THERMAL_NO_LIMIT
108 <&cpu2 THERMAL_NO_LIMIT
114 <&cpu4 THERMAL_NO_LIMIT
120 <&cpu6 THERMAL_NO_LIMIT
128 compatible = "arm,armv8-timer";
129 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
130 <1 14 4>, /* Physical Non-Secure PPI, active-low */
131 <1 11 4>, /* Virtual PPI, active-low */
132 <1 10 4>; /* Hypervisor PPI, active-low */
137 compatible = "arm,armv8-pmuv3";
138 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
142 compatible = "arm,psci-0.2";
147 compatible = "simple-bus";
148 #address-cells = <2>;
152 clockgen: clocking@1300000 {
153 compatible = "fsl,ls2080a-clockgen";
154 reg = <0 0x1300000 0 0xa0000>;
160 compatible = "fsl,ls2080a-dcfg", "syscon";
161 reg = <0x0 0x1e00000 0x0 0x10000>;
166 compatible = "fsl,qoriq-tmu";
167 reg = <0x0 0x1f80000 0x0 0x10000>;
168 interrupts = <0 23 0x4>;
169 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
170 fsl,tmu-calibration = <0x00000000 0x00000026
171 0x00000001 0x0000002d
172 0x00000002 0x00000032
173 0x00000003 0x00000039
174 0x00000004 0x0000003f
175 0x00000005 0x00000046
176 0x00000006 0x0000004d
177 0x00000007 0x00000054
178 0x00000008 0x0000005a
179 0x00000009 0x00000061
180 0x0000000a 0x0000006a
181 0x0000000b 0x00000071
183 0x00010000 0x00000025
184 0x00010001 0x0000002c
185 0x00010002 0x00000035
186 0x00010003 0x0000003d
187 0x00010004 0x00000045
188 0x00010005 0x0000004e
189 0x00010006 0x00000057
190 0x00010007 0x00000061
191 0x00010008 0x0000006b
192 0x00010009 0x00000076
194 0x00020000 0x00000029
195 0x00020001 0x00000033
196 0x00020002 0x0000003d
197 0x00020003 0x00000049
198 0x00020004 0x00000056
199 0x00020005 0x00000061
200 0x00020006 0x0000006d
202 0x00030000 0x00000021
203 0x00030001 0x0000002a
204 0x00030002 0x0000003c
205 0x00030003 0x0000004e>;
207 #thermal-sensor-cells = <1>;
210 serial0: serial@21c0500 {
211 compatible = "fsl,ns16550", "ns16550a";
212 reg = <0x0 0x21c0500 0x0 0x100>;
213 clocks = <&clockgen 4 3>;
214 interrupts = <0 32 0x4>; /* Level high type */
217 serial1: serial@21c0600 {
218 compatible = "fsl,ns16550", "ns16550a";
219 reg = <0x0 0x21c0600 0x0 0x100>;
220 clocks = <&clockgen 4 3>;
221 interrupts = <0 32 0x4>; /* Level high type */
224 cluster1_core0_watchdog: wdt@c000000 {
225 compatible = "arm,sp805", "arm,primecell";
226 reg = <0x0 0xc000000 0x0 0x1000>;
227 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
228 clock-names = "apb_pclk", "wdog_clk";
231 cluster1_core1_watchdog: wdt@c010000 {
232 compatible = "arm,sp805", "arm,primecell";
233 reg = <0x0 0xc010000 0x0 0x1000>;
234 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
235 clock-names = "apb_pclk", "wdog_clk";
238 cluster2_core0_watchdog: wdt@c100000 {
239 compatible = "arm,sp805", "arm,primecell";
240 reg = <0x0 0xc100000 0x0 0x1000>;
241 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
242 clock-names = "apb_pclk", "wdog_clk";
245 cluster2_core1_watchdog: wdt@c110000 {
246 compatible = "arm,sp805", "arm,primecell";
247 reg = <0x0 0xc110000 0x0 0x1000>;
248 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
249 clock-names = "apb_pclk", "wdog_clk";
252 cluster3_core0_watchdog: wdt@c200000 {
253 compatible = "arm,sp805", "arm,primecell";
254 reg = <0x0 0xc200000 0x0 0x1000>;
255 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
256 clock-names = "apb_pclk", "wdog_clk";
259 cluster3_core1_watchdog: wdt@c210000 {
260 compatible = "arm,sp805", "arm,primecell";
261 reg = <0x0 0xc210000 0x0 0x1000>;
262 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
263 clock-names = "apb_pclk", "wdog_clk";
266 cluster4_core0_watchdog: wdt@c300000 {
267 compatible = "arm,sp805", "arm,primecell";
268 reg = <0x0 0xc300000 0x0 0x1000>;
269 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
270 clock-names = "apb_pclk", "wdog_clk";
273 cluster4_core1_watchdog: wdt@c310000 {
274 compatible = "arm,sp805", "arm,primecell";
275 reg = <0x0 0xc310000 0x0 0x1000>;
276 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
277 clock-names = "apb_pclk", "wdog_clk";
280 crypto: crypto@8000000 {
281 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
283 #address-cells = <1>;
285 ranges = <0x0 0x00 0x8000000 0x100000>;
286 reg = <0x00 0x8000000 0x0 0x100000>;
287 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
291 compatible = "fsl,sec-v5.0-job-ring",
292 "fsl,sec-v4.0-job-ring";
293 reg = <0x10000 0x10000>;
294 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
298 compatible = "fsl,sec-v5.0-job-ring",
299 "fsl,sec-v4.0-job-ring";
300 reg = <0x20000 0x10000>;
301 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
305 compatible = "fsl,sec-v5.0-job-ring",
306 "fsl,sec-v4.0-job-ring";
307 reg = <0x30000 0x10000>;
308 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
312 compatible = "fsl,sec-v5.0-job-ring",
313 "fsl,sec-v4.0-job-ring";
314 reg = <0x40000 0x10000>;
315 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
319 fsl_mc: fsl-mc@80c000000 {
320 compatible = "fsl,qoriq-mc";
321 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
322 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
324 #address-cells = <3>;
328 * Region type 0x0 - MC portals
329 * Region type 0x1 - QBMAN portals
331 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
332 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
335 * Define the maximum number of MACs present on the SoC.
338 #address-cells = <1>;
342 compatible = "fsl,qoriq-mc-dpmac";
347 compatible = "fsl,qoriq-mc-dpmac";
352 compatible = "fsl,qoriq-mc-dpmac";
357 compatible = "fsl,qoriq-mc-dpmac";
362 compatible = "fsl,qoriq-mc-dpmac";
367 compatible = "fsl,qoriq-mc-dpmac";
372 compatible = "fsl,qoriq-mc-dpmac";
377 compatible = "fsl,qoriq-mc-dpmac";
382 compatible = "fsl,qoriq-mc-dpmac";
387 compatible = "fsl,qoriq-mc-dpmac";
392 compatible = "fsl,qoriq-mc-dpmac";
397 compatible = "fsl,qoriq-mc-dpmac";
402 compatible = "fsl,qoriq-mc-dpmac";
407 compatible = "fsl,qoriq-mc-dpmac";
412 compatible = "fsl,qoriq-mc-dpmac";
417 compatible = "fsl,qoriq-mc-dpmac";
423 smmu: iommu@5000000 {
424 compatible = "arm,mmu-500";
425 reg = <0 0x5000000 0 0x800000>;
426 #global-interrupts = <12>;
427 interrupts = <0 13 4>, /* global secure fault */
428 <0 14 4>, /* combined secure interrupt */
429 <0 15 4>, /* global non-secure fault */
430 <0 16 4>, /* combined non-secure interrupt */
431 /* performance counter interrupts 0-7 */
432 <0 211 4>, <0 212 4>,
433 <0 213 4>, <0 214 4>,
434 <0 215 4>, <0 216 4>,
435 <0 217 4>, <0 218 4>,
436 /* per context interrupt, 64 interrupts */
437 <0 146 4>, <0 147 4>,
438 <0 148 4>, <0 149 4>,
439 <0 150 4>, <0 151 4>,
440 <0 152 4>, <0 153 4>,
441 <0 154 4>, <0 155 4>,
442 <0 156 4>, <0 157 4>,
443 <0 158 4>, <0 159 4>,
444 <0 160 4>, <0 161 4>,
445 <0 162 4>, <0 163 4>,
446 <0 164 4>, <0 165 4>,
447 <0 166 4>, <0 167 4>,
448 <0 168 4>, <0 169 4>,
449 <0 170 4>, <0 171 4>,
450 <0 172 4>, <0 173 4>,
451 <0 174 4>, <0 175 4>,
452 <0 176 4>, <0 177 4>,
453 <0 178 4>, <0 179 4>,
454 <0 180 4>, <0 181 4>,
455 <0 182 4>, <0 183 4>,
456 <0 184 4>, <0 185 4>,
457 <0 186 4>, <0 187 4>,
458 <0 188 4>, <0 189 4>,
459 <0 190 4>, <0 191 4>,
460 <0 192 4>, <0 193 4>,
461 <0 194 4>, <0 195 4>,
462 <0 196 4>, <0 197 4>,
463 <0 198 4>, <0 199 4>,
464 <0 200 4>, <0 201 4>,
465 <0 202 4>, <0 203 4>,
466 <0 204 4>, <0 205 4>,
467 <0 206 4>, <0 207 4>,
468 <0 208 4>, <0 209 4>;
469 mmu-masters = <&fsl_mc 0x300 0>;
474 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
475 #address-cells = <1>;
477 reg = <0x0 0x2100000 0x0 0x10000>;
478 interrupts = <0 26 0x4>; /* Level high type */
479 clocks = <&clockgen 4 3>;
480 clock-names = "dspi";
481 spi-num-chipselects = <5>;
484 esdhc: esdhc@2140000 {
486 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
487 reg = <0x0 0x2140000 0x0 0x10000>;
488 interrupts = <0 28 0x4>; /* Level high type */
489 clocks = <&clockgen 4 1>;
490 voltage-ranges = <1800 1800 3300 3300>;
496 gpio0: gpio@2300000 {
497 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
498 reg = <0x0 0x2300000 0x0 0x10000>;
499 interrupts = <0 36 0x4>; /* Level high type */
503 interrupt-controller;
504 #interrupt-cells = <2>;
507 gpio1: gpio@2310000 {
508 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
509 reg = <0x0 0x2310000 0x0 0x10000>;
510 interrupts = <0 36 0x4>; /* Level high type */
514 interrupt-controller;
515 #interrupt-cells = <2>;
518 gpio2: gpio@2320000 {
519 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
520 reg = <0x0 0x2320000 0x0 0x10000>;
521 interrupts = <0 37 0x4>; /* Level high type */
525 interrupt-controller;
526 #interrupt-cells = <2>;
529 gpio3: gpio@2330000 {
530 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
531 reg = <0x0 0x2330000 0x0 0x10000>;
532 interrupts = <0 37 0x4>; /* Level high type */
536 interrupt-controller;
537 #interrupt-cells = <2>;
542 compatible = "fsl,vf610-i2c";
543 #address-cells = <1>;
545 reg = <0x0 0x2000000 0x0 0x10000>;
546 interrupts = <0 34 0x4>; /* Level high type */
548 clocks = <&clockgen 4 3>;
553 compatible = "fsl,vf610-i2c";
554 #address-cells = <1>;
556 reg = <0x0 0x2010000 0x0 0x10000>;
557 interrupts = <0 34 0x4>; /* Level high type */
559 clocks = <&clockgen 4 3>;
564 compatible = "fsl,vf610-i2c";
565 #address-cells = <1>;
567 reg = <0x0 0x2020000 0x0 0x10000>;
568 interrupts = <0 35 0x4>; /* Level high type */
570 clocks = <&clockgen 4 3>;
575 compatible = "fsl,vf610-i2c";
576 #address-cells = <1>;
578 reg = <0x0 0x2030000 0x0 0x10000>;
579 interrupts = <0 35 0x4>; /* Level high type */
581 clocks = <&clockgen 4 3>;
585 compatible = "fsl,ifc", "simple-bus";
586 reg = <0x0 0x2240000 0x0 0x20000>;
587 interrupts = <0 21 0x4>; /* Level high type */
589 #address-cells = <2>;
592 ranges = <0 0 0x5 0x80000000 0x08000000
593 2 0 0x5 0x30000000 0x00010000
594 3 0 0x5 0x20000000 0x00010000>;
599 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
600 #address-cells = <1>;
602 reg = <0x0 0x20c0000 0x0 0x10000>,
603 <0x0 0x20000000 0x0 0x10000000>;
604 reg-names = "QuadSPI", "QuadSPI-memory";
605 interrupts = <0 25 0x4>; /* Level high type */
606 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
607 clock-names = "qspi_en", "qspi";
610 pcie1: pcie@3400000 {
611 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
613 reg-names = "regs", "config";
614 interrupts = <0 108 0x4>; /* Level high type */
615 interrupt-names = "intr";
616 #address-cells = <3>;
621 bus-range = <0x0 0xff>;
623 #interrupt-cells = <1>;
624 interrupt-map-mask = <0 0 0 7>;
625 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
626 <0000 0 0 2 &gic 0 0 0 110 4>,
627 <0000 0 0 3 &gic 0 0 0 111 4>,
628 <0000 0 0 4 &gic 0 0 0 112 4>;
631 pcie2: pcie@3500000 {
632 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
634 reg-names = "regs", "config";
635 interrupts = <0 113 0x4>; /* Level high type */
636 interrupt-names = "intr";
637 #address-cells = <3>;
642 bus-range = <0x0 0xff>;
644 #interrupt-cells = <1>;
645 interrupt-map-mask = <0 0 0 7>;
646 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
647 <0000 0 0 2 &gic 0 0 0 115 4>,
648 <0000 0 0 3 &gic 0 0 0 116 4>,
649 <0000 0 0 4 &gic 0 0 0 117 4>;
652 pcie3: pcie@3600000 {
653 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
655 reg-names = "regs", "config";
656 interrupts = <0 118 0x4>; /* Level high type */
657 interrupt-names = "intr";
658 #address-cells = <3>;
663 bus-range = <0x0 0xff>;
665 #interrupt-cells = <1>;
666 interrupt-map-mask = <0 0 0 7>;
667 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
668 <0000 0 0 2 &gic 0 0 0 120 4>,
669 <0000 0 0 3 &gic 0 0 0 121 4>,
670 <0000 0 0 4 &gic 0 0 0 122 4>;
673 pcie4: pcie@3700000 {
674 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
676 reg-names = "regs", "config";
677 interrupts = <0 123 0x4>; /* Level high type */
678 interrupt-names = "intr";
679 #address-cells = <3>;
684 bus-range = <0x0 0xff>;
686 #interrupt-cells = <1>;
687 interrupt-map-mask = <0 0 0 7>;
688 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
689 <0000 0 0 2 &gic 0 0 0 125 4>,
690 <0000 0 0 3 &gic 0 0 0 126 4>,
691 <0000 0 0 4 &gic 0 0 0 127 4>;
694 sata0: sata@3200000 {
696 compatible = "fsl,ls2080a-ahci";
697 reg = <0x0 0x3200000 0x0 0x10000>;
698 interrupts = <0 133 0x4>; /* Level high type */
699 clocks = <&clockgen 4 3>;
703 sata1: sata@3210000 {
705 compatible = "fsl,ls2080a-ahci";
706 reg = <0x0 0x3210000 0x0 0x10000>;
707 interrupts = <0 136 0x4>; /* Level high type */
708 clocks = <&clockgen 4 3>;
714 compatible = "snps,dwc3";
715 reg = <0x0 0x3100000 0x0 0x10000>;
716 interrupts = <0 80 0x4>; /* Level high type */
718 snps,quirk-frame-length-adjustment = <0x20>;
719 snps,dis_rxdet_inp3_quirk;
724 compatible = "snps,dwc3";
725 reg = <0x0 0x3110000 0x0 0x10000>;
726 interrupts = <0 81 0x4>; /* Level high type */
728 snps,quirk-frame-length-adjustment = <0x20>;
729 snps,dis_rxdet_inp3_quirk;
733 compatible = "arm,ccn-504";
734 reg = <0x0 0x04000000 0x0 0x01000000>;
735 interrupts = <0 12 4>;
739 ddr1: memory-controller@1080000 {
740 compatible = "fsl,qoriq-memory-controller";
741 reg = <0x0 0x1080000 0x0 0x1000>;
742 interrupts = <0 17 0x4>;
746 ddr2: memory-controller@1090000 {
747 compatible = "fsl,qoriq-memory-controller";
748 reg = <0x0 0x1090000 0x0 0x1000>;
749 interrupts = <0 18 0x4>;
755 compatible = "linaro,optee-tz";