2 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 * Copyright (C) 2014-2015, Freescale Semiconductor
6 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls2080a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
64 /* We have 4 clusters having 2 Cortex-A57 cores each */
67 compatible = "arm,cortex-a57";
69 clocks = <&clockgen 1 0>;
70 next-level-cache = <&cluster0_l2>;
75 compatible = "arm,cortex-a57";
77 clocks = <&clockgen 1 0>;
78 next-level-cache = <&cluster0_l2>;
83 compatible = "arm,cortex-a57";
85 clocks = <&clockgen 1 1>;
86 next-level-cache = <&cluster1_l2>;
91 compatible = "arm,cortex-a57";
93 clocks = <&clockgen 1 1>;
94 next-level-cache = <&cluster1_l2>;
99 compatible = "arm,cortex-a57";
101 clocks = <&clockgen 1 2>;
102 next-level-cache = <&cluster2_l2>;
107 compatible = "arm,cortex-a57";
109 clocks = <&clockgen 1 2>;
110 next-level-cache = <&cluster2_l2>;
115 compatible = "arm,cortex-a57";
117 clocks = <&clockgen 1 3>;
118 next-level-cache = <&cluster3_l2>;
123 compatible = "arm,cortex-a57";
125 clocks = <&clockgen 1 3>;
126 next-level-cache = <&cluster3_l2>;
129 cluster0_l2: l2-cache0 {
130 compatible = "cache";
133 cluster1_l2: l2-cache1 {
134 compatible = "cache";
137 cluster2_l2: l2-cache2 {
138 compatible = "cache";
141 cluster3_l2: l2-cache3 {
142 compatible = "cache";
147 device_type = "memory";
148 reg = <0x00000000 0x80000000 0 0x80000000>;
149 /* DRAM space - 1, size : 2 GB DRAM */
153 compatible = "fixed-clock";
155 clock-frequency = <100000000>;
156 clock-output-names = "sysclk";
159 gic: interrupt-controller@6000000 {
160 compatible = "arm,gic-v3";
161 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
162 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
163 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
164 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
165 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
166 #interrupt-cells = <3>;
167 #address-cells = <2>;
170 interrupt-controller;
171 interrupts = <1 9 0x4>;
173 its: gic-its@6020000 {
174 compatible = "arm,gic-v3-its";
176 reg = <0x0 0x6020000 0 0x20000>;
180 rstcr: syscon@1e60000 {
181 compatible = "fsl,ls2080a-rstcr", "syscon";
182 reg = <0x0 0x1e60000 0x0 0x4>;
186 compatible ="syscon-reboot";
193 compatible = "arm,armv8-timer";
194 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
195 <1 14 4>, /* Physical Non-Secure PPI, active-low */
196 <1 11 4>, /* Virtual PPI, active-low */
197 <1 10 4>; /* Hypervisor PPI, active-low */
202 compatible = "arm,armv8-pmuv3";
203 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
207 compatible = "simple-bus";
208 #address-cells = <2>;
212 clockgen: clocking@1300000 {
213 compatible = "fsl,ls2080a-clockgen";
214 reg = <0 0x1300000 0 0xa0000>;
219 serial0: serial@21c0500 {
220 compatible = "fsl,ns16550", "ns16550a";
221 reg = <0x0 0x21c0500 0x0 0x100>;
222 clocks = <&clockgen 4 3>;
223 interrupts = <0 32 0x4>; /* Level high type */
226 serial1: serial@21c0600 {
227 compatible = "fsl,ns16550", "ns16550a";
228 reg = <0x0 0x21c0600 0x0 0x100>;
229 clocks = <&clockgen 4 3>;
230 interrupts = <0 32 0x4>; /* Level high type */
233 cluster1_core0_watchdog: wdt@c000000 {
234 compatible = "arm,sp805-wdt", "arm,primecell";
235 reg = <0x0 0xc000000 0x0 0x1000>;
236 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
237 clock-names = "apb_pclk", "wdog_clk";
240 cluster1_core1_watchdog: wdt@c010000 {
241 compatible = "arm,sp805-wdt", "arm,primecell";
242 reg = <0x0 0xc010000 0x0 0x1000>;
243 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
244 clock-names = "apb_pclk", "wdog_clk";
247 cluster2_core0_watchdog: wdt@c100000 {
248 compatible = "arm,sp805-wdt", "arm,primecell";
249 reg = <0x0 0xc100000 0x0 0x1000>;
250 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
251 clock-names = "apb_pclk", "wdog_clk";
254 cluster2_core1_watchdog: wdt@c110000 {
255 compatible = "arm,sp805-wdt", "arm,primecell";
256 reg = <0x0 0xc110000 0x0 0x1000>;
257 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
258 clock-names = "apb_pclk", "wdog_clk";
261 cluster3_core0_watchdog: wdt@c200000 {
262 compatible = "arm,sp805-wdt", "arm,primecell";
263 reg = <0x0 0xc200000 0x0 0x1000>;
264 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
265 clock-names = "apb_pclk", "wdog_clk";
268 cluster3_core1_watchdog: wdt@c210000 {
269 compatible = "arm,sp805-wdt", "arm,primecell";
270 reg = <0x0 0xc210000 0x0 0x1000>;
271 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
272 clock-names = "apb_pclk", "wdog_clk";
275 cluster4_core0_watchdog: wdt@c300000 {
276 compatible = "arm,sp805-wdt", "arm,primecell";
277 reg = <0x0 0xc300000 0x0 0x1000>;
278 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
279 clock-names = "apb_pclk", "wdog_clk";
282 cluster4_core1_watchdog: wdt@c310000 {
283 compatible = "arm,sp805-wdt", "arm,primecell";
284 reg = <0x0 0xc310000 0x0 0x1000>;
285 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
286 clock-names = "apb_pclk", "wdog_clk";
289 fsl_mc: fsl-mc@80c000000 {
290 compatible = "fsl,qoriq-mc";
291 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
292 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
294 #address-cells = <3>;
298 * Region type 0x0 - MC portals
299 * Region type 0x1 - QBMAN portals
301 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
302 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
305 * Define the maximum number of MACs present on the SoC.
308 #address-cells = <1>;
312 compatible = "fsl,qoriq-mc-dpmac";
317 compatible = "fsl,qoriq-mc-dpmac";
322 compatible = "fsl,qoriq-mc-dpmac";
327 compatible = "fsl,qoriq-mc-dpmac";
332 compatible = "fsl,qoriq-mc-dpmac";
337 compatible = "fsl,qoriq-mc-dpmac";
342 compatible = "fsl,qoriq-mc-dpmac";
347 compatible = "fsl,qoriq-mc-dpmac";
352 compatible = "fsl,qoriq-mc-dpmac";
357 compatible = "fsl,qoriq-mc-dpmac";
362 compatible = "fsl,qoriq-mc-dpmac";
367 compatible = "fsl,qoriq-mc-dpmac";
372 compatible = "fsl,qoriq-mc-dpmac";
377 compatible = "fsl,qoriq-mc-dpmac";
382 compatible = "fsl,qoriq-mc-dpmac";
387 compatible = "fsl,qoriq-mc-dpmac";
393 smmu: iommu@5000000 {
394 compatible = "arm,mmu-500";
395 reg = <0 0x5000000 0 0x800000>;
396 #global-interrupts = <12>;
397 interrupts = <0 13 4>, /* global secure fault */
398 <0 14 4>, /* combined secure interrupt */
399 <0 15 4>, /* global non-secure fault */
400 <0 16 4>, /* combined non-secure interrupt */
401 /* performance counter interrupts 0-7 */
402 <0 211 4>, <0 212 4>,
403 <0 213 4>, <0 214 4>,
404 <0 215 4>, <0 216 4>,
405 <0 217 4>, <0 218 4>,
406 /* per context interrupt, 64 interrupts */
407 <0 146 4>, <0 147 4>,
408 <0 148 4>, <0 149 4>,
409 <0 150 4>, <0 151 4>,
410 <0 152 4>, <0 153 4>,
411 <0 154 4>, <0 155 4>,
412 <0 156 4>, <0 157 4>,
413 <0 158 4>, <0 159 4>,
414 <0 160 4>, <0 161 4>,
415 <0 162 4>, <0 163 4>,
416 <0 164 4>, <0 165 4>,
417 <0 166 4>, <0 167 4>,
418 <0 168 4>, <0 169 4>,
419 <0 170 4>, <0 171 4>,
420 <0 172 4>, <0 173 4>,
421 <0 174 4>, <0 175 4>,
422 <0 176 4>, <0 177 4>,
423 <0 178 4>, <0 179 4>,
424 <0 180 4>, <0 181 4>,
425 <0 182 4>, <0 183 4>,
426 <0 184 4>, <0 185 4>,
427 <0 186 4>, <0 187 4>,
428 <0 188 4>, <0 189 4>,
429 <0 190 4>, <0 191 4>,
430 <0 192 4>, <0 193 4>,
431 <0 194 4>, <0 195 4>,
432 <0 196 4>, <0 197 4>,
433 <0 198 4>, <0 199 4>,
434 <0 200 4>, <0 201 4>,
435 <0 202 4>, <0 203 4>,
436 <0 204 4>, <0 205 4>,
437 <0 206 4>, <0 207 4>,
438 <0 208 4>, <0 209 4>;
439 mmu-masters = <&fsl_mc 0x300 0>;
444 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
445 #address-cells = <1>;
447 reg = <0x0 0x2100000 0x0 0x10000>;
448 interrupts = <0 26 0x4>; /* Level high type */
449 clocks = <&clockgen 4 3>;
450 clock-names = "dspi";
451 spi-num-chipselects = <5>;
455 esdhc: esdhc@2140000 {
457 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
458 reg = <0x0 0x2140000 0x0 0x10000>;
459 interrupts = <0 28 0x4>; /* Level high type */
460 clock-frequency = <0>; /* Updated by bootloader */
461 voltage-ranges = <1800 1800 3300 3300>;
467 gpio0: gpio@2300000 {
468 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
469 reg = <0x0 0x2300000 0x0 0x10000>;
470 interrupts = <0 36 0x4>; /* Level high type */
474 interrupt-controller;
475 #interrupt-cells = <2>;
478 gpio1: gpio@2310000 {
479 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
480 reg = <0x0 0x2310000 0x0 0x10000>;
481 interrupts = <0 36 0x4>; /* Level high type */
485 interrupt-controller;
486 #interrupt-cells = <2>;
489 gpio2: gpio@2320000 {
490 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
491 reg = <0x0 0x2320000 0x0 0x10000>;
492 interrupts = <0 37 0x4>; /* Level high type */
496 interrupt-controller;
497 #interrupt-cells = <2>;
500 gpio3: gpio@2330000 {
501 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
502 reg = <0x0 0x2330000 0x0 0x10000>;
503 interrupts = <0 37 0x4>; /* Level high type */
507 interrupt-controller;
508 #interrupt-cells = <2>;
513 compatible = "fsl,vf610-i2c";
514 #address-cells = <1>;
516 reg = <0x0 0x2000000 0x0 0x10000>;
517 interrupts = <0 34 0x4>; /* Level high type */
519 clocks = <&clockgen 4 3>;
524 compatible = "fsl,vf610-i2c";
525 #address-cells = <1>;
527 reg = <0x0 0x2010000 0x0 0x10000>;
528 interrupts = <0 34 0x4>; /* Level high type */
530 clocks = <&clockgen 4 3>;
535 compatible = "fsl,vf610-i2c";
536 #address-cells = <1>;
538 reg = <0x0 0x2020000 0x0 0x10000>;
539 interrupts = <0 35 0x4>; /* Level high type */
541 clocks = <&clockgen 4 3>;
546 compatible = "fsl,vf610-i2c";
547 #address-cells = <1>;
549 reg = <0x0 0x2030000 0x0 0x10000>;
550 interrupts = <0 35 0x4>; /* Level high type */
552 clocks = <&clockgen 4 3>;
556 compatible = "fsl,ifc", "simple-bus";
557 reg = <0x0 0x2240000 0x0 0x20000>;
558 interrupts = <0 21 0x4>; /* Level high type */
560 #address-cells = <2>;
563 ranges = <0 0 0x5 0x80000000 0x08000000
564 2 0 0x5 0x30000000 0x00010000
565 3 0 0x5 0x20000000 0x00010000>;
568 qspi: quadspi@20c0000 {
570 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
571 #address-cells = <1>;
573 reg = <0x0 0x20c0000 0x0 0x10000>,
574 <0x0 0x20000000 0x0 0x10000000>;
575 reg-names = "QuadSPI", "QuadSPI-memory";
576 interrupts = <0 25 0x4>; /* Level high type */
577 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
578 clock-names = "qspi_en", "qspi";
582 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
584 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
585 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
586 reg-names = "regs", "config";
587 interrupts = <0 108 0x4>; /* Level high type */
588 interrupt-names = "intr";
589 #address-cells = <3>;
594 bus-range = <0x0 0xff>;
595 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
596 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
598 #interrupt-cells = <1>;
599 interrupt-map-mask = <0 0 0 7>;
600 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
601 <0000 0 0 2 &gic 0 0 0 110 4>,
602 <0000 0 0 3 &gic 0 0 0 111 4>,
603 <0000 0 0 4 &gic 0 0 0 112 4>;
607 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
609 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
610 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
611 reg-names = "regs", "config";
612 interrupts = <0 113 0x4>; /* Level high type */
613 interrupt-names = "intr";
614 #address-cells = <3>;
619 bus-range = <0x0 0xff>;
620 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
621 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
623 #interrupt-cells = <1>;
624 interrupt-map-mask = <0 0 0 7>;
625 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
626 <0000 0 0 2 &gic 0 0 0 115 4>,
627 <0000 0 0 3 &gic 0 0 0 116 4>,
628 <0000 0 0 4 &gic 0 0 0 117 4>;
632 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
634 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
635 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
636 reg-names = "regs", "config";
637 interrupts = <0 118 0x4>; /* Level high type */
638 interrupt-names = "intr";
639 #address-cells = <3>;
644 bus-range = <0x0 0xff>;
645 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
646 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
648 #interrupt-cells = <1>;
649 interrupt-map-mask = <0 0 0 7>;
650 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
651 <0000 0 0 2 &gic 0 0 0 120 4>,
652 <0000 0 0 3 &gic 0 0 0 121 4>,
653 <0000 0 0 4 &gic 0 0 0 122 4>;
657 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
659 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
660 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
661 reg-names = "regs", "config";
662 interrupts = <0 123 0x4>; /* Level high type */
663 interrupt-names = "intr";
664 #address-cells = <3>;
669 bus-range = <0x0 0xff>;
670 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
671 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
673 #interrupt-cells = <1>;
674 interrupt-map-mask = <0 0 0 7>;
675 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
676 <0000 0 0 2 &gic 0 0 0 125 4>,
677 <0000 0 0 3 &gic 0 0 0 126 4>,
678 <0000 0 0 4 &gic 0 0 0 127 4>;
681 sata0: sata@3200000 {
683 compatible = "fsl,ls2080a-ahci";
684 reg = <0x0 0x3200000 0x0 0x10000>;
685 interrupts = <0 133 0x4>; /* Level high type */
686 clocks = <&clockgen 4 3>;
690 sata1: sata@3210000 {
692 compatible = "fsl,ls2080a-ahci";
693 reg = <0x0 0x3210000 0x0 0x10000>;
694 interrupts = <0 136 0x4>; /* Level high type */
695 clocks = <&clockgen 4 3>;
701 compatible = "snps,dwc3";
702 reg = <0x0 0x3100000 0x0 0x10000>;
703 interrupts = <0 80 0x4>; /* Level high type */
705 snps,quirk-frame-length-adjustment = <0x20>;
706 snps,dis_rxdet_inp3_quirk;
711 compatible = "snps,dwc3";
712 reg = <0x0 0x3110000 0x0 0x10000>;
713 interrupts = <0 81 0x4>; /* Level high type */
715 snps,quirk-frame-length-adjustment = <0x20>;
716 snps,dis_rxdet_inp3_quirk;
720 compatible = "arm,ccn-504";
721 reg = <0x0 0x04000000 0x0 0x01000000>;
722 interrupts = <0 12 4>;
726 ddr1: memory-controller@1080000 {
727 compatible = "fsl,qoriq-memory-controller";
728 reg = <0x0 0x1080000 0x0 0x1000>;
729 interrupts = <0 17 0x4>;
733 ddr2: memory-controller@1090000 {
734 compatible = "fsl,qoriq-memory-controller";
735 reg = <0x0 0x1090000 0x0 0x1000>;
736 interrupts = <0 18 0x4>;