2 * Device Tree Include file for NXP Layerscape-1088A family SoC.
6 * Harninder Rai <harninder.rai@nxp.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/thermal/thermal.h>
50 compatible = "fsl,ls1088a";
51 interrupt-parent = <&gic>;
63 /* We have 2 clusters having 4 Cortex-A53 cores each */
66 compatible = "arm,cortex-a53";
68 clocks = <&clockgen 1 0>;
69 cpu-idle-states = <&CPU_PH20>;
75 compatible = "arm,cortex-a53";
77 clocks = <&clockgen 1 0>;
78 cpu-idle-states = <&CPU_PH20>;
83 compatible = "arm,cortex-a53";
85 clocks = <&clockgen 1 0>;
86 cpu-idle-states = <&CPU_PH20>;
91 compatible = "arm,cortex-a53";
93 clocks = <&clockgen 1 0>;
94 cpu-idle-states = <&CPU_PH20>;
99 compatible = "arm,cortex-a53";
101 clocks = <&clockgen 1 1>;
102 cpu-idle-states = <&CPU_PH20>;
103 #cooling-cells = <2>;
108 compatible = "arm,cortex-a53";
110 clocks = <&clockgen 1 1>;
111 cpu-idle-states = <&CPU_PH20>;
116 compatible = "arm,cortex-a53";
118 clocks = <&clockgen 1 1>;
119 cpu-idle-states = <&CPU_PH20>;
124 compatible = "arm,cortex-a53";
126 clocks = <&clockgen 1 1>;
127 cpu-idle-states = <&CPU_PH20>;
131 compatible = "arm,idle-state";
132 idle-state-name = "PH20";
133 arm,psci-suspend-param = <0x00010000>;
134 entry-latency-us = <1000>;
135 exit-latency-us = <1000>;
136 min-residency-us = <3000>;
140 gic: interrupt-controller@6000000 {
141 compatible = "arm,gic-v3";
142 #interrupt-cells = <3>;
143 interrupt-controller;
144 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
145 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
146 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
147 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
148 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
149 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
153 compatible = "arm,armv8-timer";
154 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
155 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
156 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
157 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
161 compatible = "arm,psci-0.2";
166 compatible = "fixed-clock";
168 clock-frequency = <100000000>;
169 clock-output-names = "sysclk";
173 compatible = "simple-bus";
174 #address-cells = <2>;
178 clockgen: clocking@1300000 {
179 compatible = "fsl,ls1088a-clockgen";
180 reg = <0 0x1300000 0 0xa0000>;
186 compatible = "fsl,qoriq-tmu";
187 reg = <0x0 0x1f80000 0x0 0x10000>;
188 interrupts = <0 23 0x4>;
189 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
190 fsl,tmu-calibration =
191 /* Calibration data group 1 */
192 <0x00000000 0x00000026
193 0x00000001 0x0000002d
194 0x00000002 0x00000032
195 0x00000003 0x00000039
196 0x00000004 0x0000003f
197 0x00000005 0x00000046
198 0x00000006 0x0000004d
199 0x00000007 0x00000054
200 0x00000008 0x0000005a
201 0x00000009 0x00000061
202 0x0000000a 0x0000006a
203 0x0000000b 0x00000071
204 /* Calibration data group 2 */
205 0x00010000 0x00000025
206 0x00010001 0x0000002c
207 0x00010002 0x00000035
208 0x00010003 0x0000003d
209 0x00010004 0x00000045
210 0x00010005 0x0000004e
211 0x00010006 0x00000057
212 0x00010007 0x00000061
213 0x00010008 0x0000006b
214 0x00010009 0x00000076
215 /* Calibration data group 3 */
216 0x00020000 0x00000029
217 0x00020001 0x00000033
218 0x00020002 0x0000003d
219 0x00020003 0x00000049
220 0x00020004 0x00000056
221 0x00020005 0x00000061
222 0x00020006 0x0000006d
223 /* Calibration data group 4 */
224 0x00030000 0x00000021
225 0x00030001 0x0000002a
226 0x00030002 0x0000003c
227 0x00030003 0x0000004e>;
229 #thermal-sensor-cells = <1>;
233 cpu_thermal: cpu-thermal {
234 polling-delay-passive = <1000>;
235 polling-delay = <5000>;
236 thermal-sensors = <&tmu 0>;
239 cpu_alert: cpu-alert {
240 temperature = <85000>;
246 temperature = <95000>;
256 <&cpu0 THERMAL_NO_LIMIT
263 <&cpu4 THERMAL_NO_LIMIT
270 duart0: serial@21c0500 {
271 compatible = "fsl,ns16550", "ns16550a";
272 reg = <0x0 0x21c0500 0x0 0x100>;
273 clocks = <&clockgen 4 3>;
274 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
278 duart1: serial@21c0600 {
279 compatible = "fsl,ns16550", "ns16550a";
280 reg = <0x0 0x21c0600 0x0 0x100>;
281 clocks = <&clockgen 4 3>;
282 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
286 gpio0: gpio@2300000 {
287 compatible = "fsl,qoriq-gpio";
288 reg = <0x0 0x2300000 0x0 0x10000>;
289 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-controller;
293 #interrupt-cells = <2>;
296 gpio1: gpio@2310000 {
297 compatible = "fsl,qoriq-gpio";
298 reg = <0x0 0x2310000 0x0 0x10000>;
299 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
306 gpio2: gpio@2320000 {
307 compatible = "fsl,qoriq-gpio";
308 reg = <0x0 0x2320000 0x0 0x10000>;
309 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
316 gpio3: gpio@2330000 {
317 compatible = "fsl,qoriq-gpio";
318 reg = <0x0 0x2330000 0x0 0x10000>;
319 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
327 compatible = "fsl,ifc", "simple-bus";
328 reg = <0x0 0x2240000 0x0 0x20000>;
329 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <2>;
337 compatible = "fsl,vf610-i2c";
338 #address-cells = <1>;
340 reg = <0x0 0x2000000 0x0 0x10000>;
341 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clockgen 4 3>;
347 compatible = "fsl,vf610-i2c";
348 #address-cells = <1>;
350 reg = <0x0 0x2010000 0x0 0x10000>;
351 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&clockgen 4 3>;
357 compatible = "fsl,vf610-i2c";
358 #address-cells = <1>;
360 reg = <0x0 0x2020000 0x0 0x10000>;
361 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clockgen 4 3>;
367 compatible = "fsl,vf610-i2c";
368 #address-cells = <1>;
370 reg = <0x0 0x2030000 0x0 0x10000>;
371 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&clockgen 4 3>;
376 esdhc: esdhc@2140000 {
377 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
378 reg = <0x0 0x2140000 0x0 0x10000>;
379 interrupts = <0 28 0x4>; /* Level high type */
380 clock-frequency = <0>;
381 voltage-ranges = <1800 1800 3300 3300>;
389 compatible = "fsl,ls1088a-ahci";
390 reg = <0x0 0x3200000 0x0 0x10000>,
391 <0x7 0x100520 0x0 0x4>;
392 reg-names = "ahci", "sata-ecc";
393 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clockgen 4 3>;
399 crypto: crypto@8000000 {
400 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
402 #address-cells = <1>;
404 ranges = <0x0 0x00 0x8000000 0x100000>;
405 reg = <0x00 0x8000000 0x0 0x100000>;
406 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
410 compatible = "fsl,sec-v5.0-job-ring",
411 "fsl,sec-v4.0-job-ring";
412 reg = <0x10000 0x10000>;
413 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
417 compatible = "fsl,sec-v5.0-job-ring",
418 "fsl,sec-v4.0-job-ring";
419 reg = <0x20000 0x10000>;
420 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
424 compatible = "fsl,sec-v5.0-job-ring",
425 "fsl,sec-v4.0-job-ring";
426 reg = <0x30000 0x10000>;
427 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
431 compatible = "fsl,sec-v5.0-job-ring",
432 "fsl,sec-v4.0-job-ring";
433 reg = <0x40000 0x10000>;
434 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;