1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Travese Ten64 (LS1088) board
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
8 * Author: Mathew McBride <matt@traverse.com.au>
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
19 model = "Traverse Ten64";
20 compatible = "traverse,ten64", "fsl,ls1088a";
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
34 /* Fired by system controller when
35 * external power off (e.g ATX Power Button)
39 label = "External Power Down";
40 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
41 linux,code = <KEY_POWER>;
44 /* Rear Panel 'ADMIN' button (GPIO_H) */
46 label = "ADMIN button";
47 gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
48 linux,code = <KEY_WPS_BUTTON>;
53 compatible = "gpio-leds";
56 label = "ten64:green:sfp1:down";
57 gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
61 label = "ten64:green:sfp2:up";
62 gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
66 label = "ten64:admin";
67 gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
72 compatible = "sff,sfp";
73 i2c-bus = <&sfplower_i2c>;
74 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
75 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
76 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
77 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
78 maximum-power-milliwatt = <2000>;
82 compatible = "sff,sfp";
83 i2c-bus = <&sfpupper_i2c>;
84 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
85 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
86 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
87 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
88 maximum-power-milliwatt = <2000>;
96 phy-connection-type = "10gbase-r";
97 managed = "in-band-status";
100 /* XG0 - Lower SFP */
103 pcs-handle = <&pcs2>;
104 phy-connection-type = "10gbase-r";
105 managed = "in-band-status";
108 /* DPMAC3..6 is GE4 to GE8 */
110 phy-handle = <&mdio1_phy5>;
111 phy-connection-type = "qsgmii";
112 managed = "in-band-status";
113 pcs-handle = <&pcs3_0>;
117 phy-handle = <&mdio1_phy6>;
118 phy-connection-type = "qsgmii";
119 managed = "in-band-status";
120 pcs-handle = <&pcs3_1>;
124 phy-handle = <&mdio1_phy7>;
125 phy-connection-type = "qsgmii";
126 managed = "in-band-status";
127 pcs-handle = <&pcs3_2>;
131 phy-handle = <&mdio1_phy8>;
132 phy-connection-type = "qsgmii";
133 managed = "in-band-status";
134 pcs-handle = <&pcs3_3>;
137 /* DPMAC7..10 is GE0 to GE3 */
139 phy-handle = <&mdio1_phy1>;
140 phy-connection-type = "qsgmii";
141 managed = "in-band-status";
142 pcs-handle = <&pcs7_0>;
146 phy-handle = <&mdio1_phy2>;
147 phy-connection-type = "qsgmii";
148 managed = "in-band-status";
149 pcs-handle = <&pcs7_1>;
153 phy-handle = <&mdio1_phy3>;
154 phy-connection-type = "qsgmii";
155 managed = "in-band-status";
156 pcs-handle = <&pcs7_2>;
160 phy-handle = <&mdio1_phy4>;
161 phy-connection-type = "qsgmii";
162 managed = "in-band-status";
163 pcs-handle = <&pcs7_3>;
177 mdio1_phy5: ethernet-phy@c {
181 mdio1_phy6: ethernet-phy@d {
185 mdio1_phy7: ethernet-phy@e {
189 mdio1_phy8: ethernet-phy@f {
193 mdio1_phy1: ethernet-phy@1c {
197 mdio1_phy2: ethernet-phy@1d {
201 mdio1_phy3: ethernet-phy@1e {
205 mdio1_phy4: ethernet-phy@1f {
218 compatible = "ti,tca9539";
225 gpios = <13 GPIO_ACTIVE_HIGH>;
231 compatible = "atmel,at97sc3204t";
240 compatible = "epson,rx8035";
249 compatible = "nxp,pca9540";
250 #address-cells = <1>;
254 sfpupper_i2c: i2c@0 {
255 #address-cells = <1>;
260 sfplower_i2c: i2c@1 {
261 #address-cells = <1>;
288 compatible = "jedec,spi-nor";
289 #address-cells = <1>;
292 spi-max-frequency = <20000000>;
293 spi-rx-bus-width = <4>;
294 spi-tx-bus-width = <4>;
297 compatible = "fixed-partitions";
298 #address-cells = <1>;
308 reg = <0x100000 0x200000>;
312 label = "mcfirmware";
313 reg = <0x300000 0x200000>;
318 reg = <0x500000 0x80000>;
323 reg = <0x580000 0x40000>;
328 reg = <0x5C0000 0x40000>;
332 label = "devicetree";
333 reg = <0x600000 0x40000>;
339 compatible = "spi-nand";
340 #address-cells = <1>;
343 spi-max-frequency = <20000000>;
344 spi-rx-bus-width = <4>;
345 spi-tx-bus-width = <4>;
348 compatible = "fixed-partitions";
349 #address-cells = <1>;
352 /* reserved for future boot direct from NAND flash
353 * (this would use the same layout as the 8MiB NOR flash)
356 label = "nand-boot-reserved";
360 /* recovery / install environment */
363 reg = <0x800000 0x2000000>;
366 /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
369 reg = <0x2800000 0x6C00000>;
372 /* ubib (second OpenWrt) */
375 reg = <0x9400000 0x6C00000>;