GNU Linux-libre 6.1.90-gnu
[releases.git] / arch / arm64 / boot / dts / freescale / fsl-ls1046a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Device Tree Include file for NXP Layerscape-1046A family SoC.
4  *
5  * Copyright 2016 Freescale Semiconductor, Inc.
6  * Copyright 2018, 2020 NXP
7  *
8  * Mingkai Hu <mingkai.hu@nxp.com>
9  */
10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
15
16 / {
17         compatible = "fsl,ls1046a";
18         interrupt-parent = <&gic>;
19         #address-cells = <2>;
20         #size-cells = <2>;
21
22         aliases {
23                 crypto = &crypto;
24                 fman0 = &fman0;
25                 ethernet0 = &enet0;
26                 ethernet1 = &enet1;
27                 ethernet2 = &enet2;
28                 ethernet3 = &enet3;
29                 ethernet4 = &enet4;
30                 ethernet5 = &enet5;
31                 ethernet6 = &enet6;
32                 ethernet7 = &enet7;
33                 rtc1 = &ftm_alarm0;
34         };
35
36         cpus {
37                 #address-cells = <1>;
38                 #size-cells = <0>;
39
40                 cpu0: cpu@0 {
41                         device_type = "cpu";
42                         compatible = "arm,cortex-a72";
43                         reg = <0x0>;
44                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
45                         next-level-cache = <&l2>;
46                         cpu-idle-states = <&CPU_PH20>;
47                         #cooling-cells = <2>;
48                 };
49
50                 cpu1: cpu@1 {
51                         device_type = "cpu";
52                         compatible = "arm,cortex-a72";
53                         reg = <0x1>;
54                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
55                         next-level-cache = <&l2>;
56                         cpu-idle-states = <&CPU_PH20>;
57                         #cooling-cells = <2>;
58                 };
59
60                 cpu2: cpu@2 {
61                         device_type = "cpu";
62                         compatible = "arm,cortex-a72";
63                         reg = <0x2>;
64                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
65                         next-level-cache = <&l2>;
66                         cpu-idle-states = <&CPU_PH20>;
67                         #cooling-cells = <2>;
68                 };
69
70                 cpu3: cpu@3 {
71                         device_type = "cpu";
72                         compatible = "arm,cortex-a72";
73                         reg = <0x3>;
74                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
75                         next-level-cache = <&l2>;
76                         cpu-idle-states = <&CPU_PH20>;
77                         #cooling-cells = <2>;
78                 };
79
80                 l2: l2-cache {
81                         compatible = "cache";
82                 };
83         };
84
85         idle-states {
86                 /*
87                  * PSCI node is not added default, U-boot will add missing
88                  * parts if it determines to use PSCI.
89                  */
90                 entry-method = "psci";
91
92                 CPU_PH20: cpu-ph20 {
93                         compatible = "arm,idle-state";
94                         idle-state-name = "PH20";
95                         arm,psci-suspend-param = <0x0>;
96                         entry-latency-us = <1000>;
97                         exit-latency-us = <1000>;
98                         min-residency-us = <3000>;
99                 };
100         };
101
102         memory@80000000 {
103                 device_type = "memory";
104                 /* Real size will be filled by bootloader */
105                 reg = <0x0 0x80000000 0x0 0x0>;
106         };
107
108         sysclk: sysclk {
109                 compatible = "fixed-clock";
110                 #clock-cells = <0>;
111                 clock-frequency = <100000000>;
112                 clock-output-names = "sysclk";
113         };
114
115         reboot {
116                 compatible = "syscon-reboot";
117                 regmap = <&dcfg>;
118                 offset = <0xb0>;
119                 mask = <0x02>;
120         };
121
122         thermal-zones {
123                 ddr-controller {
124                         polling-delay-passive = <1000>;
125                         polling-delay = <5000>;
126                         thermal-sensors = <&tmu 0>;
127
128                         trips {
129                                 ddr-ctrler-alert {
130                                         temperature = <85000>;
131                                         hysteresis = <2000>;
132                                         type = "passive";
133                                 };
134
135                                 ddr-ctrler-crit {
136                                         temperature = <95000>;
137                                         hysteresis = <2000>;
138                                         type = "critical";
139                                 };
140                         };
141                 };
142
143                 serdes {
144                         polling-delay-passive = <1000>;
145                         polling-delay = <5000>;
146                         thermal-sensors = <&tmu 1>;
147
148                         trips {
149                                 serdes-alert {
150                                         temperature = <85000>;
151                                         hysteresis = <2000>;
152                                         type = "passive";
153                                 };
154
155                                 serdes-crit {
156                                         temperature = <95000>;
157                                         hysteresis = <2000>;
158                                         type = "critical";
159                                 };
160                         };
161                 };
162
163                 fman {
164                         polling-delay-passive = <1000>;
165                         polling-delay = <5000>;
166                         thermal-sensors = <&tmu 2>;
167
168                         trips {
169                                 fman-alert {
170                                         temperature = <85000>;
171                                         hysteresis = <2000>;
172                                         type = "passive";
173                                 };
174
175                                 fman-crit {
176                                         temperature = <95000>;
177                                         hysteresis = <2000>;
178                                         type = "critical";
179                                 };
180                         };
181                 };
182
183                 core-cluster {
184                         polling-delay-passive = <1000>;
185                         polling-delay = <5000>;
186                         thermal-sensors = <&tmu 3>;
187
188                         trips {
189                                 core_cluster_alert: core-cluster-alert {
190                                         temperature = <85000>;
191                                         hysteresis = <2000>;
192                                         type = "passive";
193                                 };
194
195                                 core_cluster_crit: core-cluster-crit {
196                                         temperature = <95000>;
197                                         hysteresis = <2000>;
198                                         type = "critical";
199                                 };
200                         };
201
202                         cooling-maps {
203                                 map0 {
204                                         trip = <&core_cluster_alert>;
205                                         cooling-device =
206                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210                                 };
211                         };
212                 };
213
214                 sec {
215                         polling-delay-passive = <1000>;
216                         polling-delay = <5000>;
217                         thermal-sensors = <&tmu 4>;
218
219                         trips {
220                                 sec-alert {
221                                         temperature = <85000>;
222                                         hysteresis = <2000>;
223                                         type = "passive";
224                                 };
225
226                                 sec-crit {
227                                         temperature = <95000>;
228                                         hysteresis = <2000>;
229                                         type = "critical";
230                                 };
231                         };
232                 };
233         };
234
235         timer {
236                 compatible = "arm,armv8-timer";
237                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
238                                           IRQ_TYPE_LEVEL_LOW)>,
239                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
240                                           IRQ_TYPE_LEVEL_LOW)>,
241                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
242                                           IRQ_TYPE_LEVEL_LOW)>,
243                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
244                                           IRQ_TYPE_LEVEL_LOW)>;
245         };
246
247         pmu {
248                 compatible = "arm,cortex-a72-pmu";
249                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
250                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
251                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
252                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
253                 interrupt-affinity = <&cpu0>,
254                                      <&cpu1>,
255                                      <&cpu2>,
256                                      <&cpu3>;
257         };
258
259         gic: interrupt-controller@1400000 {
260                 compatible = "arm,gic-400";
261                 #interrupt-cells = <3>;
262                 interrupt-controller;
263                 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
264                       <0x0 0x1420000 0 0x20000>, /* GICC */
265                       <0x0 0x1440000 0 0x20000>, /* GICH */
266                       <0x0 0x1460000 0 0x20000>; /* GICV */
267                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
268                                          IRQ_TYPE_LEVEL_LOW)>;
269         };
270
271         soc: soc {
272                 compatible = "simple-bus";
273                 #address-cells = <2>;
274                 #size-cells = <2>;
275                 ranges;
276                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
277                 dma-coherent;
278
279                 ddr: memory-controller@1080000 {
280                         compatible = "fsl,qoriq-memory-controller";
281                         reg = <0x0 0x1080000 0x0 0x1000>;
282                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
283                         big-endian;
284                 };
285
286                 ifc: memory-controller@1530000 {
287                         compatible = "fsl,ifc";
288                         reg = <0x0 0x1530000 0x0 0x10000>;
289                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
290                         status = "disabled";
291                 };
292
293                 qspi: spi@1550000 {
294                         compatible = "fsl,ls1021a-qspi";
295                         #address-cells = <1>;
296                         #size-cells = <0>;
297                         reg = <0x0 0x1550000 0x0 0x10000>,
298                                 <0x0 0x40000000 0x0 0x10000000>;
299                         reg-names = "QuadSPI", "QuadSPI-memory";
300                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
301                         clock-names = "qspi_en", "qspi";
302                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
303                                             QORIQ_CLK_PLL_DIV(2)>,
304                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
305                                             QORIQ_CLK_PLL_DIV(2)>;
306                         status = "disabled";
307                 };
308
309                 esdhc: esdhc@1560000 {
310                         compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
311                         reg = <0x0 0x1560000 0x0 0x10000>;
312                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
313                         clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
314                         voltage-ranges = <1800 1800 3300 3300>;
315                         sdhci,auto-cmd12;
316                         big-endian;
317                         bus-width = <4>;
318                 };
319
320                 scfg: scfg@1570000 {
321                         compatible = "fsl,ls1046a-scfg", "syscon";
322                         reg = <0x0 0x1570000 0x0 0x10000>;
323                         big-endian;
324                         #address-cells = <1>;
325                         #size-cells = <1>;
326                         ranges = <0x0 0x0 0x1570000 0x10000>;
327
328                         extirq: interrupt-controller@1ac {
329                                 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq";
330                                 #interrupt-cells = <2>;
331                                 #address-cells = <0>;
332                                 interrupt-controller;
333                                 reg = <0x1ac 4>;
334                                 interrupt-map =
335                                         <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
336                                         <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
337                                         <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
338                                         <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
339                                         <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
340                                         <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
341                                         <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
342                                         <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
343                                         <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
344                                         <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
345                                         <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
346                                         <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
347                                 interrupt-map-mask = <0xf 0x0>;
348                         };
349                 };
350
351                 crypto: crypto@1700000 {
352                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
353                                      "fsl,sec-v4.0";
354                         fsl,sec-era = <8>;
355                         #address-cells = <1>;
356                         #size-cells = <1>;
357                         ranges = <0x0 0x00 0x1700000 0x100000>;
358                         reg = <0x00 0x1700000 0x0 0x100000>;
359                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
360
361                         sec_jr0: jr@10000 {
362                                 compatible = "fsl,sec-v5.4-job-ring",
363                                              "fsl,sec-v5.0-job-ring",
364                                              "fsl,sec-v4.0-job-ring";
365                                 reg = <0x10000 0x10000>;
366                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
367                         };
368
369                         sec_jr1: jr@20000 {
370                                 compatible = "fsl,sec-v5.4-job-ring",
371                                              "fsl,sec-v5.0-job-ring",
372                                              "fsl,sec-v4.0-job-ring";
373                                 reg = <0x20000 0x10000>;
374                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
375                         };
376
377                         sec_jr2: jr@30000 {
378                                 compatible = "fsl,sec-v5.4-job-ring",
379                                              "fsl,sec-v5.0-job-ring",
380                                              "fsl,sec-v4.0-job-ring";
381                                 reg = <0x30000 0x10000>;
382                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
383                         };
384
385                         sec_jr3: jr@40000 {
386                                 compatible = "fsl,sec-v5.4-job-ring",
387                                              "fsl,sec-v5.0-job-ring",
388                                              "fsl,sec-v4.0-job-ring";
389                                 reg = <0x40000 0x10000>;
390                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
391                         };
392                 };
393
394                 qman: qman@1880000 {
395                         compatible = "fsl,qman";
396                         reg = <0x0 0x1880000 0x0 0x10000>;
397                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
398                         memory-region = <&qman_fqd &qman_pfdr>;
399
400                 };
401
402                 bman: bman@1890000 {
403                         compatible = "fsl,bman";
404                         reg = <0x0 0x1890000 0x0 0x10000>;
405                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
406                         memory-region = <&bman_fbpr>;
407
408                 };
409
410                 qportals: qman-portals@500000000 {
411                         ranges = <0x0 0x5 0x00000000 0x8000000>;
412                 };
413
414                 bportals: bman-portals@508000000 {
415                         ranges = <0x0 0x5 0x08000000 0x8000000>;
416                 };
417
418                 sfp: efuse@1e80000 {
419                         compatible = "fsl,ls1021a-sfp";
420                         reg = <0x0 0x1e80000 0x0 0x10000>;
421                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
422                                             QORIQ_CLK_PLL_DIV(4)>;
423                         clock-names = "sfp";
424                 };
425
426                 dcfg: dcfg@1ee0000 {
427                         compatible = "fsl,ls1046a-dcfg", "syscon";
428                         reg = <0x0 0x1ee0000 0x0 0x1000>;
429                         big-endian;
430                 };
431
432                 clockgen: clocking@1ee1000 {
433                         compatible = "fsl,ls1046a-clockgen";
434                         reg = <0x0 0x1ee1000 0x0 0x1000>;
435                         #clock-cells = <2>;
436                         clocks = <&sysclk>;
437                 };
438
439                 tmu: tmu@1f00000 {
440                         compatible = "fsl,qoriq-tmu";
441                         reg = <0x0 0x1f00000 0x0 0x10000>;
442                         interrupts = <0 33 0x4>;
443                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
444                         fsl,tmu-calibration =
445                                 /* Calibration data group 1 */
446                                 <0x00000000 0x00000023
447                                 0x00000001 0x00000029
448                                 0x00000002 0x0000002f
449                                 0x00000003 0x00000036
450                                 0x00000004 0x0000003c
451                                 0x00000005 0x00000042
452                                 0x00000006 0x00000049
453                                 0x00000007 0x0000004f
454                                 0x00000008 0x00000055
455                                 0x00000009 0x0000005c
456                                 0x0000000a 0x00000062
457                                 0x0000000b 0x00000068
458                                 /* Calibration data group 2 */
459                                 0x00010000 0x00000022
460                                 0x00010001 0x0000002a
461                                 0x00010002 0x00000032
462                                 0x00010003 0x0000003a
463                                 0x00010004 0x00000042
464                                 0x00010005 0x0000004a
465                                 0x00010006 0x00000052
466                                 0x00010007 0x0000005a
467                                 0x00010008 0x00000062
468                                 0x00010009 0x0000006a
469                                 /* Calibration data group 3 */
470                                 0x00020000 0x00000021
471                                 0x00020001 0x0000002b
472                                 0x00020002 0x00000035
473                                 0x00020003 0x0000003e
474                                 0x00020004 0x00000048
475                                 0x00020005 0x00000052
476                                 0x00020006 0x0000005c
477                                 /* Calibration data group 4 */
478                                 0x00030000 0x00000011
479                                 0x00030001 0x0000001a
480                                 0x00030002 0x00000024
481                                 0x00030003 0x0000002e
482                                 0x00030004 0x00000038
483                                 0x00030005 0x00000042
484                                 0x00030006 0x0000004c
485                                 0x00030007 0x00000056>;
486                         big-endian;
487                         #thermal-sensor-cells = <1>;
488                 };
489
490                 dspi: spi@2100000 {
491                         compatible = "fsl,ls1021a-v1.0-dspi";
492                         #address-cells = <1>;
493                         #size-cells = <0>;
494                         reg = <0x0 0x2100000 0x0 0x10000>;
495                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
496                         clock-names = "dspi";
497                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
498                                             QORIQ_CLK_PLL_DIV(2)>;
499                         spi-num-chipselects = <5>;
500                         big-endian;
501                         status = "disabled";
502                 };
503
504                 i2c0: i2c@2180000 {
505                         compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
506                         #address-cells = <1>;
507                         #size-cells = <0>;
508                         reg = <0x0 0x2180000 0x0 0x10000>;
509                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
510                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
511                                             QORIQ_CLK_PLL_DIV(2)>;
512                         dmas = <&edma0 1 38>,
513                                <&edma0 1 39>;
514                         dma-names = "rx", "tx";
515                         status = "disabled";
516                 };
517
518                 i2c1: i2c@2190000 {
519                         compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
520                         #address-cells = <1>;
521                         #size-cells = <0>;
522                         reg = <0x0 0x2190000 0x0 0x10000>;
523                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
524                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
525                                             QORIQ_CLK_PLL_DIV(2)>;
526                         scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
527                         status = "disabled";
528                 };
529
530                 i2c2: i2c@21a0000 {
531                         compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
532                         #address-cells = <1>;
533                         #size-cells = <0>;
534                         reg = <0x0 0x21a0000 0x0 0x10000>;
535                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
536                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
537                                             QORIQ_CLK_PLL_DIV(2)>;
538                         scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
539                         status = "disabled";
540                 };
541
542                 i2c3: i2c@21b0000 {
543                         compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
544                         #address-cells = <1>;
545                         #size-cells = <0>;
546                         reg = <0x0 0x21b0000 0x0 0x10000>;
547                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
548                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
549                                             QORIQ_CLK_PLL_DIV(2)>;
550                         scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
551                         status = "disabled";
552                 };
553
554                 duart0: serial@21c0500 {
555                         compatible = "fsl,ns16550", "ns16550a";
556                         reg = <0x00 0x21c0500 0x0 0x100>;
557                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
558                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
559                                             QORIQ_CLK_PLL_DIV(2)>;
560                         status = "disabled";
561                 };
562
563                 duart1: serial@21c0600 {
564                         compatible = "fsl,ns16550", "ns16550a";
565                         reg = <0x00 0x21c0600 0x0 0x100>;
566                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
567                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
568                                             QORIQ_CLK_PLL_DIV(2)>;
569                         status = "disabled";
570                 };
571
572                 duart2: serial@21d0500 {
573                         compatible = "fsl,ns16550", "ns16550a";
574                         reg = <0x0 0x21d0500 0x0 0x100>;
575                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
576                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
577                                             QORIQ_CLK_PLL_DIV(2)>;
578                         status = "disabled";
579                 };
580
581                 duart3: serial@21d0600 {
582                         compatible = "fsl,ns16550", "ns16550a";
583                         reg = <0x0 0x21d0600 0x0 0x100>;
584                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
585                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
586                                             QORIQ_CLK_PLL_DIV(2)>;
587                         status = "disabled";
588                 };
589
590                 gpio0: gpio@2300000 {
591                         compatible = "fsl,qoriq-gpio";
592                         reg = <0x0 0x2300000 0x0 0x10000>;
593                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
594                         gpio-controller;
595                         #gpio-cells = <2>;
596                         interrupt-controller;
597                         #interrupt-cells = <2>;
598                 };
599
600                 gpio1: gpio@2310000 {
601                         compatible = "fsl,qoriq-gpio";
602                         reg = <0x0 0x2310000 0x0 0x10000>;
603                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
604                         gpio-controller;
605                         #gpio-cells = <2>;
606                         interrupt-controller;
607                         #interrupt-cells = <2>;
608                 };
609
610                 gpio2: gpio@2320000 {
611                         compatible = "fsl,qoriq-gpio";
612                         reg = <0x0 0x2320000 0x0 0x10000>;
613                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
614                         gpio-controller;
615                         #gpio-cells = <2>;
616                         interrupt-controller;
617                         #interrupt-cells = <2>;
618                 };
619
620                 gpio3: gpio@2330000 {
621                         compatible = "fsl,qoriq-gpio";
622                         reg = <0x0 0x2330000 0x0 0x10000>;
623                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
624                         gpio-controller;
625                         #gpio-cells = <2>;
626                         interrupt-controller;
627                         #interrupt-cells = <2>;
628                 };
629
630                 lpuart0: serial@2950000 {
631                         compatible = "fsl,ls1021a-lpuart";
632                         reg = <0x0 0x2950000 0x0 0x1000>;
633                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
634                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
635                                             QORIQ_CLK_PLL_DIV(1)>;
636                         clock-names = "ipg";
637                         status = "disabled";
638                 };
639
640                 lpuart1: serial@2960000 {
641                         compatible = "fsl,ls1021a-lpuart";
642                         reg = <0x0 0x2960000 0x0 0x1000>;
643                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
644                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
645                                             QORIQ_CLK_PLL_DIV(2)>;
646                         clock-names = "ipg";
647                         status = "disabled";
648                 };
649
650                 lpuart2: serial@2970000 {
651                         compatible = "fsl,ls1021a-lpuart";
652                         reg = <0x0 0x2970000 0x0 0x1000>;
653                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
654                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
655                                             QORIQ_CLK_PLL_DIV(2)>;
656                         clock-names = "ipg";
657                         status = "disabled";
658                 };
659
660                 lpuart3: serial@2980000 {
661                         compatible = "fsl,ls1021a-lpuart";
662                         reg = <0x0 0x2980000 0x0 0x1000>;
663                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
664                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
665                                             QORIQ_CLK_PLL_DIV(2)>;
666                         clock-names = "ipg";
667                         status = "disabled";
668                 };
669
670                 lpuart4: serial@2990000 {
671                         compatible = "fsl,ls1021a-lpuart";
672                         reg = <0x0 0x2990000 0x0 0x1000>;
673                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
674                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
675                                             QORIQ_CLK_PLL_DIV(2)>;
676                         clock-names = "ipg";
677                         status = "disabled";
678                 };
679
680                 lpuart5: serial@29a0000 {
681                         compatible = "fsl,ls1021a-lpuart";
682                         reg = <0x0 0x29a0000 0x0 0x1000>;
683                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
684                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
685                                             QORIQ_CLK_PLL_DIV(2)>;
686                         clock-names = "ipg";
687                         status = "disabled";
688                 };
689
690                 wdog0: watchdog@2ad0000 {
691                         compatible = "fsl,imx21-wdt";
692                         reg = <0x0 0x2ad0000 0x0 0x10000>;
693                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
694                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
695                                             QORIQ_CLK_PLL_DIV(2)>;
696                         big-endian;
697                 };
698
699                 edma0: dma-controller@2c00000 {
700                         #dma-cells = <2>;
701                         compatible = "fsl,vf610-edma";
702                         reg = <0x0 0x2c00000 0x0 0x10000>,
703                               <0x0 0x2c10000 0x0 0x10000>,
704                               <0x0 0x2c20000 0x0 0x10000>;
705                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
706                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
707                         interrupt-names = "edma-tx", "edma-err";
708                         dma-channels = <32>;
709                         big-endian;
710                         clock-names = "dmamux0", "dmamux1";
711                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
712                                             QORIQ_CLK_PLL_DIV(2)>,
713                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
714                                             QORIQ_CLK_PLL_DIV(2)>;
715                 };
716
717                 aux_bus: aux_bus {
718                         #address-cells = <2>;
719                         #size-cells = <2>;
720                         compatible = "simple-bus";
721                         ranges;
722                         dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
723
724                         usb0: usb@2f00000 {
725                                 compatible = "snps,dwc3";
726                                 reg = <0x0 0x2f00000 0x0 0x10000>;
727                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
728                                 dr_mode = "host";
729                                 snps,quirk-frame-length-adjustment = <0x20>;
730                                 snps,dis_rxdet_inp3_quirk;
731                                 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
732                                 usb3-lpm-capable;
733                         };
734
735                         usb1: usb@3000000 {
736                                 compatible = "snps,dwc3";
737                                 reg = <0x0 0x3000000 0x0 0x10000>;
738                                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
739                                 dr_mode = "host";
740                                 snps,quirk-frame-length-adjustment = <0x20>;
741                                 snps,dis_rxdet_inp3_quirk;
742                                 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
743                                 usb3-lpm-capable;
744                         };
745
746                         usb2: usb@3100000 {
747                                 compatible = "snps,dwc3";
748                                 reg = <0x0 0x3100000 0x0 0x10000>;
749                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
750                                 dr_mode = "host";
751                                 snps,quirk-frame-length-adjustment = <0x20>;
752                                 snps,dis_rxdet_inp3_quirk;
753                                 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
754                                 usb3-lpm-capable;
755                         };
756
757                         sata: sata@3200000 {
758                                 compatible = "fsl,ls1046a-ahci";
759                                 reg = <0x0 0x3200000 0x0 0x10000>,
760                                         <0x0 0x20140520 0x0 0x4>;
761                                 reg-names = "ahci", "sata-ecc";
762                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
763                                 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
764                                                     QORIQ_CLK_PLL_DIV(2)>;
765                         };
766                 };
767
768                 msi1: msi-controller@1580000 {
769                         compatible = "fsl,ls1046a-msi";
770                         msi-controller;
771                         reg = <0x0 0x1580000 0x0 0x10000>;
772                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
773                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
774                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
775                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
776                 };
777
778                 msi2: msi-controller@1590000 {
779                         compatible = "fsl,ls1046a-msi";
780                         msi-controller;
781                         reg = <0x0 0x1590000 0x0 0x10000>;
782                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
783                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
784                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
785                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
786                 };
787
788                 msi3: msi-controller@15a0000 {
789                         compatible = "fsl,ls1046a-msi";
790                         msi-controller;
791                         reg = <0x0 0x15a0000 0x0 0x10000>;
792                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
793                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
794                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
795                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
796                 };
797
798                 pcie1: pcie@3400000 {
799                         compatible = "fsl,ls1046a-pcie";
800                         reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
801                               <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
802                         reg-names = "regs", "config";
803                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
804                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
805                         interrupt-names = "aer", "pme";
806                         #address-cells = <3>;
807                         #size-cells = <2>;
808                         device_type = "pci";
809                         num-viewport = <8>;
810                         bus-range = <0x0 0xff>;
811                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
812                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
813                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
814                         #interrupt-cells = <1>;
815                         interrupt-map-mask = <0 0 0 7>;
816                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
817                                         <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
818                                         <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
819                                         <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
820                         big-endian;
821                         status = "disabled";
822                 };
823
824                 pcie_ep1: pcie_ep@3400000 {
825                         compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
826                         reg = <0x00 0x03400000 0x0 0x00100000>,
827                               <0x40 0x00000000 0x8 0x00000000>;
828                         reg-names = "regs", "addr_space";
829                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
830                         interrupt-names = "pme";
831                         num-ib-windows = <6>;
832                         num-ob-windows = <8>;
833                         big-endian;
834                         status = "disabled";
835                 };
836
837                 pcie2: pcie@3500000 {
838                         compatible = "fsl,ls1046a-pcie";
839                         reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
840                               <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
841                         reg-names = "regs", "config";
842                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
843                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
844                         interrupt-names = "aer", "pme";
845                         #address-cells = <3>;
846                         #size-cells = <2>;
847                         device_type = "pci";
848                         num-viewport = <8>;
849                         bus-range = <0x0 0xff>;
850                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
851                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
852                         msi-parent = <&msi2>, <&msi3>, <&msi1>;
853                         #interrupt-cells = <1>;
854                         interrupt-map-mask = <0 0 0 7>;
855                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
856                                         <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
857                                         <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
858                                         <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
859                         big-endian;
860                         status = "disabled";
861                 };
862
863                 pcie_ep2: pcie_ep@3500000 {
864                         compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
865                         reg = <0x00 0x03500000 0x0 0x00100000>,
866                               <0x48 0x00000000 0x8 0x00000000>;
867                         reg-names = "regs", "addr_space";
868                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
869                         interrupt-names = "pme";
870                         num-ib-windows = <6>;
871                         num-ob-windows = <8>;
872                         big-endian;
873                         status = "disabled";
874                 };
875
876                 pcie3: pcie@3600000 {
877                         compatible = "fsl,ls1046a-pcie";
878                         reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
879                               <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
880                         reg-names = "regs", "config";
881                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
882                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
883                         interrupt-names = "aer", "pme";
884                         #address-cells = <3>;
885                         #size-cells = <2>;
886                         device_type = "pci";
887                         num-viewport = <8>;
888                         bus-range = <0x0 0xff>;
889                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
890                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891                         msi-parent = <&msi3>, <&msi1>, <&msi2>;
892                         #interrupt-cells = <1>;
893                         interrupt-map-mask = <0 0 0 7>;
894                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
895                                         <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
896                                         <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
897                                         <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
898                         big-endian;
899                         status = "disabled";
900                 };
901
902                 pcie_ep3: pcie_ep@3600000 {
903                         compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
904                         reg = <0x00 0x03600000 0x0 0x00100000>,
905                               <0x50 0x00000000 0x8 0x00000000>;
906                         reg-names = "regs", "addr_space";
907                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
908                         interrupt-names = "pme";
909                         num-ib-windows = <6>;
910                         num-ob-windows = <8>;
911                         big-endian;
912                         status = "disabled";
913                 };
914
915                 qdma: dma-controller@8380000 {
916                         compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
917                         reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
918                               <0x0 0x8390000 0x0 0x10000>, /* Status regs */
919                               <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
920                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
921                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
922                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
923                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
924                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
925                         interrupt-names = "qdma-error", "qdma-queue0",
926                                 "qdma-queue1", "qdma-queue2", "qdma-queue3";
927                         dma-channels = <8>;
928                         block-number = <1>;
929                         block-offset = <0x10000>;
930                         fsl,dma-queues = <2>;
931                         status-sizes = <64>;
932                         queue-sizes = <64 64>;
933                         big-endian;
934                 };
935
936                 rcpm: power-controller@1ee2140 {
937                         compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
938                         reg = <0x0 0x1ee2140 0x0 0x4>;
939                         #fsl,rcpm-wakeup-cells = <1>;
940                 };
941
942                 ftm_alarm0: timer@29d0000 {
943                         compatible = "fsl,ls1046a-ftm-alarm";
944                         reg = <0x0 0x29d0000 0x0 0x10000>;
945                         fsl,rcpm-wakeup = <&rcpm 0x20000>;
946                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
947                         big-endian;
948                 };
949         };
950
951         reserved-memory {
952                 #address-cells = <2>;
953                 #size-cells = <2>;
954                 ranges;
955
956                 bman_fbpr: bman-fbpr {
957                         compatible = "shared-dma-pool";
958                         size = <0 0x1000000>;
959                         alignment = <0 0x1000000>;
960                         no-map;
961                 };
962
963                 qman_fqd: qman-fqd {
964                         compatible = "shared-dma-pool";
965                         size = <0 0x800000>;
966                         alignment = <0 0x800000>;
967                         no-map;
968                 };
969
970                 qman_pfdr: qman-pfdr {
971                         compatible = "shared-dma-pool";
972                         size = <0 0x2000000>;
973                         alignment = <0 0x2000000>;
974                         no-map;
975                 };
976         };
977
978         firmware {
979                 optee {
980                         compatible = "linaro,optee-tz";
981                         method = "smc";
982                 };
983         };
984 };
985
986 #include "qoriq-qman-portals.dtsi"
987 #include "qoriq-bman-portals.dtsi"