arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
   3  *
   4  * Copyright 2016 Freescale Semiconductor, Inc.
   5  *
   6  * Mingkai Hu <mingkai.hu@nxp.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPLv2 or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This library is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This library is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 / {
  51         compatible = "fsl,ls1046a";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 crypto = &crypto;
  58                 fman0 = &fman0;
  59                 ethernet0 = &enet0;
  60                 ethernet1 = &enet1;
  61                 ethernet2 = &enet2;
  62                 ethernet3 = &enet3;
  63                 ethernet4 = &enet4;
  64                 ethernet5 = &enet5;
  65                 ethernet6 = &enet6;
  66                 ethernet7 = &enet7;
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a72";
  76                         reg = <0x0>;
  77                         clocks = <&clockgen 1 0>;
  78                         next-level-cache = <&l2>;
  79                         cpu-idle-states = <&CPU_PH20>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a72";
  86                         reg = <0x1>;
  87                         clocks = <&clockgen 1 0>;
  88                         next-level-cache = <&l2>;
  89                         cpu-idle-states = <&CPU_PH20>;
  90                 };
  91
  92                 cpu2: cpu@2 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a72";
  95                         reg = <0x2>;
  96                         clocks = <&clockgen 1 0>;
  97                         next-level-cache = <&l2>;
  98                         cpu-idle-states = <&CPU_PH20>;
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a72";
 104                         reg = <0x3>;
 105                         clocks = <&clockgen 1 0>;
 106                         next-level-cache = <&l2>;
 107                         cpu-idle-states = <&CPU_PH20>;
 108                 };
 109
 110                 l2: l2-cache {
 111                         compatible = "cache";
 112                 };
 113         };
 114
 115         idle-states {
 116                 /*
 117                  * PSCI node is not added default, U-boot will add missing
 118                  * parts if it determines to use PSCI.
 119                  */
 120                 entry-method = "arm,psci";
 121
 122                 CPU_PH20: cpu-ph20 {
 123                         compatible = "arm,idle-state";
 124                         idle-state-name = "PH20";
 125                         arm,psci-suspend-param = <0x00010000>;
 126                         entry-latency-us = <1000>;
 127                         exit-latency-us = <1000>;
 128                         min-residency-us = <3000>;
 129                 };
 130         };
 131
 132         memory@80000000 {
 133                 device_type = "memory";
 134         };
 135
 136         sysclk: sysclk {
 137                 compatible = "fixed-clock";
 138                 #clock-cells = <0>;
 139                 clock-frequency = <100000000>;
 140                 clock-output-names = "sysclk";
 141         };
 142
 143         reboot {
 144                 compatible ="syscon-reboot";
 145                 regmap = <&dcfg>;
 146                 offset = <0xb0>;
 147                 mask = <0x02>;
 148         };
 149
 150         timer {
 151                 compatible = "arm,armv8-timer";
 152                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
 153                                           IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
 155                                           IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
 157                                           IRQ_TYPE_LEVEL_LOW)>,
 158                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
 159                                           IRQ_TYPE_LEVEL_LOW)>;
 160         };
 161
 162         pmu {
 163                 compatible = "arm,cortex-a72-pmu";
 164                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 168                 interrupt-affinity = <&cpu0>,
 169                                      <&cpu1>,
 170                                      <&cpu2>,
 171                                      <&cpu3>;
 172         };
 173
 174         gic: interrupt-controller@1400000 {
 175                 compatible = "arm,gic-400";
 176                 #interrupt-cells = <3>;
 177                 interrupt-controller;
 178                 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
 179                       <0x0 0x1420000 0 0x20000>, /* GICC */
 180                       <0x0 0x1440000 0 0x20000>, /* GICH */
 181                       <0x0 0x1460000 0 0x20000>; /* GICV */
 182                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 183                                          IRQ_TYPE_LEVEL_LOW)>;
 184         };
 185
 186         soc: soc {
 187                 compatible = "simple-bus";
 188                 #address-cells = <2>;
 189                 #size-cells = <2>;
 190                 ranges;
 191
 192                 ddr: memory-controller@1080000 {
 193                         compatible = "fsl,qoriq-memory-controller";
 194                         reg = <0x0 0x1080000 0x0 0x1000>;
 195                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 196                         big-endian;
 197                 };
 198
 199                 ifc: ifc@1530000 {
 200                         compatible = "fsl,ifc", "simple-bus";
 201                         reg = <0x0 0x1530000 0x0 0x10000>;
 202                         big-endian;
 203                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 204                 };
 205
 206                 qspi: quadspi@1550000 {
 207                         compatible = "fsl,ls1021a-qspi";
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         reg = <0x0 0x1550000 0x0 0x10000>,
 211                                 <0x0 0x40000000 0x0 0x10000000>;
 212                         reg-names = "QuadSPI", "QuadSPI-memory";
 213                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 214                         clock-names = "qspi_en", "qspi";
 215                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 216                         big-endian;
 217                         fsl,qspi-has-second-chip;
 218                         status = "disabled";
 219                 };
 220
 221                 esdhc: esdhc@1560000 {
 222                         compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
 223                         reg = <0x0 0x1560000 0x0 0x10000>;
 224                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&clockgen 2 1>;
 226                         voltage-ranges = <1800 1800 3300 3300>;
 227                         sdhci,auto-cmd12;
 228                         big-endian;
 229                         bus-width = <4>;
 230                 };
 231
 232                 scfg: scfg@1570000 {
 233                         compatible = "fsl,ls1046a-scfg", "syscon";
 234                         reg = <0x0 0x1570000 0x0 0x10000>;
 235                         big-endian;
 236                 };
 237
 238                 crypto: crypto@1700000 {
 239                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 240                                      "fsl,sec-v4.0";
 241                         fsl,sec-era = <8>;
 242                         #address-cells = <1>;
 243                         #size-cells = <1>;
 244                         ranges = <0x0 0x00 0x1700000 0x100000>;
 245                         reg = <0x00 0x1700000 0x0 0x100000>;
 246                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 247                         dma-coherent;
 248
 249                         sec_jr0: jr@10000 {
 250                                 compatible = "fsl,sec-v5.4-job-ring",
 251                                              "fsl,sec-v5.0-job-ring",
 252                                              "fsl,sec-v4.0-job-ring";
 253                                 reg        = <0x10000 0x10000>;
 254                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 255                         };
 256
 257                         sec_jr1: jr@20000 {
 258                                 compatible = "fsl,sec-v5.4-job-ring",
 259                                              "fsl,sec-v5.0-job-ring",
 260                                              "fsl,sec-v4.0-job-ring";
 261                                 reg        = <0x20000 0x10000>;
 262                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 263                         };
 264
 265                         sec_jr2: jr@30000 {
 266                                 compatible = "fsl,sec-v5.4-job-ring",
 267                                              "fsl,sec-v5.0-job-ring",
 268                                              "fsl,sec-v4.0-job-ring";
 269                                 reg        = <0x30000 0x10000>;
 270                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 271                         };
 272
 273                         sec_jr3: jr@40000 {
 274                                 compatible = "fsl,sec-v5.4-job-ring",
 275                                              "fsl,sec-v5.0-job-ring",
 276                                              "fsl,sec-v4.0-job-ring";
 277                                 reg        = <0x40000 0x10000>;
 278                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 279                         };
 280                 };
 281
 282                 qman: qman@1880000 {
 283                         compatible = "fsl,qman";
 284                         reg = <0x0 0x1880000 0x0 0x10000>;
 285                         interrupts = <0 45 0x4>;
 286                         memory-region = <&qman_fqd &qman_pfdr>;
 287
 288                 };
 289
 290                 bman: bman@1890000 {
 291                         compatible = "fsl,bman";
 292                         reg = <0x0 0x1890000 0x0 0x10000>;
 293                         interrupts = <0 45 0x4>;
 294                         memory-region = <&bman_fbpr>;
 295
 296                 };
 297
 298                 qportals: qman-portals@500000000 {
 299                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 300                 };
 301
 302                 bportals: bman-portals@508000000 {
 303                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 304                 };
 305
 306                 dcfg: dcfg@1ee0000 {
 307                         compatible = "fsl,ls1046a-dcfg", "syscon";
 308                         reg = <0x0 0x1ee0000 0x0 0x1000>;
 309                         big-endian;
 310                 };
 311
 312                 clockgen: clocking@1ee1000 {
 313                         compatible = "fsl,ls1046a-clockgen";
 314                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 315                         #clock-cells = <2>;
 316                         clocks = <&sysclk>;
 317                 };
 318
 319                 tmu: tmu@1f00000 {
 320                         compatible = "fsl,qoriq-tmu";
 321                         reg = <0x0 0x1f00000 0x0 0x10000>;
 322                         interrupts = <0 33 0x4>;
 323                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 324                         fsl,tmu-calibration =
 325                                 /* Calibration data group 1 */
 326                                 <0x00000000 0x00000026
 327                                 0x00000001 0x0000002d
 328                                 0x00000002 0x00000032
 329                                 0x00000003 0x00000039
 330                                 0x00000004 0x0000003f
 331                                 0x00000005 0x00000046
 332                                 0x00000006 0x0000004d
 333                                 0x00000007 0x00000054
 334                                 0x00000008 0x0000005a
 335                                 0x00000009 0x00000061
 336                                 0x0000000a 0x0000006a
 337                                 0x0000000b 0x00000071
 338                                 /* Calibration data group 2 */
 339                                 0x00010000 0x00000025
 340                                 0x00010001 0x0000002c
 341                                 0x00010002 0x00000035
 342                                 0x00010003 0x0000003d
 343                                 0x00010004 0x00000045
 344                                 0x00010005 0x0000004e
 345                                 0x00010006 0x00000057
 346                                 0x00010007 0x00000061
 347                                 0x00010008 0x0000006b
 348                                 0x00010009 0x00000076
 349                                 /* Calibration data group 3 */
 350                                 0x00020000 0x00000029
 351                                 0x00020001 0x00000033
 352                                 0x00020002 0x0000003d
 353                                 0x00020003 0x00000049
 354                                 0x00020004 0x00000056
 355                                 0x00020005 0x00000061
 356                                 0x00020006 0x0000006d
 357                                 /* Calibration data group 4 */
 358                                 0x00030000 0x00000021
 359                                 0x00030001 0x0000002a
 360                                 0x00030002 0x0000003c
 361                                 0x00030003 0x0000004e>;
 362                         big-endian;
 363                         #thermal-sensor-cells = <1>;
 364                 };
 365
 366                 thermal-zones {
 367                         cpu_thermal: cpu-thermal {
 368                                 polling-delay-passive = <1000>;
 369                                 polling-delay = <5000>;
 370                                 thermal-sensors = <&tmu 3>;
 371
 372                                 trips {
 373                                         cpu_alert: cpu-alert {
 374                                                 temperature = <85000>;
 375                                                 hysteresis = <2000>;
 376                                                 type = "passive";
 377                                         };
 378
 379                                         cpu_crit: cpu-crit {
 380                                                 temperature = <95000>;
 381                                                 hysteresis = <2000>;
 382                                                 type = "critical";
 383                                         };
 384                                 };
 385
 386                                 cooling-maps {
 387                                         map0 {
 388                                                 trip = <&cpu_alert>;
 389                                                 cooling-device =
 390                                                         <&cpu0 THERMAL_NO_LIMIT
 391                                                         THERMAL_NO_LIMIT>;
 392                                         };
 393                                 };
 394                         };
 395                 };
 396
 397                 dspi: dspi@2100000 {
 398                         compatible = "fsl,ls1021a-v1.0-dspi";
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         reg = <0x0 0x2100000 0x0 0x10000>;
 402                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 403                         clock-names = "dspi";
 404                         clocks = <&clockgen 4 1>;
 405                         spi-num-chipselects = <5>;
 406                         big-endian;
 407                         status = "disabled";
 408                 };
 409
 410                 i2c0: i2c@2180000 {
 411                         compatible = "fsl,vf610-i2c";
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         reg = <0x0 0x2180000 0x0 0x10000>;
 415                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 416                         clocks = <&clockgen 4 1>;
 417                         dmas = <&edma0 1 39>,
 418                                <&edma0 1 38>;
 419                         dma-names = "tx", "rx";
 420                         status = "disabled";
 421                 };
 422
 423                 i2c1: i2c@2190000 {
 424                         compatible = "fsl,vf610-i2c";
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         reg = <0x0 0x2190000 0x0 0x10000>;
 428                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&clockgen 4 1>;
 430                         status = "disabled";
 431                 };
 432
 433                 i2c2: i2c@21a0000 {
 434                         compatible = "fsl,vf610-i2c";
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         reg = <0x0 0x21a0000 0x0 0x10000>;
 438                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 439                         clocks = <&clockgen 4 1>;
 440                         status = "disabled";
 441                 };
 442
 443                 i2c3: i2c@21b0000 {
 444                         compatible = "fsl,vf610-i2c";
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         reg = <0x0 0x21b0000 0x0 0x10000>;
 448                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 449                         clocks = <&clockgen 4 1>;
 450                         status = "disabled";
 451                 };
 452
 453                 duart0: serial@21c0500 {
 454                         compatible = "fsl,ns16550", "ns16550a";
 455                         reg = <0x00 0x21c0500 0x0 0x100>;
 456                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&clockgen 4 1>;
 458                 };
 459
 460                 duart1: serial@21c0600 {
 461                         compatible = "fsl,ns16550", "ns16550a";
 462                         reg = <0x00 0x21c0600 0x0 0x100>;
 463                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&clockgen 4 1>;
 465                 };
 466
 467                 duart2: serial@21d0500 {
 468                         compatible = "fsl,ns16550", "ns16550a";
 469                         reg = <0x0 0x21d0500 0x0 0x100>;
 470                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&clockgen 4 1>;
 472                 };
 473
 474                 duart3: serial@21d0600 {
 475                         compatible = "fsl,ns16550", "ns16550a";
 476                         reg = <0x0 0x21d0600 0x0 0x100>;
 477                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&clockgen 4 1>;
 479                 };
 480
 481                 gpio0: gpio@2300000 {
 482                         compatible = "fsl,qoriq-gpio";
 483                         reg = <0x0 0x2300000 0x0 0x10000>;
 484                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 485                         gpio-controller;
 486                         #gpio-cells = <2>;
 487                         interrupt-controller;
 488                         #interrupt-cells = <2>;
 489                 };
 490
 491                 gpio1: gpio@2310000 {
 492                         compatible = "fsl,qoriq-gpio";
 493                         reg = <0x0 0x2310000 0x0 0x10000>;
 494                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 495                         gpio-controller;
 496                         #gpio-cells = <2>;
 497                         interrupt-controller;
 498                         #interrupt-cells = <2>;
 499                 };
 500
 501                 gpio2: gpio@2320000 {
 502                         compatible = "fsl,qoriq-gpio";
 503                         reg = <0x0 0x2320000 0x0 0x10000>;
 504                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 505                         gpio-controller;
 506                         #gpio-cells = <2>;
 507                         interrupt-controller;
 508                         #interrupt-cells = <2>;
 509                 };
 510
 511                 gpio3: gpio@2330000 {
 512                         compatible = "fsl,qoriq-gpio";
 513                         reg = <0x0 0x2330000 0x0 0x10000>;
 514                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 515                         gpio-controller;
 516                         #gpio-cells = <2>;
 517                         interrupt-controller;
 518                         #interrupt-cells = <2>;
 519                 };
 520
 521                 lpuart0: serial@2950000 {
 522                         compatible = "fsl,ls1021a-lpuart";
 523                         reg = <0x0 0x2950000 0x0 0x1000>;
 524                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&clockgen 4 0>;
 526                         clock-names = "ipg";
 527                         status = "disabled";
 528                 };
 529
 530                 lpuart1: serial@2960000 {
 531                         compatible = "fsl,ls1021a-lpuart";
 532                         reg = <0x0 0x2960000 0x0 0x1000>;
 533                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&clockgen 4 1>;
 535                         clock-names = "ipg";
 536                         status = "disabled";
 537                 };
 538
 539                 lpuart2: serial@2970000 {
 540                         compatible = "fsl,ls1021a-lpuart";
 541                         reg = <0x0 0x2970000 0x0 0x1000>;
 542                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&clockgen 4 1>;
 544                         clock-names = "ipg";
 545                         status = "disabled";
 546                 };
 547
 548                 lpuart3: serial@2980000 {
 549                         compatible = "fsl,ls1021a-lpuart";
 550                         reg = <0x0 0x2980000 0x0 0x1000>;
 551                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&clockgen 4 1>;
 553                         clock-names = "ipg";
 554                         status = "disabled";
 555                 };
 556
 557                 lpuart4: serial@2990000 {
 558                         compatible = "fsl,ls1021a-lpuart";
 559                         reg = <0x0 0x2990000 0x0 0x1000>;
 560                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 561                         clocks = <&clockgen 4 1>;
 562                         clock-names = "ipg";
 563                         status = "disabled";
 564                 };
 565
 566                 lpuart5: serial@29a0000 {
 567                         compatible = "fsl,ls1021a-lpuart";
 568                         reg = <0x0 0x29a0000 0x0 0x1000>;
 569                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 570                         clocks = <&clockgen 4 1>;
 571                         clock-names = "ipg";
 572                         status = "disabled";
 573                 };
 574
 575                 wdog0: watchdog@2ad0000 {
 576                         compatible = "fsl,imx21-wdt";
 577                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 578                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 579                         clocks = <&clockgen 4 1>;
 580                         big-endian;
 581                 };
 582
 583                 edma0: edma@2c00000 {
 584                         #dma-cells = <2>;
 585                         compatible = "fsl,vf610-edma";
 586                         reg = <0x0 0x2c00000 0x0 0x10000>,
 587                               <0x0 0x2c10000 0x0 0x10000>,
 588                               <0x0 0x2c20000 0x0 0x10000>;
 589                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 590                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 591                         interrupt-names = "edma-tx", "edma-err";
 592                         dma-channels = <32>;
 593                         big-endian;
 594                         clock-names = "dmamux0", "dmamux1";
 595                         clocks = <&clockgen 4 1>,
 596                                  <&clockgen 4 1>;
 597                 };
 598
 599                 usb0: usb@2f00000 {
 600                         compatible = "snps,dwc3";
 601                         reg = <0x0 0x2f00000 0x0 0x10000>;
 602                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 603                         dr_mode = "host";
 604                         snps,quirk-frame-length-adjustment = <0x20>;
 605                         snps,dis_rxdet_inp3_quirk;
 606                 };
 607
 608                 usb1: usb@3000000 {
 609                         compatible = "snps,dwc3";
 610                         reg = <0x0 0x3000000 0x0 0x10000>;
 611                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 612                         dr_mode = "host";
 613                         snps,quirk-frame-length-adjustment = <0x20>;
 614                         snps,dis_rxdet_inp3_quirk;
 615                 };
 616
 617                 usb2: usb@3100000 {
 618                         compatible = "snps,dwc3";
 619                         reg = <0x0 0x3100000 0x0 0x10000>;
 620                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 621                         dr_mode = "host";
 622                         snps,quirk-frame-length-adjustment = <0x20>;
 623                         snps,dis_rxdet_inp3_quirk;
 624                 };
 625
 626                 sata: sata@3200000 {
 627                         compatible = "fsl,ls1046a-ahci";
 628                         reg = <0x0 0x3200000 0x0 0x10000>,
 629                                 <0x0 0x20140520 0x0 0x4>;
 630                         reg-names = "ahci", "sata-ecc";
 631                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 632                         clocks = <&clockgen 4 1>;
 633                 };
 634
 635                 msi1: msi-controller@1580000 {
 636                         compatible = "fsl,ls1046a-msi";
 637                         msi-controller;
 638                         reg = <0x0 0x1580000 0x0 0x10000>;
 639                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 640                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 641                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 642                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 643                 };
 644
 645                 msi2: msi-controller@1590000 {
 646                         compatible = "fsl,ls1046a-msi";
 647                         msi-controller;
 648                         reg = <0x0 0x1590000 0x0 0x10000>;
 649                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 652                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 653                 };
 654
 655                 msi3: msi-controller@15a0000 {
 656                         compatible = "fsl,ls1046a-msi";
 657                         msi-controller;
 658                         reg = <0x0 0x15a0000 0x0 0x10000>;
 659                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 660                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 663                 };
 664
 665         };
 666
 667         reserved-memory {
 668                 #address-cells = <2>;
 669                 #size-cells = <2>;
 670                 ranges;
 671
 672                 bman_fbpr: bman-fbpr {
 673                         compatible = "shared-dma-pool";
 674                         size = <0 0x1000000>;
 675                         alignment = <0 0x1000000>;
 676                         no-map;
 677                 };
 678
 679                 qman_fqd: qman-fqd {
 680                         compatible = "shared-dma-pool";
 681                         size = <0 0x800000>;
 682                         alignment = <0 0x800000>;
 683                         no-map;
 684                 };
 685
 686                 qman_pfdr: qman-pfdr {
 687                         compatible = "shared-dma-pool";
 688                         size = <0 0x2000000>;
 689                         alignment = <0 0x2000000>;
 690                         no-map;
 691                 };
 692         };
 693 };
 694
 695 #include "qoriq-qman-portals.dtsi"
 696 #include "qoriq-bman-portals.dtsi"