1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2019-2020 NXP
8 * Mingkai Hu <mingkai.hu@nxp.com>
13 #include "fsl-ls1046a.dtsi"
16 model = "LS1046A RDB Board";
17 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
27 stdout-path = "serial0:115200n8";
51 compatible = "ti,ina220";
53 shunt-resistor = <1000>;
57 compatible = "adi,adt7461";
62 compatible = "onnn,cat24c05", "atmel,24c04";
71 compatible = "nxp,pcf2129";
73 /* IRQ_RTC_B -> IRQ05, active low */
74 interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
81 /* NAND Flashe and CPLD on board */
82 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
83 0x2 0x0 0x0 0x7fb00000 0x00000100>;
87 compatible = "fsl,ifc-nand";
90 reg = <0x0 0x0 0x10000>;
93 cpld: board-control@2,0 {
94 compatible = "fsl,ls1046ardb-cpld";
95 reg = <0x2 0x0 0x0000100>;
102 s25fs512s0: flash@0 {
103 compatible = "jedec,spi-nor";
104 #address-cells = <1>;
106 spi-max-frequency = <50000000>;
107 spi-rx-bus-width = <4>;
108 spi-tx-bus-width = <1>;
112 s25fs512s1: flash@1 {
113 compatible = "jedec,spi-nor";
114 #address-cells = <1>;
116 spi-max-frequency = <50000000>;
117 spi-rx-bus-width = <4>;
118 spi-tx-bus-width = <1>;
127 #include "fsl-ls1046-post.dtsi"
131 phy-handle = <&rgmii_phy1>;
132 phy-connection-type = "rgmii-id";
136 phy-handle = <&rgmii_phy2>;
137 phy-connection-type = "rgmii-id";
141 phy-handle = <&sgmii_phy1>;
142 phy-connection-type = "sgmii";
146 phy-handle = <&sgmii_phy2>;
147 phy-connection-type = "sgmii";
150 ethernet@f0000 { /* 10GEC1 */
151 phy-handle = <&aqr106_phy>;
152 phy-connection-type = "xgmii";
155 ethernet@f2000 { /* 10GEC2 */
156 phy-connection-type = "10gbase-r";
157 managed = "in-band-status";
161 rgmii_phy1: ethernet-phy@1 {
165 rgmii_phy2: ethernet-phy@2 {
169 sgmii_phy1: ethernet-phy@3 {
173 sgmii_phy2: ethernet-phy@4 {
179 aqr106_phy: ethernet-phy@0 {
180 compatible = "ethernet-phy-ieee802.3-c45";
181 interrupts = <0 131 4>;