2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright 2014-2015, Freescale Semiconductor
6 * Mingkai Hu <Mingkai.hu@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
65 compatible = "arm,cortex-a53";
67 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>;
73 compatible = "arm,cortex-a53";
75 clocks = <&clockgen 1 0>;
76 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a53";
83 clocks = <&clockgen 1 0>;
84 next-level-cache = <&l2>;
89 compatible = "arm,cortex-a53";
91 clocks = <&clockgen 1 0>;
92 next-level-cache = <&l2>;
101 device_type = "memory";
102 reg = <0x0 0x80000000 0 0x80000000>;
103 /* DRAM space 1, size: 2GiB DRAM */
107 compatible = "fixed-clock";
109 clock-frequency = <100000000>;
110 clock-output-names = "sysclk";
114 compatible ="syscon-reboot";
121 compatible = "arm,armv8-timer";
122 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
123 <1 14 0xf08>, /* Physical Non-Secure PPI */
124 <1 11 0xf08>, /* Virtual PPI */
125 <1 10 0xf08>; /* Hypervisor PPI */
130 compatible = "arm,armv8-pmuv3";
131 interrupts = <0 106 0x4>,
135 interrupt-affinity = <&cpu0>,
141 gic: interrupt-controller@1400000 {
142 compatible = "arm,gic-400";
143 #interrupt-cells = <3>;
144 interrupt-controller;
145 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
146 <0x0 0x1402000 0 0x2000>, /* GICC */
147 <0x0 0x1404000 0 0x2000>, /* GICH */
148 <0x0 0x1406000 0 0x2000>; /* GICV */
149 interrupts = <1 9 0xf08>;
153 compatible = "simple-bus";
154 #address-cells = <2>;
158 clockgen: clocking@1ee1000 {
159 compatible = "fsl,ls1043a-clockgen";
160 reg = <0x0 0x1ee1000 0x0 0x1000>;
166 compatible = "fsl,ls1043a-scfg", "syscon";
167 reg = <0x0 0x1570000 0x0 0x10000>;
171 crypto: crypto@1700000 {
172 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
175 #address-cells = <1>;
177 ranges = <0x0 0x00 0x1700000 0x100000>;
178 reg = <0x00 0x1700000 0x0 0x100000>;
179 interrupts = <0 75 0x4>;
183 compatible = "fsl,sec-v5.4-job-ring",
184 "fsl,sec-v5.0-job-ring",
185 "fsl,sec-v4.0-job-ring";
186 reg = <0x10000 0x10000>;
187 interrupts = <0 71 0x4>;
191 compatible = "fsl,sec-v5.4-job-ring",
192 "fsl,sec-v5.0-job-ring",
193 "fsl,sec-v4.0-job-ring";
194 reg = <0x20000 0x10000>;
195 interrupts = <0 72 0x4>;
199 compatible = "fsl,sec-v5.4-job-ring",
200 "fsl,sec-v5.0-job-ring",
201 "fsl,sec-v4.0-job-ring";
202 reg = <0x30000 0x10000>;
203 interrupts = <0 73 0x4>;
207 compatible = "fsl,sec-v5.4-job-ring",
208 "fsl,sec-v5.0-job-ring",
209 "fsl,sec-v4.0-job-ring";
210 reg = <0x40000 0x10000>;
211 interrupts = <0 74 0x4>;
216 compatible = "fsl,ls1043a-dcfg", "syscon";
217 reg = <0x0 0x1ee0000 0x0 0x10000>;
222 compatible = "fsl,ifc", "simple-bus";
223 reg = <0x0 0x1530000 0x0 0x10000>;
224 interrupts = <0 43 0x4>;
227 qspi: quadspi@1550000 {
228 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
229 #address-cells = <1>;
231 reg = <0x0 0x1550000 0x0 0x10000>,
232 <0x0 0x40000000 0x0 0x4000000>;
233 reg-names = "QuadSPI", "QuadSPI-memory";
234 interrupts = <0 99 0x4>;
235 clock-names = "qspi_en", "qspi";
236 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
241 esdhc: esdhc@1560000 {
242 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
243 reg = <0x0 0x1560000 0x0 0x10000>;
244 interrupts = <0 62 0x4>;
245 clock-frequency = <0>;
246 voltage-ranges = <1800 1800 3300 3300>;
252 ddr: memory-controller@1080000 {
253 compatible = "fsl,qoriq-memory-controller";
254 reg = <0x0 0x1080000 0x0 0x1000>;
255 interrupts = <0 144 0x4>;
259 dspi0: dspi@2100000 {
260 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
261 #address-cells = <1>;
263 reg = <0x0 0x2100000 0x0 0x10000>;
264 interrupts = <0 64 0x4>;
265 clock-names = "dspi";
266 clocks = <&clockgen 4 0>;
267 spi-num-chipselects = <5>;
272 dspi1: dspi@2110000 {
273 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
274 #address-cells = <1>;
276 reg = <0x0 0x2110000 0x0 0x10000>;
277 interrupts = <0 65 0x4>;
278 clock-names = "dspi";
279 clocks = <&clockgen 4 0>;
280 spi-num-chipselects = <5>;
286 compatible = "fsl,vf610-i2c";
287 #address-cells = <1>;
289 reg = <0x0 0x2180000 0x0 0x10000>;
290 interrupts = <0 56 0x4>;
292 clocks = <&clockgen 4 0>;
293 dmas = <&edma0 1 39>,
295 dma-names = "tx", "rx";
300 compatible = "fsl,vf610-i2c";
301 #address-cells = <1>;
303 reg = <0x0 0x2190000 0x0 0x10000>;
304 interrupts = <0 57 0x4>;
306 clocks = <&clockgen 4 0>;
311 compatible = "fsl,vf610-i2c";
312 #address-cells = <1>;
314 reg = <0x0 0x21a0000 0x0 0x10000>;
315 interrupts = <0 58 0x4>;
317 clocks = <&clockgen 4 0>;
322 compatible = "fsl,vf610-i2c";
323 #address-cells = <1>;
325 reg = <0x0 0x21b0000 0x0 0x10000>;
326 interrupts = <0 59 0x4>;
328 clocks = <&clockgen 4 0>;
332 duart0: serial@21c0500 {
333 compatible = "fsl,ns16550", "ns16550a";
334 reg = <0x00 0x21c0500 0x0 0x100>;
335 interrupts = <0 54 0x4>;
336 clocks = <&clockgen 4 0>;
339 duart1: serial@21c0600 {
340 compatible = "fsl,ns16550", "ns16550a";
341 reg = <0x00 0x21c0600 0x0 0x100>;
342 interrupts = <0 54 0x4>;
343 clocks = <&clockgen 4 0>;
346 duart2: serial@21d0500 {
347 compatible = "fsl,ns16550", "ns16550a";
348 reg = <0x0 0x21d0500 0x0 0x100>;
349 interrupts = <0 55 0x4>;
350 clocks = <&clockgen 4 0>;
353 duart3: serial@21d0600 {
354 compatible = "fsl,ns16550", "ns16550a";
355 reg = <0x0 0x21d0600 0x0 0x100>;
356 interrupts = <0 55 0x4>;
357 clocks = <&clockgen 4 0>;
360 gpio1: gpio@2300000 {
361 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
362 reg = <0x0 0x2300000 0x0 0x10000>;
363 interrupts = <0 66 0x4>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
370 gpio2: gpio@2310000 {
371 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
372 reg = <0x0 0x2310000 0x0 0x10000>;
373 interrupts = <0 67 0x4>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
380 gpio3: gpio@2320000 {
381 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
382 reg = <0x0 0x2320000 0x0 0x10000>;
383 interrupts = <0 68 0x4>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
390 gpio4: gpio@2330000 {
391 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
392 reg = <0x0 0x2330000 0x0 0x10000>;
393 interrupts = <0 134 0x4>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
400 lpuart0: serial@2950000 {
401 compatible = "fsl,ls1021a-lpuart";
402 reg = <0x0 0x2950000 0x0 0x1000>;
403 interrupts = <0 48 0x4>;
404 clocks = <&clockgen 0 0>;
409 lpuart1: serial@2960000 {
410 compatible = "fsl,ls1021a-lpuart";
411 reg = <0x0 0x2960000 0x0 0x1000>;
412 interrupts = <0 49 0x4>;
413 clocks = <&clockgen 4 0>;
418 lpuart2: serial@2970000 {
419 compatible = "fsl,ls1021a-lpuart";
420 reg = <0x0 0x2970000 0x0 0x1000>;
421 interrupts = <0 50 0x4>;
422 clocks = <&clockgen 4 0>;
427 lpuart3: serial@2980000 {
428 compatible = "fsl,ls1021a-lpuart";
429 reg = <0x0 0x2980000 0x0 0x1000>;
430 interrupts = <0 51 0x4>;
431 clocks = <&clockgen 4 0>;
436 lpuart4: serial@2990000 {
437 compatible = "fsl,ls1021a-lpuart";
438 reg = <0x0 0x2990000 0x0 0x1000>;
439 interrupts = <0 52 0x4>;
440 clocks = <&clockgen 4 0>;
445 lpuart5: serial@29a0000 {
446 compatible = "fsl,ls1021a-lpuart";
447 reg = <0x0 0x29a0000 0x0 0x1000>;
448 interrupts = <0 53 0x4>;
449 clocks = <&clockgen 4 0>;
454 wdog0: wdog@2ad0000 {
455 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
456 reg = <0x0 0x2ad0000 0x0 0x10000>;
457 interrupts = <0 83 0x4>;
458 clocks = <&clockgen 4 0>;
459 clock-names = "wdog";
463 edma0: edma@2c00000 {
465 compatible = "fsl,vf610-edma";
466 reg = <0x0 0x2c00000 0x0 0x10000>,
467 <0x0 0x2c10000 0x0 0x10000>,
468 <0x0 0x2c20000 0x0 0x10000>;
469 interrupts = <0 103 0x4>,
471 interrupt-names = "edma-tx", "edma-err";
474 clock-names = "dmamux0", "dmamux1";
475 clocks = <&clockgen 4 0>,
480 compatible = "snps,dwc3";
481 reg = <0x0 0x2f00000 0x0 0x10000>;
482 interrupts = <0 60 0x4>;
484 snps,quirk-frame-length-adjustment = <0x20>;
485 snps,dis_rxdet_inp3_quirk;
489 compatible = "snps,dwc3";
490 reg = <0x0 0x3000000 0x0 0x10000>;
491 interrupts = <0 61 0x4>;
493 snps,quirk-frame-length-adjustment = <0x20>;
494 snps,dis_rxdet_inp3_quirk;
498 compatible = "snps,dwc3";
499 reg = <0x0 0x3100000 0x0 0x10000>;
500 interrupts = <0 63 0x4>;
502 snps,quirk-frame-length-adjustment = <0x20>;
503 snps,dis_rxdet_inp3_quirk;
507 compatible = "fsl,ls1043a-ahci";
508 reg = <0x0 0x3200000 0x0 0x10000>;
509 interrupts = <0 69 0x4>;
510 clocks = <&clockgen 4 0>;
514 msi1: msi-controller1@1571000 {
515 compatible = "fsl,1s1043a-msi";
516 reg = <0x0 0x1571000 0x0 0x8>;
518 interrupts = <0 116 0x4>;
521 msi2: msi-controller2@1572000 {
522 compatible = "fsl,1s1043a-msi";
523 reg = <0x0 0x1572000 0x0 0x8>;
525 interrupts = <0 126 0x4>;
528 msi3: msi-controller3@1573000 {
529 compatible = "fsl,1s1043a-msi";
530 reg = <0x0 0x1573000 0x0 0x8>;
532 interrupts = <0 160 0x4>;
536 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
537 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
538 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
539 reg-names = "regs", "config";
540 interrupts = <0 118 0x4>, /* controller interrupt */
541 <0 117 0x4>; /* PME interrupt */
542 interrupt-names = "intr", "pme";
543 #address-cells = <3>;
548 bus-range = <0x0 0xff>;
549 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
550 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
551 msi-parent = <&msi1>;
552 #interrupt-cells = <1>;
553 interrupt-map-mask = <0 0 0 7>;
554 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
555 <0000 0 0 2 &gic 0 111 0x4>,
556 <0000 0 0 3 &gic 0 112 0x4>,
557 <0000 0 0 4 &gic 0 113 0x4>;
561 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
562 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
563 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
564 reg-names = "regs", "config";
565 interrupts = <0 128 0x4>,
567 interrupt-names = "intr", "pme";
568 #address-cells = <3>;
573 bus-range = <0x0 0xff>;
574 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
575 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
576 msi-parent = <&msi2>;
577 #interrupt-cells = <1>;
578 interrupt-map-mask = <0 0 0 7>;
579 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
580 <0000 0 0 2 &gic 0 121 0x4>,
581 <0000 0 0 3 &gic 0 122 0x4>,
582 <0000 0 0 4 &gic 0 123 0x4>;
586 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
587 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
588 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
589 reg-names = "regs", "config";
590 interrupts = <0 162 0x4>,
592 interrupt-names = "intr", "pme";
593 #address-cells = <3>;
598 bus-range = <0x0 0xff>;
599 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
600 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
601 msi-parent = <&msi3>;
602 #interrupt-cells = <1>;
603 interrupt-map-mask = <0 0 0 7>;
604 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
605 <0000 0 0 2 &gic 0 155 0x4>,
606 <0000 0 0 3 &gic 0 156 0x4>,
607 <0000 0 0 4 &gic 0 157 0x4>;