arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1043A family SoC.
   4  *
   5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   6  * Copyright 2018, 2020 NXP
   7  *
   8  * Mingkai Hu <Mingkai.hu@freescale.com>
   9  */
  10
  11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 / {
  17         compatible = "fsl,ls1043a";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 crypto = &crypto;
  24                 fman0 = &fman0;
  25                 ethernet0 = &enet0;
  26                 ethernet1 = &enet1;
  27                 ethernet2 = &enet2;
  28                 ethernet3 = &enet3;
  29                 ethernet4 = &enet4;
  30                 ethernet5 = &enet5;
  31                 ethernet6 = &enet6;
  32                 rtc1 = &ftm_alarm0;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 /*
  40                  * We expect the enable-method for cpu's to be "psci", but this
  41                  * is dependent on the SoC FW, which will fill this in.
  42                  *
  43                  * Currently supported enable-method is psci v0.2
  44                  */
  45                 cpu0: cpu@0 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a53";
  48                         reg = <0x0>;
  49                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  50                         next-level-cache = <&l2>;
  51                         cpu-idle-states = <&CPU_PH20>;
  52                         #cooling-cells = <2>;
  53                 };
  54
  55                 cpu1: cpu@1 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         reg = <0x1>;
  59                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  60                         next-level-cache = <&l2>;
  61                         cpu-idle-states = <&CPU_PH20>;
  62                         #cooling-cells = <2>;
  63                 };
  64
  65                 cpu2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53";
  68                         reg = <0x2>;
  69                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  70                         next-level-cache = <&l2>;
  71                         cpu-idle-states = <&CPU_PH20>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu3: cpu@3 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53";
  78                         reg = <0x3>;
  79                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  80                         next-level-cache = <&l2>;
  81                         cpu-idle-states = <&CPU_PH20>;
  82                         #cooling-cells = <2>;
  83                 };
  84
  85                 l2: l2-cache {
  86                         compatible = "cache";
  87                 };
  88         };
  89
  90         idle-states {
  91                 /*
  92                  * PSCI node is not added default, U-boot will add missing
  93                  * parts if it determines to use PSCI.
  94                  */
  95                 entry-method = "psci";
  96
  97                 CPU_PH20: cpu-ph20 {
  98                         compatible = "arm,idle-state";
  99                         idle-state-name = "PH20";
 100                         arm,psci-suspend-param = <0x0>;
 101                         entry-latency-us = <1000>;
 102                         exit-latency-us = <1000>;
 103                         min-residency-us = <3000>;
 104                 };
 105         };
 106
 107         memory@80000000 {
 108                 device_type = "memory";
 109                 reg = <0x0 0x80000000 0 0x80000000>;
 110                       /* DRAM space 1, size: 2GiB DRAM */
 111         };
 112
 113         reserved-memory {
 114                 #address-cells = <2>;
 115                 #size-cells = <2>;
 116                 ranges;
 117
 118                 bman_fbpr: bman-fbpr {
 119                         compatible = "shared-dma-pool";
 120                         size = <0 0x1000000>;
 121                         alignment = <0 0x1000000>;
 122                         no-map;
 123                 };
 124
 125                 qman_fqd: qman-fqd {
 126                         compatible = "shared-dma-pool";
 127                         size = <0 0x400000>;
 128                         alignment = <0 0x400000>;
 129                         no-map;
 130                 };
 131
 132                 qman_pfdr: qman-pfdr {
 133                         compatible = "shared-dma-pool";
 134                         size = <0 0x2000000>;
 135                         alignment = <0 0x2000000>;
 136                         no-map;
 137                 };
 138         };
 139
 140         sysclk: sysclk {
 141                 compatible = "fixed-clock";
 142                 #clock-cells = <0>;
 143                 clock-frequency = <100000000>;
 144                 clock-output-names = "sysclk";
 145         };
 146
 147         reboot {
 148                 compatible = "syscon-reboot";
 149                 regmap = <&dcfg>;
 150                 offset = <0xb0>;
 151                 mask = <0x02>;
 152         };
 153
 154         thermal-zones {
 155                 ddr-controller {
 156                         polling-delay-passive = <1000>;
 157                         polling-delay = <5000>;
 158                         thermal-sensors = <&tmu 0>;
 159
 160                         trips {
 161                                 ddr-ctrler-alert {
 162                                         temperature = <85000>;
 163                                         hysteresis = <2000>;
 164                                         type = "passive";
 165                                 };
 166
 167                                 ddr-ctrler-crit {
 168                                         temperature = <95000>;
 169                                         hysteresis = <2000>;
 170                                         type = "critical";
 171                                 };
 172                         };
 173                 };
 174
 175                 serdes {
 176                         polling-delay-passive = <1000>;
 177                         polling-delay = <5000>;
 178                         thermal-sensors = <&tmu 1>;
 179
 180                         trips {
 181                                 serdes-alert {
 182                                         temperature = <85000>;
 183                                         hysteresis = <2000>;
 184                                         type = "passive";
 185                                 };
 186
 187                                 serdes-crit {
 188                                         temperature = <95000>;
 189                                         hysteresis = <2000>;
 190                                         type = "critical";
 191                                 };
 192                         };
 193                 };
 194
 195                 fman {
 196                         polling-delay-passive = <1000>;
 197                         polling-delay = <5000>;
 198                         thermal-sensors = <&tmu 2>;
 199
 200                         trips {
 201                                 fman-alert {
 202                                         temperature = <85000>;
 203                                         hysteresis = <2000>;
 204                                         type = "passive";
 205                                 };
 206
 207                                 fman-crit {
 208                                         temperature = <95000>;
 209                                         hysteresis = <2000>;
 210                                         type = "critical";
 211                                 };
 212                         };
 213                 };
 214
 215                 core-cluster {
 216                         polling-delay-passive = <1000>;
 217                         polling-delay = <5000>;
 218                         thermal-sensors = <&tmu 3>;
 219
 220                         trips {
 221                                 core_cluster_alert: core-cluster-alert {
 222                                         temperature = <85000>;
 223                                         hysteresis = <2000>;
 224                                         type = "passive";
 225                                 };
 226
 227                                 core_cluster_crit: core-cluster-crit {
 228                                         temperature = <95000>;
 229                                         hysteresis = <2000>;
 230                                         type = "critical";
 231                                 };
 232                         };
 233
 234                         cooling-maps {
 235                                 map0 {
 236                                         trip = <&core_cluster_alert>;
 237                                         cooling-device =
 238                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 239                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 240                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 241                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 242                                 };
 243                         };
 244                 };
 245
 246                 sec {
 247                         polling-delay-passive = <1000>;
 248                         polling-delay = <5000>;
 249                         thermal-sensors = <&tmu 4>;
 250
 251                         trips {
 252                                 sec-alert {
 253                                         temperature = <85000>;
 254                                         hysteresis = <2000>;
 255                                         type = "passive";
 256                                 };
 257
 258                                 sec-crit {
 259                                         temperature = <95000>;
 260                                         hysteresis = <2000>;
 261                                         type = "critical";
 262                                 };
 263                         };
 264                 };
 265         };
 266
 267         timer {
 268                 compatible = "arm,armv8-timer";
 269                 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
 270                              <1 14 0xf08>, /* Physical Non-Secure PPI */
 271                              <1 11 0xf08>, /* Virtual PPI */
 272                              <1 10 0xf08>; /* Hypervisor PPI */
 273                 fsl,erratum-a008585;
 274         };
 275
 276         pmu {
 277                 compatible = "arm,armv8-pmuv3";
 278                 interrupts = <0 106 0x4>,
 279                              <0 107 0x4>,
 280                              <0 95 0x4>,
 281                              <0 97 0x4>;
 282                 interrupt-affinity = <&cpu0>,
 283                                      <&cpu1>,
 284                                      <&cpu2>,
 285                                      <&cpu3>;
 286         };
 287
 288         gic: interrupt-controller@1400000 {
 289                 compatible = "arm,gic-400";
 290                 #interrupt-cells = <3>;
 291                 interrupt-controller;
 292                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
 293                       <0x0 0x1402000 0 0x2000>, /* GICC */
 294                       <0x0 0x1404000 0 0x2000>, /* GICH */
 295                       <0x0 0x1406000 0 0x2000>; /* GICV */
 296                 interrupts = <1 9 0xf08>;
 297         };
 298
 299         soc: soc {
 300                 compatible = "simple-bus";
 301                 #address-cells = <2>;
 302                 #size-cells = <2>;
 303                 ranges;
 304                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 305                 dma-coherent;
 306
 307                 clockgen: clocking@1ee1000 {
 308                         compatible = "fsl,ls1043a-clockgen";
 309                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 310                         #clock-cells = <2>;
 311                         clocks = <&sysclk>;
 312                 };
 313
 314                 scfg: scfg@1570000 {
 315                         compatible = "fsl,ls1043a-scfg", "syscon";
 316                         reg = <0x0 0x1570000 0x0 0x10000>;
 317                         big-endian;
 318                         #address-cells = <1>;
 319                         #size-cells = <1>;
 320                         ranges = <0x0 0x0 0x1570000 0x10000>;
 321
 322                         extirq: interrupt-controller@1ac {
 323                                 compatible = "fsl,ls1043a-extirq";
 324                                 #interrupt-cells = <2>;
 325                                 #address-cells = <0>;
 326                                 interrupt-controller;
 327                                 reg = <0x1ac 4>;
 328                                 interrupt-map =
 329                                         <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 330                                         <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 331                                         <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 332                                         <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 333                                         <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 334                                         <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 335                                         <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 336                                         <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 337                                         <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 338                                         <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 339                                         <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 340                                         <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 341                                 interrupt-map-mask = <0xf 0x0>;
 342                         };
 343                 };
 344
 345                 crypto: crypto@1700000 {
 346                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 347                                      "fsl,sec-v4.0";
 348                         fsl,sec-era = <3>;
 349                         #address-cells = <1>;
 350                         #size-cells = <1>;
 351                         ranges = <0x0 0x00 0x1700000 0x100000>;
 352                         reg = <0x00 0x1700000 0x0 0x100000>;
 353                         interrupts = <0 75 0x4>;
 354                         dma-coherent;
 355
 356                         sec_jr0: jr@10000 {
 357                                 compatible = "fsl,sec-v5.4-job-ring",
 358                                              "fsl,sec-v5.0-job-ring",
 359                                              "fsl,sec-v4.0-job-ring";
 360                                 reg = <0x10000 0x10000>;
 361                                 interrupts = <0 71 0x4>;
 362                         };
 363
 364                         sec_jr1: jr@20000 {
 365                                 compatible = "fsl,sec-v5.4-job-ring",
 366                                              "fsl,sec-v5.0-job-ring",
 367                                              "fsl,sec-v4.0-job-ring";
 368                                 reg = <0x20000 0x10000>;
 369                                 interrupts = <0 72 0x4>;
 370                         };
 371
 372                         sec_jr2: jr@30000 {
 373                                 compatible = "fsl,sec-v5.4-job-ring",
 374                                              "fsl,sec-v5.0-job-ring",
 375                                              "fsl,sec-v4.0-job-ring";
 376                                 reg = <0x30000 0x10000>;
 377                                 interrupts = <0 73 0x4>;
 378                         };
 379
 380                         sec_jr3: jr@40000 {
 381                                 compatible = "fsl,sec-v5.4-job-ring",
 382                                              "fsl,sec-v5.0-job-ring",
 383                                              "fsl,sec-v4.0-job-ring";
 384                                 reg = <0x40000 0x10000>;
 385                                 interrupts = <0 74 0x4>;
 386                         };
 387                 };
 388
 389                 sfp: efuse@1e80000 {
 390                         compatible = "fsl,ls1021a-sfp";
 391                         reg = <0x0 0x1e80000 0x0 0x10000>;
 392                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 393                                             QORIQ_CLK_PLL_DIV(4)>;
 394                         clock-names = "sfp";
 395                 };
 396
 397                 dcfg: dcfg@1ee0000 {
 398                         compatible = "fsl,ls1043a-dcfg", "syscon";
 399                         reg = <0x0 0x1ee0000 0x0 0x1000>;
 400                         big-endian;
 401                 };
 402
 403                 ifc: memory-controller@1530000 {
 404                         compatible = "fsl,ifc";
 405                         reg = <0x0 0x1530000 0x0 0x10000>;
 406                         interrupts = <0 43 0x4>;
 407                 };
 408
 409                 qspi: spi@1550000 {
 410                         compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         reg = <0x0 0x1550000 0x0 0x10000>,
 414                                 <0x0 0x40000000 0x0 0x4000000>;
 415                         reg-names = "QuadSPI", "QuadSPI-memory";
 416                         interrupts = <0 99 0x4>;
 417                         clock-names = "qspi_en", "qspi";
 418                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 419                                             QORIQ_CLK_PLL_DIV(1)>,
 420                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 421                                             QORIQ_CLK_PLL_DIV(1)>;
 422                         status = "disabled";
 423                 };
 424
 425                 esdhc: esdhc@1560000 {
 426                         compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
 427                         reg = <0x0 0x1560000 0x0 0x10000>;
 428                         interrupts = <0 62 0x4>;
 429                         clock-frequency = <0>;
 430                         voltage-ranges = <1800 1800 3300 3300>;
 431                         sdhci,auto-cmd12;
 432                         big-endian;
 433                         bus-width = <4>;
 434                 };
 435
 436                 ddr: memory-controller@1080000 {
 437                         compatible = "fsl,qoriq-memory-controller";
 438                         reg = <0x0 0x1080000 0x0 0x1000>;
 439                         interrupts = <0 144 0x4>;
 440                         big-endian;
 441                 };
 442
 443                 tmu: tmu@1f00000 {
 444                         compatible = "fsl,qoriq-tmu";
 445                         reg = <0x0 0x1f00000 0x0 0x10000>;
 446                         interrupts = <0 33 0x4>;
 447                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
 448                         fsl,tmu-calibration = <0x00000000 0x00000023
 449                                                0x00000001 0x0000002a
 450                                                0x00000002 0x00000031
 451                                                0x00000003 0x00000037
 452                                                0x00000004 0x0000003e
 453                                                0x00000005 0x00000044
 454                                                0x00000006 0x0000004b
 455                                                0x00000007 0x00000051
 456                                                0x00000008 0x00000058
 457                                                0x00000009 0x0000005e
 458                                                0x0000000a 0x00000065
 459                                                0x0000000b 0x0000006b
 460
 461                                                0x00010000 0x00000023
 462                                                0x00010001 0x0000002b
 463                                                0x00010002 0x00000033
 464                                                0x00010003 0x0000003b
 465                                                0x00010004 0x00000043
 466                                                0x00010005 0x0000004b
 467                                                0x00010006 0x00000054
 468                                                0x00010007 0x0000005c
 469                                                0x00010008 0x00000064
 470                                                0x00010009 0x0000006c
 471
 472                                                0x00020000 0x00000021
 473                                                0x00020001 0x0000002c
 474                                                0x00020002 0x00000036
 475                                                0x00020003 0x00000040
 476                                                0x00020004 0x0000004b
 477                                                0x00020005 0x00000055
 478                                                0x00020006 0x0000005f
 479
 480                                                0x00030000 0x00000013
 481                                                0x00030001 0x0000001d
 482                                                0x00030002 0x00000028
 483                                                0x00030003 0x00000032
 484                                                0x00030004 0x0000003d
 485                                                0x00030005 0x00000047
 486                                                0x00030006 0x00000052
 487                                                0x00030007 0x0000005c>;
 488                         #thermal-sensor-cells = <1>;
 489                 };
 490
 491                 qman: qman@1880000 {
 492                         compatible = "fsl,qman";
 493                         reg = <0x0 0x1880000 0x0 0x10000>;
 494                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 495                         memory-region = <&qman_fqd &qman_pfdr>;
 496                 };
 497
 498                 bman: bman@1890000 {
 499                         compatible = "fsl,bman";
 500                         reg = <0x0 0x1890000 0x0 0x10000>;
 501                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 502                         memory-region = <&bman_fbpr>;
 503                 };
 504
 505                 bportals: bman-portals@508000000 {
 506                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 507                 };
 508
 509                 qportals: qman-portals@500000000 {
 510                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 511                 };
 512
 513                 dspi0: spi@2100000 {
 514                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         reg = <0x0 0x2100000 0x0 0x10000>;
 518                         interrupts = <0 64 0x4>;
 519                         clock-names = "dspi";
 520                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 521                                             QORIQ_CLK_PLL_DIV(1)>;
 522                         spi-num-chipselects = <5>;
 523                         big-endian;
 524                         status = "disabled";
 525                 };
 526
 527                 dspi1: spi@2110000 {
 528                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         reg = <0x0 0x2110000 0x0 0x10000>;
 532                         interrupts = <0 65 0x4>;
 533                         clock-names = "dspi";
 534                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 535                                             QORIQ_CLK_PLL_DIV(1)>;
 536                         spi-num-chipselects = <5>;
 537                         big-endian;
 538                         status = "disabled";
 539                 };
 540
 541                 i2c0: i2c@2180000 {
 542                         compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         reg = <0x0 0x2180000 0x0 0x10000>;
 546                         interrupts = <0 56 0x4>;
 547                         clock-names = "i2c";
 548                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 549                                             QORIQ_CLK_PLL_DIV(1)>;
 550                         dmas = <&edma0 1 38>,
 551                                <&edma0 1 39>;
 552                         dma-names = "rx", "tx";
 553                         status = "disabled";
 554                 };
 555
 556                 i2c1: i2c@2190000 {
 557                         compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         reg = <0x0 0x2190000 0x0 0x10000>;
 561                         interrupts = <0 57 0x4>;
 562                         clock-names = "i2c";
 563                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 564                                             QORIQ_CLK_PLL_DIV(1)>;
 565                         scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 566                         status = "disabled";
 567                 };
 568
 569                 i2c2: i2c@21a0000 {
 570                         compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
 571                         #address-cells = <1>;
 572                         #size-cells = <0>;
 573                         reg = <0x0 0x21a0000 0x0 0x10000>;
 574                         interrupts = <0 58 0x4>;
 575                         clock-names = "i2c";
 576                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 577                                             QORIQ_CLK_PLL_DIV(1)>;
 578                         scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 579                         status = "disabled";
 580                 };
 581
 582                 i2c3: i2c@21b0000 {
 583                         compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         reg = <0x0 0x21b0000 0x0 0x10000>;
 587                         interrupts = <0 59 0x4>;
 588                         clock-names = "i2c";
 589                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 590                                             QORIQ_CLK_PLL_DIV(1)>;
 591                         scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 592                         status = "disabled";
 593                 };
 594
 595                 duart0: serial@21c0500 {
 596                         compatible = "fsl,ns16550", "ns16550a";
 597                         reg = <0x00 0x21c0500 0x0 0x100>;
 598                         interrupts = <0 54 0x4>;
 599                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 600                                             QORIQ_CLK_PLL_DIV(1)>;
 601                 };
 602
 603                 duart1: serial@21c0600 {
 604                         compatible = "fsl,ns16550", "ns16550a";
 605                         reg = <0x00 0x21c0600 0x0 0x100>;
 606                         interrupts = <0 54 0x4>;
 607                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 608                                             QORIQ_CLK_PLL_DIV(1)>;
 609                 };
 610
 611                 duart2: serial@21d0500 {
 612                         compatible = "fsl,ns16550", "ns16550a";
 613                         reg = <0x0 0x21d0500 0x0 0x100>;
 614                         interrupts = <0 55 0x4>;
 615                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 616                                             QORIQ_CLK_PLL_DIV(1)>;
 617                 };
 618
 619                 duart3: serial@21d0600 {
 620                         compatible = "fsl,ns16550", "ns16550a";
 621                         reg = <0x0 0x21d0600 0x0 0x100>;
 622                         interrupts = <0 55 0x4>;
 623                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 624                                             QORIQ_CLK_PLL_DIV(1)>;
 625                 };
 626
 627                 gpio1: gpio@2300000 {
 628                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 629                         reg = <0x0 0x2300000 0x0 0x10000>;
 630                         interrupts = <0 66 0x4>;
 631                         gpio-controller;
 632                         #gpio-cells = <2>;
 633                         interrupt-controller;
 634                         #interrupt-cells = <2>;
 635                 };
 636
 637                 gpio2: gpio@2310000 {
 638                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 639                         reg = <0x0 0x2310000 0x0 0x10000>;
 640                         interrupts = <0 67 0x4>;
 641                         gpio-controller;
 642                         #gpio-cells = <2>;
 643                         interrupt-controller;
 644                         #interrupt-cells = <2>;
 645                 };
 646
 647                 gpio3: gpio@2320000 {
 648                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 649                         reg = <0x0 0x2320000 0x0 0x10000>;
 650                         interrupts = <0 68 0x4>;
 651                         gpio-controller;
 652                         #gpio-cells = <2>;
 653                         interrupt-controller;
 654                         #interrupt-cells = <2>;
 655                 };
 656
 657                 gpio4: gpio@2330000 {
 658                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 659                         reg = <0x0 0x2330000 0x0 0x10000>;
 660                         interrupts = <0 134 0x4>;
 661                         gpio-controller;
 662                         #gpio-cells = <2>;
 663                         interrupt-controller;
 664                         #interrupt-cells = <2>;
 665                 };
 666
 667                 uqe: uqe@2400000 {
 668                         #address-cells = <1>;
 669                         #size-cells = <1>;
 670                         compatible = "fsl,qe", "simple-bus";
 671                         ranges = <0x0 0x0 0x2400000 0x40000>;
 672                         reg = <0x0 0x2400000 0x0 0x480>;
 673                         brg-frequency = <100000000>;
 674                         bus-frequency = <200000000>;
 675                         fsl,qe-num-riscs = <1>;
 676                         fsl,qe-num-snums = <28>;
 677
 678                         qeic: qeic@80 {
 679                                 compatible = "fsl,qe-ic";
 680                                 reg = <0x80 0x80>;
 681                                 #address-cells = <0>;
 682                                 interrupt-controller;
 683                                 #interrupt-cells = <1>;
 684                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 685                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 686                         };
 687
 688                         si1: si@700 {
 689                                 #address-cells = <1>;
 690                                 #size-cells = <0>;
 691                                 compatible = "fsl,ls1043-qe-si",
 692                                                 "fsl,t1040-qe-si";
 693                                 reg = <0x700 0x80>;
 694                         };
 695
 696                         siram1: siram@1000 {
 697                                 #address-cells = <1>;
 698                                 #size-cells = <1>;
 699                                 compatible = "fsl,ls1043-qe-siram",
 700                                                 "fsl,t1040-qe-siram";
 701                                 reg = <0x1000 0x800>;
 702                         };
 703
 704                         ucc@2000 {
 705                                 cell-index = <1>;
 706                                 reg = <0x2000 0x200>;
 707                                 interrupts = <32>;
 708                                 interrupt-parent = <&qeic>;
 709                         };
 710
 711                         ucc@2200 {
 712                                 cell-index = <3>;
 713                                 reg = <0x2200 0x200>;
 714                                 interrupts = <34>;
 715                                 interrupt-parent = <&qeic>;
 716                         };
 717
 718                         muram@10000 {
 719                                 #address-cells = <1>;
 720                                 #size-cells = <1>;
 721                                 compatible = "fsl,qe-muram", "fsl,cpm-muram";
 722                                 ranges = <0x0 0x10000 0x6000>;
 723
 724                                 data-only@0 {
 725                                         compatible = "fsl,qe-muram-data",
 726                                         "fsl,cpm-muram-data";
 727                                         reg = <0x0 0x6000>;
 728                                 };
 729                         };
 730                 };
 731
 732                 lpuart0: serial@2950000 {
 733                         compatible = "fsl,ls1021a-lpuart";
 734                         reg = <0x0 0x2950000 0x0 0x1000>;
 735                         interrupts = <0 48 0x4>;
 736                         clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
 737                         clock-names = "ipg";
 738                         status = "disabled";
 739                 };
 740
 741                 lpuart1: serial@2960000 {
 742                         compatible = "fsl,ls1021a-lpuart";
 743                         reg = <0x0 0x2960000 0x0 0x1000>;
 744                         interrupts = <0 49 0x4>;
 745                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 746                                             QORIQ_CLK_PLL_DIV(1)>;
 747                         clock-names = "ipg";
 748                         status = "disabled";
 749                 };
 750
 751                 lpuart2: serial@2970000 {
 752                         compatible = "fsl,ls1021a-lpuart";
 753                         reg = <0x0 0x2970000 0x0 0x1000>;
 754                         interrupts = <0 50 0x4>;
 755                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 756                                             QORIQ_CLK_PLL_DIV(1)>;
 757                         clock-names = "ipg";
 758                         status = "disabled";
 759                 };
 760
 761                 lpuart3: serial@2980000 {
 762                         compatible = "fsl,ls1021a-lpuart";
 763                         reg = <0x0 0x2980000 0x0 0x1000>;
 764                         interrupts = <0 51 0x4>;
 765                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 766                                             QORIQ_CLK_PLL_DIV(1)>;
 767                         clock-names = "ipg";
 768                         status = "disabled";
 769                 };
 770
 771                 lpuart4: serial@2990000 {
 772                         compatible = "fsl,ls1021a-lpuart";
 773                         reg = <0x0 0x2990000 0x0 0x1000>;
 774                         interrupts = <0 52 0x4>;
 775                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 776                                             QORIQ_CLK_PLL_DIV(1)>;
 777                         clock-names = "ipg";
 778                         status = "disabled";
 779                 };
 780
 781                 lpuart5: serial@29a0000 {
 782                         compatible = "fsl,ls1021a-lpuart";
 783                         reg = <0x0 0x29a0000 0x0 0x1000>;
 784                         interrupts = <0 53 0x4>;
 785                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 786                                             QORIQ_CLK_PLL_DIV(1)>;
 787                         clock-names = "ipg";
 788                         status = "disabled";
 789                 };
 790
 791                 wdog0: watchdog@2ad0000 {
 792                         compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
 793                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 794                         interrupts = <0 83 0x4>;
 795                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 796                                             QORIQ_CLK_PLL_DIV(1)>;
 797                         clock-names = "wdog";
 798                         big-endian;
 799                 };
 800
 801                 edma0: dma-controller@2c00000 {
 802                         #dma-cells = <2>;
 803                         compatible = "fsl,vf610-edma";
 804                         reg = <0x0 0x2c00000 0x0 0x10000>,
 805                               <0x0 0x2c10000 0x0 0x10000>,
 806                               <0x0 0x2c20000 0x0 0x10000>;
 807                         interrupts = <0 103 0x4>,
 808                                      <0 103 0x4>;
 809                         interrupt-names = "edma-tx", "edma-err";
 810                         dma-channels = <32>;
 811                         big-endian;
 812                         clock-names = "dmamux0", "dmamux1";
 813                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 814                                             QORIQ_CLK_PLL_DIV(1)>,
 815                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 816                                             QORIQ_CLK_PLL_DIV(1)>;
 817                 };
 818
 819                 aux_bus: aux_bus {
 820                         #address-cells = <2>;
 821                         #size-cells = <2>;
 822                         compatible = "simple-bus";
 823                         ranges;
 824                         dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
 825
 826                         usb0: usb@2f00000 {
 827                                 compatible = "snps,dwc3";
 828                                 reg = <0x0 0x2f00000 0x0 0x10000>;
 829                                 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
 830                                 dr_mode = "host";
 831                                 snps,quirk-frame-length-adjustment = <0x20>;
 832                                 snps,dis_rxdet_inp3_quirk;
 833                                 usb3-lpm-capable;
 834                                 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 835                                 status = "disabled";
 836                         };
 837
 838                         usb1: usb@3000000 {
 839                                 compatible = "snps,dwc3";
 840                                 reg = <0x0 0x3000000 0x0 0x10000>;
 841                                 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
 842                                 dr_mode = "host";
 843                                 snps,quirk-frame-length-adjustment = <0x20>;
 844                                 snps,dis_rxdet_inp3_quirk;
 845                                 usb3-lpm-capable;
 846                                 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 847                                 status = "disabled";
 848                         };
 849
 850                         usb2: usb@3100000 {
 851                                 compatible = "snps,dwc3";
 852                                 reg = <0x0 0x3100000 0x0 0x10000>;
 853                                 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
 854                                 dr_mode = "host";
 855                                 snps,quirk-frame-length-adjustment = <0x20>;
 856                                 snps,dis_rxdet_inp3_quirk;
 857                                 usb3-lpm-capable;
 858                                 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 859                                 status = "disabled";
 860                         };
 861
 862                         sata: sata@3200000 {
 863                                 compatible = "fsl,ls1043a-ahci";
 864                                 reg = <0x0 0x3200000 0x0 0x10000>,
 865                                         <0x0 0x20140520 0x0 0x4>;
 866                                 reg-names = "ahci", "sata-ecc";
 867                                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 868                                 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 869                                                     QORIQ_CLK_PLL_DIV(1)>;
 870                                 dma-coherent;
 871                         };
 872                 };
 873
 874                 msi1: msi-controller1@1571000 {
 875                         compatible = "fsl,ls1043a-msi";
 876                         reg = <0x0 0x1571000 0x0 0x8>;
 877                         msi-controller;
 878                         interrupts = <0 116 0x4>;
 879                 };
 880
 881                 msi2: msi-controller2@1572000 {
 882                         compatible = "fsl,ls1043a-msi";
 883                         reg = <0x0 0x1572000 0x0 0x8>;
 884                         msi-controller;
 885                         interrupts = <0 126 0x4>;
 886                 };
 887
 888                 msi3: msi-controller3@1573000 {
 889                         compatible = "fsl,ls1043a-msi";
 890                         reg = <0x0 0x1573000 0x0 0x8>;
 891                         msi-controller;
 892                         interrupts = <0 160 0x4>;
 893                 };
 894
 895                 pcie1: pcie@3400000 {
 896                         compatible = "fsl,ls1043a-pcie";
 897                         reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
 898                               <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 899                         reg-names = "regs", "config";
 900                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>,
 901                                      <0 118 IRQ_TYPE_LEVEL_HIGH>;
 902                         interrupt-names = "pme", "aer";
 903                         #address-cells = <3>;
 904                         #size-cells = <2>;
 905                         device_type = "pci";
 906                         num-viewport = <6>;
 907                         bus-range = <0x0 0xff>;
 908                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 909                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 910                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 911                         #interrupt-cells = <1>;
 912                         interrupt-map-mask = <0 0 0 7>;
 913                         interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
 914                                         <0000 0 0 2 &gic 0 111 0x4>,
 915                                         <0000 0 0 3 &gic 0 112 0x4>,
 916                                         <0000 0 0 4 &gic 0 113 0x4>;
 917                         fsl,pcie-scfg = <&scfg 0>;
 918                         big-endian;
 919                         status = "disabled";
 920                 };
 921
 922                 pcie2: pcie@3500000 {
 923                         compatible = "fsl,ls1043a-pcie";
 924                         reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
 925                               <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 926                         reg-names = "regs", "config";
 927                         interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <0 128 IRQ_TYPE_LEVEL_HIGH>;
 929                         interrupt-names = "pme", "aer";
 930                         #address-cells = <3>;
 931                         #size-cells = <2>;
 932                         device_type = "pci";
 933                         num-viewport = <6>;
 934                         bus-range = <0x0 0xff>;
 935                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 936                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 937                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 938                         #interrupt-cells = <1>;
 939                         interrupt-map-mask = <0 0 0 7>;
 940                         interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
 941                                         <0000 0 0 2 &gic 0 121 0x4>,
 942                                         <0000 0 0 3 &gic 0 122 0x4>,
 943                                         <0000 0 0 4 &gic 0 123 0x4>;
 944                         fsl,pcie-scfg = <&scfg 1>;
 945                         big-endian;
 946                         status = "disabled";
 947                 };
 948
 949                 pcie3: pcie@3600000 {
 950                         compatible = "fsl,ls1043a-pcie";
 951                         reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
 952                               <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 953                         reg-names = "regs", "config";
 954                         interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>,
 955                                      <0 162 IRQ_TYPE_LEVEL_HIGH>;
 956                         interrupt-names = "pme", "aer";
 957                         #address-cells = <3>;
 958                         #size-cells = <2>;
 959                         device_type = "pci";
 960                         num-viewport = <6>;
 961                         bus-range = <0x0 0xff>;
 962                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 963                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 964                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 965                         #interrupt-cells = <1>;
 966                         interrupt-map-mask = <0 0 0 7>;
 967                         interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
 968                                         <0000 0 0 2 &gic 0 155 0x4>,
 969                                         <0000 0 0 3 &gic 0 156 0x4>,
 970                                         <0000 0 0 4 &gic 0 157 0x4>;
 971                         fsl,pcie-scfg = <&scfg 2>;
 972                         big-endian;
 973                         status = "disabled";
 974                 };
 975
 976                 qdma: dma-controller@8380000 {
 977                         compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
 978                         reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
 979                               <0x0 0x8390000 0x0 0x10000>, /* Status regs */
 980                               <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
 981                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 982                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 983                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 984                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 985                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 986                         interrupt-names = "qdma-error", "qdma-queue0",
 987                                 "qdma-queue1", "qdma-queue2", "qdma-queue3";
 988                         dma-channels = <8>;
 989                         block-number = <1>;
 990                         block-offset = <0x10000>;
 991                         fsl,dma-queues = <2>;
 992                         status-sizes = <64>;
 993                         queue-sizes = <64 64>;
 994                         big-endian;
 995                 };
 996
 997                 rcpm: power-controller@1ee2140 {
 998                         compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
 999                         reg = <0x0 0x1ee2140 0x0 0x4>;
1000                         #fsl,rcpm-wakeup-cells = <1>;
1001                 };
1002
1003                 ftm_alarm0: timer@29d0000 {
1004                         compatible = "fsl,ls1043a-ftm-alarm";
1005                         reg = <0x0 0x29d0000 0x0 0x10000>;
1006                         fsl,rcpm-wakeup = <&rcpm 0x20000>;
1007                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1008                         big-endian;
1009                 };
1010         };
1011
1012         firmware {
1013                 optee {
1014                         compatible = "linaro,optee-tz";
1015                         method = "smc";
1016                 };
1017         };
1018
1019 };
1020
1021 #include "qoriq-qman-portals.dtsi"
1022 #include "qoriq-bman-portals.dtsi"