arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   4  *
   5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   6  *
   7  * Mingkai Hu <Mingkai.hu@freescale.com>
   8  */
   9
  10 #include <dt-bindings/thermal/thermal.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12
  13 / {
  14         compatible = "fsl,ls1043a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 fman0 = &fman0;
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25                 ethernet4 = &enet4;
  26                 ethernet5 = &enet5;
  27                 ethernet6 = &enet6;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 /*
  35                  * We expect the enable-method for cpu's to be "psci", but this
  36                  * is dependent on the SoC FW, which will fill this in.
  37                  *
  38                  * Currently supported enable-method is psci v0.2
  39                  */
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53";
  43                         reg = <0x0>;
  44                         clocks = <&clockgen 1 0>;
  45                         next-level-cache = <&l2>;
  46                         cpu-idle-states = <&CPU_PH20>;
  47                         #cooling-cells = <2>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53";
  53                         reg = <0x1>;
  54                         clocks = <&clockgen 1 0>;
  55                         next-level-cache = <&l2>;
  56                         cpu-idle-states = <&CPU_PH20>;
  57                         #cooling-cells = <2>;
  58                 };
  59
  60                 cpu2: cpu@2 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         reg = <0x2>;
  64                         clocks = <&clockgen 1 0>;
  65                         next-level-cache = <&l2>;
  66                         cpu-idle-states = <&CPU_PH20>;
  67                         #cooling-cells = <2>;
  68                 };
  69
  70                 cpu3: cpu@3 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53";
  73                         reg = <0x3>;
  74                         clocks = <&clockgen 1 0>;
  75                         next-level-cache = <&l2>;
  76                         cpu-idle-states = <&CPU_PH20>;
  77                         #cooling-cells = <2>;
  78                 };
  79
  80                 l2: l2-cache {
  81                         compatible = "cache";
  82                 };
  83         };
  84
  85         idle-states {
  86                 /*
  87                  * PSCI node is not added default, U-boot will add missing
  88                  * parts if it determines to use PSCI.
  89                  */
  90                 entry-method = "psci";
  91
  92                 CPU_PH20: cpu-ph20 {
  93                         compatible = "arm,idle-state";
  94                         idle-state-name = "PH20";
  95                         arm,psci-suspend-param = <0x0>;
  96                         entry-latency-us = <1000>;
  97                         exit-latency-us = <1000>;
  98                         min-residency-us = <3000>;
  99                 };
 100         };
 101
 102         memory@80000000 {
 103                 device_type = "memory";
 104                 reg = <0x0 0x80000000 0 0x80000000>;
 105                       /* DRAM space 1, size: 2GiB DRAM */
 106         };
 107
 108         reserved-memory {
 109                 #address-cells = <2>;
 110                 #size-cells = <2>;
 111                 ranges;
 112
 113                 bman_fbpr: bman-fbpr {
 114                         compatible = "shared-dma-pool";
 115                         size = <0 0x1000000>;
 116                         alignment = <0 0x1000000>;
 117                         no-map;
 118                 };
 119
 120                 qman_fqd: qman-fqd {
 121                         compatible = "shared-dma-pool";
 122                         size = <0 0x400000>;
 123                         alignment = <0 0x400000>;
 124                         no-map;
 125                 };
 126
 127                 qman_pfdr: qman-pfdr {
 128                         compatible = "shared-dma-pool";
 129                         size = <0 0x2000000>;
 130                         alignment = <0 0x2000000>;
 131                         no-map;
 132                 };
 133         };
 134
 135         sysclk: sysclk {
 136                 compatible = "fixed-clock";
 137                 #clock-cells = <0>;
 138                 clock-frequency = <100000000>;
 139                 clock-output-names = "sysclk";
 140         };
 141
 142         reboot {
 143                 compatible ="syscon-reboot";
 144                 regmap = <&dcfg>;
 145                 offset = <0xb0>;
 146                 mask = <0x02>;
 147         };
 148
 149         thermal-zones {
 150                 cpu_thermal: cpu-thermal {
 151                         polling-delay-passive = <1000>;
 152                         polling-delay = <5000>;
 153
 154                         thermal-sensors = <&tmu 3>;
 155
 156                         trips {
 157                                 cpu_alert: cpu-alert {
 158                                         temperature = <85000>;
 159                                         hysteresis = <2000>;
 160                                         type = "passive";
 161                                 };
 162                                 cpu_crit: cpu-crit {
 163                                         temperature = <95000>;
 164                                         hysteresis = <2000>;
 165                                         type = "critical";
 166                                 };
 167                         };
 168
 169                         cooling-maps {
 170                                 map0 {
 171                                         trip = <&cpu_alert>;
 172                                         cooling-device =
 173                                                 <&cpu0 THERMAL_NO_LIMIT
 174                                                 THERMAL_NO_LIMIT>;
 175                                 };
 176                         };
 177                 };
 178         };
 179
 180         timer {
 181                 compatible = "arm,armv8-timer";
 182                 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
 183                              <1 14 0xf08>, /* Physical Non-Secure PPI */
 184                              <1 11 0xf08>, /* Virtual PPI */
 185                              <1 10 0xf08>; /* Hypervisor PPI */
 186                 fsl,erratum-a008585;
 187         };
 188
 189         pmu {
 190                 compatible = "arm,armv8-pmuv3";
 191                 interrupts = <0 106 0x4>,
 192                              <0 107 0x4>,
 193                              <0 95 0x4>,
 194                              <0 97 0x4>;
 195                 interrupt-affinity = <&cpu0>,
 196                                      <&cpu1>,
 197                                      <&cpu2>,
 198                                      <&cpu3>;
 199         };
 200
 201         gic: interrupt-controller@1400000 {
 202                 compatible = "arm,gic-400";
 203                 #interrupt-cells = <3>;
 204                 interrupt-controller;
 205                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
 206                       <0x0 0x1402000 0 0x2000>, /* GICC */
 207                       <0x0 0x1404000 0 0x2000>, /* GICH */
 208                       <0x0 0x1406000 0 0x2000>; /* GICV */
 209                 interrupts = <1 9 0xf08>;
 210         };
 211
 212         soc: soc {
 213                 compatible = "simple-bus";
 214                 #address-cells = <2>;
 215                 #size-cells = <2>;
 216                 ranges;
 217
 218                 clockgen: clocking@1ee1000 {
 219                         compatible = "fsl,ls1043a-clockgen";
 220                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 221                         #clock-cells = <2>;
 222                         clocks = <&sysclk>;
 223                 };
 224
 225                 scfg: scfg@1570000 {
 226                         compatible = "fsl,ls1043a-scfg", "syscon";
 227                         reg = <0x0 0x1570000 0x0 0x10000>;
 228                         big-endian;
 229                 };
 230
 231                 crypto: crypto@1700000 {
 232                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 233                                      "fsl,sec-v4.0";
 234                         fsl,sec-era = <3>;
 235                         #address-cells = <1>;
 236                         #size-cells = <1>;
 237                         ranges = <0x0 0x00 0x1700000 0x100000>;
 238                         reg = <0x00 0x1700000 0x0 0x100000>;
 239                         interrupts = <0 75 0x4>;
 240                         dma-coherent;
 241
 242                         sec_jr0: jr@10000 {
 243                                 compatible = "fsl,sec-v5.4-job-ring",
 244                                              "fsl,sec-v5.0-job-ring",
 245                                              "fsl,sec-v4.0-job-ring";
 246                                 reg        = <0x10000 0x10000>;
 247                                 interrupts = <0 71 0x4>;
 248                         };
 249
 250                         sec_jr1: jr@20000 {
 251                                 compatible = "fsl,sec-v5.4-job-ring",
 252                                              "fsl,sec-v5.0-job-ring",
 253                                              "fsl,sec-v4.0-job-ring";
 254                                 reg        = <0x20000 0x10000>;
 255                                 interrupts = <0 72 0x4>;
 256                         };
 257
 258                         sec_jr2: jr@30000 {
 259                                 compatible = "fsl,sec-v5.4-job-ring",
 260                                              "fsl,sec-v5.0-job-ring",
 261                                              "fsl,sec-v4.0-job-ring";
 262                                 reg        = <0x30000 0x10000>;
 263                                 interrupts = <0 73 0x4>;
 264                         };
 265
 266                         sec_jr3: jr@40000 {
 267                                 compatible = "fsl,sec-v5.4-job-ring",
 268                                              "fsl,sec-v5.0-job-ring",
 269                                              "fsl,sec-v4.0-job-ring";
 270                                 reg        = <0x40000 0x10000>;
 271                                 interrupts = <0 74 0x4>;
 272                         };
 273                 };
 274
 275                 dcfg: dcfg@1ee0000 {
 276                         compatible = "fsl,ls1043a-dcfg", "syscon";
 277                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 278                         big-endian;
 279                 };
 280
 281                 ifc: ifc@1530000 {
 282                         compatible = "fsl,ifc", "simple-bus";
 283                         reg = <0x0 0x1530000 0x0 0x10000>;
 284                         big-endian;
 285                         interrupts = <0 43 0x4>;
 286                 };
 287
 288                 qspi: spi@1550000 {
 289                         compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
 290                         #address-cells = <1>;
 291                         #size-cells = <0>;
 292                         reg = <0x0 0x1550000 0x0 0x10000>,
 293                                 <0x0 0x40000000 0x0 0x4000000>;
 294                         reg-names = "QuadSPI", "QuadSPI-memory";
 295                         interrupts = <0 99 0x4>;
 296                         clock-names = "qspi_en", "qspi";
 297                         clocks = <&clockgen 4 0>, <&clockgen 4 0>;
 298                         big-endian;
 299                         status = "disabled";
 300                 };
 301
 302                 esdhc: esdhc@1560000 {
 303                         compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
 304                         reg = <0x0 0x1560000 0x0 0x10000>;
 305                         interrupts = <0 62 0x4>;
 306                         clock-frequency = <0>;
 307                         voltage-ranges = <1800 1800 3300 3300>;
 308                         sdhci,auto-cmd12;
 309                         big-endian;
 310                         bus-width = <4>;
 311                 };
 312
 313                 ddr: memory-controller@1080000 {
 314                         compatible = "fsl,qoriq-memory-controller";
 315                         reg = <0x0 0x1080000 0x0 0x1000>;
 316                         interrupts = <0 144 0x4>;
 317                         big-endian;
 318                 };
 319
 320                 tmu: tmu@1f00000 {
 321                         compatible = "fsl,qoriq-tmu";
 322                         reg = <0x0 0x1f00000 0x0 0x10000>;
 323                         interrupts = <0 33 0x4>;
 324                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 325                         fsl,tmu-calibration = <0x00000000 0x00000026
 326                                                0x00000001 0x0000002d
 327                                                0x00000002 0x00000032
 328                                                0x00000003 0x00000039
 329                                                0x00000004 0x0000003f
 330                                                0x00000005 0x00000046
 331                                                0x00000006 0x0000004d
 332                                                0x00000007 0x00000054
 333                                                0x00000008 0x0000005a
 334                                                0x00000009 0x00000061
 335                                                0x0000000a 0x0000006a
 336                                                0x0000000b 0x00000071
 337
 338                                                0x00010000 0x00000025
 339                                                0x00010001 0x0000002c
 340                                                0x00010002 0x00000035
 341                                                0x00010003 0x0000003d
 342                                                0x00010004 0x00000045
 343                                                0x00010005 0x0000004e
 344                                                0x00010006 0x00000057
 345                                                0x00010007 0x00000061
 346                                                0x00010008 0x0000006b
 347                                                0x00010009 0x00000076
 348
 349                                                0x00020000 0x00000029
 350                                                0x00020001 0x00000033
 351                                                0x00020002 0x0000003d
 352                                                0x00020003 0x00000049
 353                                                0x00020004 0x00000056
 354                                                0x00020005 0x00000061
 355                                                0x00020006 0x0000006d
 356
 357                                                0x00030000 0x00000021
 358                                                0x00030001 0x0000002a
 359                                                0x00030002 0x0000003c
 360                                                0x00030003 0x0000004e>;
 361                         #thermal-sensor-cells = <1>;
 362                 };
 363
 364                 qman: qman@1880000 {
 365                         compatible = "fsl,qman";
 366                         reg = <0x0 0x1880000 0x0 0x10000>;
 367                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 368                         memory-region = <&qman_fqd &qman_pfdr>;
 369                 };
 370
 371                 bman: bman@1890000 {
 372                         compatible = "fsl,bman";
 373                         reg = <0x0 0x1890000 0x0 0x10000>;
 374                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 375                         memory-region = <&bman_fbpr>;
 376                 };
 377
 378                 bportals: bman-portals@508000000 {
 379                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 380                 };
 381
 382                 qportals: qman-portals@500000000 {
 383                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 384                 };
 385
 386                 dspi0: spi@2100000 {
 387                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         reg = <0x0 0x2100000 0x0 0x10000>;
 391                         interrupts = <0 64 0x4>;
 392                         clock-names = "dspi";
 393                         clocks = <&clockgen 4 0>;
 394                         spi-num-chipselects = <5>;
 395                         big-endian;
 396                         status = "disabled";
 397                 };
 398
 399                 dspi1: spi@2110000 {
 400                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         reg = <0x0 0x2110000 0x0 0x10000>;
 404                         interrupts = <0 65 0x4>;
 405                         clock-names = "dspi";
 406                         clocks = <&clockgen 4 0>;
 407                         spi-num-chipselects = <5>;
 408                         big-endian;
 409                         status = "disabled";
 410                 };
 411
 412                 i2c0: i2c@2180000 {
 413                         compatible = "fsl,vf610-i2c";
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         reg = <0x0 0x2180000 0x0 0x10000>;
 417                         interrupts = <0 56 0x4>;
 418                         clock-names = "i2c";
 419                         clocks = <&clockgen 4 0>;
 420                         dmas = <&edma0 1 39>,
 421                                <&edma0 1 38>;
 422                         dma-names = "tx", "rx";
 423                         status = "disabled";
 424                 };
 425
 426                 i2c1: i2c@2190000 {
 427                         compatible = "fsl,vf610-i2c";
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         reg = <0x0 0x2190000 0x0 0x10000>;
 431                         interrupts = <0 57 0x4>;
 432                         clock-names = "i2c";
 433                         clocks = <&clockgen 4 0>;
 434                         status = "disabled";
 435                 };
 436
 437                 i2c2: i2c@21a0000 {
 438                         compatible = "fsl,vf610-i2c";
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         reg = <0x0 0x21a0000 0x0 0x10000>;
 442                         interrupts = <0 58 0x4>;
 443                         clock-names = "i2c";
 444                         clocks = <&clockgen 4 0>;
 445                         status = "disabled";
 446                 };
 447
 448                 i2c3: i2c@21b0000 {
 449                         compatible = "fsl,vf610-i2c";
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         reg = <0x0 0x21b0000 0x0 0x10000>;
 453                         interrupts = <0 59 0x4>;
 454                         clock-names = "i2c";
 455                         clocks = <&clockgen 4 0>;
 456                         status = "disabled";
 457                 };
 458
 459                 duart0: serial@21c0500 {
 460                         compatible = "fsl,ns16550", "ns16550a";
 461                         reg = <0x00 0x21c0500 0x0 0x100>;
 462                         interrupts = <0 54 0x4>;
 463                         clocks = <&clockgen 4 0>;
 464                 };
 465
 466                 duart1: serial@21c0600 {
 467                         compatible = "fsl,ns16550", "ns16550a";
 468                         reg = <0x00 0x21c0600 0x0 0x100>;
 469                         interrupts = <0 54 0x4>;
 470                         clocks = <&clockgen 4 0>;
 471                 };
 472
 473                 duart2: serial@21d0500 {
 474                         compatible = "fsl,ns16550", "ns16550a";
 475                         reg = <0x0 0x21d0500 0x0 0x100>;
 476                         interrupts = <0 55 0x4>;
 477                         clocks = <&clockgen 4 0>;
 478                 };
 479
 480                 duart3: serial@21d0600 {
 481                         compatible = "fsl,ns16550", "ns16550a";
 482                         reg = <0x0 0x21d0600 0x0 0x100>;
 483                         interrupts = <0 55 0x4>;
 484                         clocks = <&clockgen 4 0>;
 485                 };
 486
 487                 gpio1: gpio@2300000 {
 488                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 489                         reg = <0x0 0x2300000 0x0 0x10000>;
 490                         interrupts = <0 66 0x4>;
 491                         gpio-controller;
 492                         #gpio-cells = <2>;
 493                         interrupt-controller;
 494                         #interrupt-cells = <2>;
 495                 };
 496
 497                 gpio2: gpio@2310000 {
 498                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 499                         reg = <0x0 0x2310000 0x0 0x10000>;
 500                         interrupts = <0 67 0x4>;
 501                         gpio-controller;
 502                         #gpio-cells = <2>;
 503                         interrupt-controller;
 504                         #interrupt-cells = <2>;
 505                 };
 506
 507                 gpio3: gpio@2320000 {
 508                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 509                         reg = <0x0 0x2320000 0x0 0x10000>;
 510                         interrupts = <0 68 0x4>;
 511                         gpio-controller;
 512                         #gpio-cells = <2>;
 513                         interrupt-controller;
 514                         #interrupt-cells = <2>;
 515                 };
 516
 517                 gpio4: gpio@2330000 {
 518                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 519                         reg = <0x0 0x2330000 0x0 0x10000>;
 520                         interrupts = <0 134 0x4>;
 521                         gpio-controller;
 522                         #gpio-cells = <2>;
 523                         interrupt-controller;
 524                         #interrupt-cells = <2>;
 525                 };
 526
 527                 lpuart0: serial@2950000 {
 528                         compatible = "fsl,ls1021a-lpuart";
 529                         reg = <0x0 0x2950000 0x0 0x1000>;
 530                         interrupts = <0 48 0x4>;
 531                         clocks = <&clockgen 0 0>;
 532                         clock-names = "ipg";
 533                         status = "disabled";
 534                 };
 535
 536                 lpuart1: serial@2960000 {
 537                         compatible = "fsl,ls1021a-lpuart";
 538                         reg = <0x0 0x2960000 0x0 0x1000>;
 539                         interrupts = <0 49 0x4>;
 540                         clocks = <&clockgen 4 0>;
 541                         clock-names = "ipg";
 542                         status = "disabled";
 543                 };
 544
 545                 lpuart2: serial@2970000 {
 546                         compatible = "fsl,ls1021a-lpuart";
 547                         reg = <0x0 0x2970000 0x0 0x1000>;
 548                         interrupts = <0 50 0x4>;
 549                         clocks = <&clockgen 4 0>;
 550                         clock-names = "ipg";
 551                         status = "disabled";
 552                 };
 553
 554                 lpuart3: serial@2980000 {
 555                         compatible = "fsl,ls1021a-lpuart";
 556                         reg = <0x0 0x2980000 0x0 0x1000>;
 557                         interrupts = <0 51 0x4>;
 558                         clocks = <&clockgen 4 0>;
 559                         clock-names = "ipg";
 560                         status = "disabled";
 561                 };
 562
 563                 lpuart4: serial@2990000 {
 564                         compatible = "fsl,ls1021a-lpuart";
 565                         reg = <0x0 0x2990000 0x0 0x1000>;
 566                         interrupts = <0 52 0x4>;
 567                         clocks = <&clockgen 4 0>;
 568                         clock-names = "ipg";
 569                         status = "disabled";
 570                 };
 571
 572                 lpuart5: serial@29a0000 {
 573                         compatible = "fsl,ls1021a-lpuart";
 574                         reg = <0x0 0x29a0000 0x0 0x1000>;
 575                         interrupts = <0 53 0x4>;
 576                         clocks = <&clockgen 4 0>;
 577                         clock-names = "ipg";
 578                         status = "disabled";
 579                 };
 580
 581                 wdog0: wdog@2ad0000 {
 582                         compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
 583                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 584                         interrupts = <0 83 0x4>;
 585                         clocks = <&clockgen 4 0>;
 586                         clock-names = "wdog";
 587                         big-endian;
 588                 };
 589
 590                 edma0: edma@2c00000 {
 591                         #dma-cells = <2>;
 592                         compatible = "fsl,vf610-edma";
 593                         reg = <0x0 0x2c00000 0x0 0x10000>,
 594                               <0x0 0x2c10000 0x0 0x10000>,
 595                               <0x0 0x2c20000 0x0 0x10000>;
 596                         interrupts = <0 103 0x4>,
 597                                      <0 103 0x4>;
 598                         interrupt-names = "edma-tx", "edma-err";
 599                         dma-channels = <32>;
 600                         big-endian;
 601                         clock-names = "dmamux0", "dmamux1";
 602                         clocks = <&clockgen 4 0>,
 603                                  <&clockgen 4 0>;
 604                 };
 605
 606                 usb0: usb3@2f00000 {
 607                         compatible = "snps,dwc3";
 608                         reg = <0x0 0x2f00000 0x0 0x10000>;
 609                         interrupts = <0 60 0x4>;
 610                         dr_mode = "host";
 611                         snps,quirk-frame-length-adjustment = <0x20>;
 612                         snps,dis_rxdet_inp3_quirk;
 613                 };
 614
 615                 usb1: usb3@3000000 {
 616                         compatible = "snps,dwc3";
 617                         reg = <0x0 0x3000000 0x0 0x10000>;
 618                         interrupts = <0 61 0x4>;
 619                         dr_mode = "host";
 620                         snps,quirk-frame-length-adjustment = <0x20>;
 621                         snps,dis_rxdet_inp3_quirk;
 622                 };
 623
 624                 usb2: usb3@3100000 {
 625                         compatible = "snps,dwc3";
 626                         reg = <0x0 0x3100000 0x0 0x10000>;
 627                         interrupts = <0 63 0x4>;
 628                         dr_mode = "host";
 629                         snps,quirk-frame-length-adjustment = <0x20>;
 630                         snps,dis_rxdet_inp3_quirk;
 631                 };
 632
 633                 sata: sata@3200000 {
 634                         compatible = "fsl,ls1043a-ahci";
 635                         reg = <0x0 0x3200000 0x0 0x10000>,
 636                                 <0x0 0x20140520 0x0 0x4>;
 637                         reg-names = "ahci", "sata-ecc";
 638                         interrupts = <0 69 0x4>;
 639                         clocks = <&clockgen 4 0>;
 640                         dma-coherent;
 641                 };
 642
 643                 msi1: msi-controller1@1571000 {
 644                         compatible = "fsl,ls1043a-msi";
 645                         reg = <0x0 0x1571000 0x0 0x8>;
 646                         msi-controller;
 647                         interrupts = <0 116 0x4>;
 648                 };
 649
 650                 msi2: msi-controller2@1572000 {
 651                         compatible = "fsl,ls1043a-msi";
 652                         reg = <0x0 0x1572000 0x0 0x8>;
 653                         msi-controller;
 654                         interrupts = <0 126 0x4>;
 655                 };
 656
 657                 msi3: msi-controller3@1573000 {
 658                         compatible = "fsl,ls1043a-msi";
 659                         reg = <0x0 0x1573000 0x0 0x8>;
 660                         msi-controller;
 661                         interrupts = <0 160 0x4>;
 662                 };
 663
 664                 pcie@3400000 {
 665                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 666                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 667                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 668                         reg-names = "regs", "config";
 669                         interrupts = <0 118 0x4>, /* controller interrupt */
 670                                      <0 117 0x4>; /* PME interrupt */
 671                         interrupt-names = "intr", "pme";
 672                         #address-cells = <3>;
 673                         #size-cells = <2>;
 674                         device_type = "pci";
 675                         dma-coherent;
 676                         num-lanes = <4>;
 677                         bus-range = <0x0 0xff>;
 678                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 679                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 680                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 681                         #interrupt-cells = <1>;
 682                         interrupt-map-mask = <0 0 0 7>;
 683                         interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
 684                                         <0000 0 0 2 &gic 0 111 0x4>,
 685                                         <0000 0 0 3 &gic 0 112 0x4>,
 686                                         <0000 0 0 4 &gic 0 113 0x4>;
 687                 };
 688
 689                 pcie@3500000 {
 690                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 691                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 692                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 693                         reg-names = "regs", "config";
 694                         interrupts = <0 128 0x4>,
 695                                      <0 127 0x4>;
 696                         interrupt-names = "intr", "pme";
 697                         #address-cells = <3>;
 698                         #size-cells = <2>;
 699                         device_type = "pci";
 700                         dma-coherent;
 701                         num-lanes = <2>;
 702                         bus-range = <0x0 0xff>;
 703                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 704                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 705                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 706                         #interrupt-cells = <1>;
 707                         interrupt-map-mask = <0 0 0 7>;
 708                         interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
 709                                         <0000 0 0 2 &gic 0 121 0x4>,
 710                                         <0000 0 0 3 &gic 0 122 0x4>,
 711                                         <0000 0 0 4 &gic 0 123 0x4>;
 712                 };
 713
 714                 pcie@3600000 {
 715                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 716                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 717                                0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 718                         reg-names = "regs", "config";
 719                         interrupts = <0 162 0x4>,
 720                                      <0 161 0x4>;
 721                         interrupt-names = "intr", "pme";
 722                         #address-cells = <3>;
 723                         #size-cells = <2>;
 724                         device_type = "pci";
 725                         dma-coherent;
 726                         num-lanes = <2>;
 727                         bus-range = <0x0 0xff>;
 728                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 729                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 730                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 731                         #interrupt-cells = <1>;
 732                         interrupt-map-mask = <0 0 0 7>;
 733                         interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
 734                                         <0000 0 0 2 &gic 0 155 0x4>,
 735                                         <0000 0 0 3 &gic 0 156 0x4>,
 736                                         <0000 0 0 4 &gic 0 157 0x4>;
 737                 };
 738         };
 739
 740         firmware {
 741                 optee {
 742                         compatible = "linaro,optee-tz";
 743                         method = "smc";
 744                 };
 745         };
 746
 747 };
 748
 749 #include "qoriq-qman-portals.dtsi"
 750 #include "qoriq-bman-portals.dtsi"