1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
7 * Mingkai Hu <Mingkai.hu@freescale.com>
11 #include "fsl-ls1043a.dtsi"
14 model = "LS1043A RDB Board";
25 stdout-path = "serial0:115200n8";
32 compatible = "ti,ina220";
34 shunt-resistor = <1000>;
37 compatible = "adi,adt7461";
41 compatible = "atmel,24c512";
45 compatible = "atmel,24c512";
49 compatible = "pericom,pt7c4338";
58 /* NOR, NAND Flashes and FPGA on board */
59 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
60 0x1 0x0 0x0 0x7e800000 0x00010000
61 0x2 0x0 0x0 0x7fb00000 0x00000100>;
64 compatible = "cfi-flash";
67 reg = <0x0 0x0 0x8000000>;
73 compatible = "fsl,ifc-nand";
76 reg = <0x1 0x0 0x10000>;
79 cpld: board-control@2,0 {
80 compatible = "fsl,ls1043ardb-cpld";
81 reg = <0x2 0x0 0x0000100>;
92 compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
94 spi-max-frequency = <1000000>; /* input clock */
106 #include "fsl-ls1043-post.dtsi"
110 phy-handle = <&qsgmii_phy1>;
111 phy-connection-type = "qsgmii";
115 phy-handle = <&qsgmii_phy2>;
116 phy-connection-type = "qsgmii";
120 phy-handle = <&rgmii_phy1>;
121 phy-connection-type = "rgmii-id";
125 phy-handle = <&rgmii_phy2>;
126 phy-connection-type = "rgmii-id";
130 phy-handle = <&qsgmii_phy3>;
131 phy-connection-type = "qsgmii";
135 phy-handle = <&qsgmii_phy4>;
136 phy-connection-type = "qsgmii";
139 ethernet@f0000 { /* 10GEC1 */
140 phy-handle = <&aqr105_phy>;
141 phy-connection-type = "xgmii";
145 rgmii_phy1: ethernet-phy@1 {
149 rgmii_phy2: ethernet-phy@2 {
153 qsgmii_phy1: ethernet-phy@4 {
157 qsgmii_phy2: ethernet-phy@5 {
161 qsgmii_phy3: ethernet-phy@6 {
165 qsgmii_phy4: ethernet-phy@7 {
171 aqr105_phy: ethernet-phy@1 {
172 compatible = "ethernet-phy-ieee802.3-c45";
173 interrupts = <0 132 4>;