1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
8 * Mingkai Hu <Mingkai.hu@freescale.com>
12 #include "fsl-ls1043a.dtsi"
15 model = "LS1043A RDB Board";
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
34 compatible = "ti,ina220";
36 shunt-resistor = <1000>;
40 compatible = "adi,adt7461";
45 compatible = "nxp,pcf85263";
50 compatible = "atmel,24c512";
55 compatible = "atmel,24c512";
60 compatible = "pericom,pt7c4338";
69 /* NOR, NAND Flashes and FPGA on board */
70 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
71 0x1 0x0 0x0 0x7e800000 0x00010000
72 0x2 0x0 0x0 0x7fb00000 0x00000100>;
75 compatible = "cfi-flash";
78 reg = <0x0 0x0 0x8000000>;
85 compatible = "fsl,ifc-nand";
88 reg = <0x1 0x0 0x10000>;
91 cpld: board-control@2,0 {
92 compatible = "fsl,ls1043ardb-cpld";
93 reg = <0x2 0x0 0x0000100>;
102 #address-cells = <1>;
104 compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
106 spi-max-frequency = <1000000>; /* input clock */
107 fsl,spi-cs-sck-delay = <100>;
108 fsl,spi-sck-cs-delay = <100>;
112 compatible = "maxim,ds26522";
114 spi-max-frequency = <2000000>;
115 fsl,spi-cs-sck-delay = <100>;
116 fsl,spi-sck-cs-delay = <50>;
120 compatible = "maxim,ds26522";
122 spi-max-frequency = <2000000>;
123 fsl,spi-cs-sck-delay = <100>;
124 fsl,spi-sck-cs-delay = <50>;
136 #include "fsl-ls1043-post.dtsi"
140 phy-handle = <&qsgmii_phy1>;
141 phy-connection-type = "qsgmii";
145 phy-handle = <&qsgmii_phy2>;
146 phy-connection-type = "qsgmii";
150 phy-handle = <&rgmii_phy1>;
151 phy-connection-type = "rgmii-id";
155 phy-handle = <&rgmii_phy2>;
156 phy-connection-type = "rgmii-id";
160 phy-handle = <&qsgmii_phy3>;
161 phy-connection-type = "qsgmii";
165 phy-handle = <&qsgmii_phy4>;
166 phy-connection-type = "qsgmii";
169 ethernet@f0000 { /* 10GEC1 */
170 phy-handle = <&aqr105_phy>;
171 phy-connection-type = "xgmii";
175 rgmii_phy1: ethernet-phy@1 {
179 rgmii_phy2: ethernet-phy@2 {
183 qsgmii_phy1: ethernet-phy@4 {
187 qsgmii_phy2: ethernet-phy@5 {
191 qsgmii_phy3: ethernet-phy@6 {
195 qsgmii_phy4: ethernet-phy@7 {
201 aqr105_phy: ethernet-phy@1 {
202 compatible = "ethernet-phy-ieee802.3-c45";
203 interrupts = <0 132 4>;
211 compatible = "fsl,ucc-hdlc";
212 rx-clock-name = "clk8";
213 tx-clock-name = "clk9";
214 fsl,rx-sync-clock = "rsync_pin";
215 fsl,tx-sync-clock = "tsync_pin";
216 fsl,tx-timeslot-mask = <0xfffffffe>;
217 fsl,rx-timeslot-mask = <0xfffffffe>;
218 fsl,tdm-framer-type = "e1";
220 fsl,siram-entry-id = <0>;