arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   4  *
   5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  *
   8  * Mingkai Hu <Mingkai.hu@freescale.com>
   9  */
  10
  11 /dts-v1/;
  12 #include "fsl-ls1043a.dtsi"
  13
  14 / {
  15         model = "LS1043A RDB Board";
  16         compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
  17
  18         aliases {
  19                 serial0 = &duart0;
  20                 serial1 = &duart1;
  21                 serial2 = &duart2;
  22                 serial3 = &duart3;
  23         };
  24
  25         chosen {
  26                 stdout-path = "serial0:115200n8";
  27         };
  28 };
  29
  30 &i2c0 {
  31         status = "okay";
  32
  33         ina220@40 {
  34                 compatible = "ti,ina220";
  35                 reg = <0x40>;
  36                 shunt-resistor = <1000>;
  37         };
  38
  39         adt7461a@4c {
  40                 compatible = "adi,adt7461";
  41                 reg = <0x4c>;
  42         };
  43
  44         rtc@51 {
  45                 compatible = "nxp,pcf85263";
  46                 reg = <0x51>;
  47         };
  48
  49         eeprom@52 {
  50                 compatible = "atmel,24c512";
  51                 reg = <0x52>;
  52         };
  53
  54         eeprom@53 {
  55                 compatible = "atmel,24c512";
  56                 reg = <0x53>;
  57         };
  58
  59         rtc@68 {
  60                 compatible = "pericom,pt7c4338";
  61                 reg = <0x68>;
  62         };
  63 };
  64
  65 &ifc {
  66         status = "okay";
  67         #address-cells = <2>;
  68         #size-cells = <1>;
  69         /* NOR, NAND Flashes and FPGA on board */
  70         ranges = <0x0 0x0 0x0 0x60000000 0x08000000
  71                   0x1 0x0 0x0 0x7e800000 0x00010000
  72                   0x2 0x0 0x0 0x7fb00000 0x00000100>;
  73
  74                 nor@0,0 {
  75                         compatible = "cfi-flash";
  76                         #address-cells = <1>;
  77                         #size-cells = <1>;
  78                         reg = <0x0 0x0 0x8000000>;
  79                         big-endian;
  80                         bank-width = <2>;
  81                         device-width = <1>;
  82                 };
  83
  84                 nand@1,0 {
  85                         compatible = "fsl,ifc-nand";
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         reg = <0x1 0x0 0x10000>;
  89                 };
  90
  91                 cpld: board-control@2,0 {
  92                         compatible = "fsl,ls1043ardb-cpld";
  93                         reg = <0x2 0x0 0x0000100>;
  94                 };
  95 };
  96
  97 &dspi0 {
  98         bus-num = <0>;
  99         status = "okay";
 100
 101         flash@0 {
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
 105                 reg = <0>;
 106                 spi-max-frequency = <1000000>; /* input clock */
 107                 fsl,spi-cs-sck-delay = <100>;
 108                 fsl,spi-sck-cs-delay = <100>;
 109         };
 110
 111         slic@2 {
 112                 compatible = "maxim,ds26522";
 113                 reg = <2>;
 114                 spi-max-frequency = <2000000>;
 115                 fsl,spi-cs-sck-delay = <100>;
 116                 fsl,spi-sck-cs-delay = <50>;
 117         };
 118
 119         slic@3 {
 120                 compatible = "maxim,ds26522";
 121                 reg = <3>;
 122                 spi-max-frequency = <2000000>;
 123                 fsl,spi-cs-sck-delay = <100>;
 124                 fsl,spi-sck-cs-delay = <50>;
 125         };
 126 };
 127
 128 &duart0 {
 129         status = "okay";
 130 };
 131
 132 &duart1 {
 133         status = "okay";
 134 };
 135
 136 #include "fsl-ls1043-post.dtsi"
 137
 138 &fman0 {
 139         ethernet@e0000 {
 140                 phy-handle = <&qsgmii_phy1>;
 141                 phy-connection-type = "qsgmii";
 142         };
 143
 144         ethernet@e2000 {
 145                 phy-handle = <&qsgmii_phy2>;
 146                 phy-connection-type = "qsgmii";
 147         };
 148
 149         ethernet@e4000 {
 150                 phy-handle = <&rgmii_phy1>;
 151                 phy-connection-type = "rgmii-id";
 152         };
 153
 154         ethernet@e6000 {
 155                 phy-handle = <&rgmii_phy2>;
 156                 phy-connection-type = "rgmii-id";
 157         };
 158
 159         ethernet@e8000 {
 160                 phy-handle = <&qsgmii_phy3>;
 161                 phy-connection-type = "qsgmii";
 162         };
 163
 164         ethernet@ea000 {
 165                 phy-handle = <&qsgmii_phy4>;
 166                 phy-connection-type = "qsgmii";
 167         };
 168
 169         ethernet@f0000 { /* 10GEC1 */
 170                 phy-handle = <&aqr105_phy>;
 171                 phy-connection-type = "xgmii";
 172         };
 173
 174         mdio@fc000 {
 175                 rgmii_phy1: ethernet-phy@1 {
 176                         reg = <0x1>;
 177                 };
 178
 179                 rgmii_phy2: ethernet-phy@2 {
 180                         reg = <0x2>;
 181                 };
 182
 183                 qsgmii_phy1: ethernet-phy@4 {
 184                         reg = <0x4>;
 185                 };
 186
 187                 qsgmii_phy2: ethernet-phy@5 {
 188                         reg = <0x5>;
 189                 };
 190
 191                 qsgmii_phy3: ethernet-phy@6 {
 192                         reg = <0x6>;
 193                 };
 194
 195                 qsgmii_phy4: ethernet-phy@7 {
 196                         reg = <0x7>;
 197                 };
 198         };
 199
 200         mdio@fd000 {
 201                 aqr105_phy: ethernet-phy@1 {
 202                         compatible = "ethernet-phy-ieee802.3-c45";
 203                         interrupts = <0 132 4>;
 204                         reg = <0x1>;
 205                 };
 206         };
 207 };
 208
 209 &uqe {
 210         ucc_hdlc: ucc@2000 {
 211                 compatible = "fsl,ucc-hdlc";
 212                 rx-clock-name = "clk8";
 213                 tx-clock-name = "clk9";
 214                 fsl,rx-sync-clock = "rsync_pin";
 215                 fsl,tx-sync-clock = "tsync_pin";
 216                 fsl,tx-timeslot-mask = <0xfffffffe>;
 217                 fsl,rx-timeslot-mask = <0xfffffffe>;
 218                 fsl,tdm-framer-type = "e1";
 219                 fsl,tdm-id = <0>;
 220                 fsl,siram-entry-id = <0>;
 221                 fsl,tdm-interface;
 222         };
 223 };
 224
 225 &usb0 {
 226         status = "okay";
 227 };
 228
 229 &usb1 {
 230         status = "okay";
 231 };