arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1012A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2019-2020 NXP
   7  *
   8  */
   9
  10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "fsl,ls1012a";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 crypto = &crypto;
  22                 rtc1 = &ftm_alarm0;
  23                 rtic-a = &rtic_a;
  24                 rtic-b = &rtic_b;
  25                 rtic-c = &rtic_c;
  26                 rtic-d = &rtic_d;
  27                 sec-mon = &sec_mon;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53";
  37                         reg = <0x0>;
  38                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  39                         #cooling-cells = <2>;
  40                         cpu-idle-states = <&CPU_PH20>;
  41                 };
  42         };
  43
  44         idle-states {
  45                 /*
  46                  * PSCI node is not added default, U-boot will add missing
  47                  * parts if it determines to use PSCI.
  48                  */
  49                 entry-method = "psci";
  50
  51                 CPU_PH20: cpu-ph20 {
  52                         compatible = "arm,idle-state";
  53                         idle-state-name = "PH20";
  54                         arm,psci-suspend-param = <0x0>;
  55                         entry-latency-us = <1000>;
  56                         exit-latency-us = <1000>;
  57                         min-residency-us = <3000>;
  58                 };
  59         };
  60
  61         sysclk: sysclk {
  62                 compatible = "fixed-clock";
  63                 #clock-cells = <0>;
  64                 clock-frequency = <125000000>;
  65                 clock-output-names = "sysclk";
  66         };
  67
  68         coreclk: coreclk {
  69                 compatible = "fixed-clock";
  70                 #clock-cells = <0>;
  71                 clock-frequency = <100000000>;
  72                 clock-output-names = "coreclk";
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv8-timer";
  77                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
  78                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
  79                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
  80                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
  81         };
  82
  83         pmu {
  84                 compatible = "arm,armv8-pmuv3";
  85                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
  86         };
  87
  88         gic: interrupt-controller@1400000 {
  89                 compatible = "arm,gic-400";
  90                 #interrupt-cells = <3>;
  91                 interrupt-controller;
  92                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  93                       <0x0 0x1402000 0 0x2000>, /* GICC */
  94                       <0x0 0x1404000 0 0x2000>, /* GICH */
  95                       <0x0 0x1406000 0 0x2000>; /* GICV */
  96                 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
  97         };
  98
  99         reboot {
 100                 compatible = "syscon-reboot";
 101                 regmap = <&dcfg>;
 102                 offset = <0xb0>;
 103                 mask = <0x02>;
 104         };
 105
 106         thermal-zones {
 107                 cpu_thermal: cpu-thermal {
 108                         polling-delay-passive = <1000>;
 109                         polling-delay = <5000>;
 110                         thermal-sensors = <&tmu 0>;
 111
 112                         trips {
 113                                 cpu_alert: cpu-alert {
 114                                         temperature = <85000>;
 115                                         hysteresis = <2000>;
 116                                         type = "passive";
 117                                 };
 118
 119                                 cpu_crit: cpu-crit {
 120                                         temperature = <95000>;
 121                                         hysteresis = <2000>;
 122                                         type = "critical";
 123                                 };
 124                         };
 125
 126                         cooling-maps {
 127                                 map0 {
 128                                         trip = <&cpu_alert>;
 129                                         cooling-device =
 130                                                 <&cpu0 THERMAL_NO_LIMIT
 131                                                 THERMAL_NO_LIMIT>;
 132                                 };
 133                         };
 134                 };
 135         };
 136
 137         soc {
 138                 compatible = "simple-bus";
 139                 #address-cells = <2>;
 140                 #size-cells = <2>;
 141                 ranges;
 142
 143                 qspi: spi@1550000 {
 144                         compatible = "fsl,ls1021a-qspi";
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         reg = <0x0 0x1550000 0x0 0x10000>,
 148                                 <0x0 0x40000000 0x0 0x10000000>;
 149                         reg-names = "QuadSPI", "QuadSPI-memory";
 150                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 151                         clock-names = "qspi_en", "qspi";
 152                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 153                                             QORIQ_CLK_PLL_DIV(1)>,
 154                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 155                                             QORIQ_CLK_PLL_DIV(1)>;
 156                         status = "disabled";
 157                 };
 158
 159                 esdhc0: esdhc@1560000 {
 160                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 161                         reg = <0x0 0x1560000 0x0 0x10000>;
 162                         interrupts = <0 62 0x4>;
 163                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 164                                             QORIQ_CLK_PLL_DIV(1)>;
 165                         voltage-ranges = <1800 1800 3300 3300>;
 166                         sdhci,auto-cmd12;
 167                         big-endian;
 168                         bus-width = <4>;
 169                         status = "disabled";
 170                 };
 171
 172                 scfg: scfg@1570000 {
 173                         compatible = "fsl,ls1012a-scfg", "syscon";
 174                         reg = <0x0 0x1570000 0x0 0x10000>;
 175                         big-endian;
 176                 };
 177
 178                 esdhc1: esdhc@1580000 {
 179                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 180                         reg = <0x0 0x1580000 0x0 0x10000>;
 181                         interrupts = <0 65 0x4>;
 182                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 183                                             QORIQ_CLK_PLL_DIV(1)>;
 184                         voltage-ranges = <1800 1800 3300 3300>;
 185                         sdhci,auto-cmd12;
 186                         big-endian;
 187                         broken-cd;
 188                         bus-width = <4>;
 189                         status = "disabled";
 190                 };
 191
 192                 crypto: crypto@1700000 {
 193                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 194                                      "fsl,sec-v4.0";
 195                         fsl,sec-era = <8>;
 196                         #address-cells = <1>;
 197                         #size-cells = <1>;
 198                         ranges = <0x0 0x00 0x1700000 0x100000>;
 199                         reg = <0x00 0x1700000 0x0 0x100000>;
 200                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 201                         dma-coherent;
 202
 203                         sec_jr0: jr@10000 {
 204                                 compatible = "fsl,sec-v5.4-job-ring",
 205                                              "fsl,sec-v5.0-job-ring",
 206                                              "fsl,sec-v4.0-job-ring";
 207                                 reg = <0x10000 0x10000>;
 208                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 209                         };
 210
 211                         sec_jr1: jr@20000 {
 212                                 compatible = "fsl,sec-v5.4-job-ring",
 213                                              "fsl,sec-v5.0-job-ring",
 214                                              "fsl,sec-v4.0-job-ring";
 215                                 reg = <0x20000 0x10000>;
 216                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 217                         };
 218
 219                         sec_jr2: jr@30000 {
 220                                 compatible = "fsl,sec-v5.4-job-ring",
 221                                              "fsl,sec-v5.0-job-ring",
 222                                              "fsl,sec-v4.0-job-ring";
 223                                 reg = <0x30000 0x10000>;
 224                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 225                         };
 226
 227                         sec_jr3: jr@40000 {
 228                                 compatible = "fsl,sec-v5.4-job-ring",
 229                                              "fsl,sec-v5.0-job-ring",
 230                                              "fsl,sec-v4.0-job-ring";
 231                                 reg = <0x40000 0x10000>;
 232                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 233                         };
 234
 235                         rtic@60000 {
 236                                 compatible = "fsl,sec-v5.4-rtic",
 237                                              "fsl,sec-v5.0-rtic",
 238                                              "fsl,sec-v4.0-rtic";
 239                                 #address-cells = <1>;
 240                                 #size-cells = <1>;
 241                                 reg = <0x60000 0x100>, <0x60e00 0x18>;
 242                                 ranges = <0x0 0x60100 0x500>;
 243
 244                                 rtic_a: rtic-a@0 {
 245                                         compatible = "fsl,sec-v5.4-rtic-memory",
 246                                                      "fsl,sec-v5.0-rtic-memory",
 247                                                      "fsl,sec-v4.0-rtic-memory";
 248                                         reg = <0x00 0x20>, <0x100 0x100>;
 249                                 };
 250
 251                                 rtic_b: rtic-b@20 {
 252                                         compatible = "fsl,sec-v5.4-rtic-memory",
 253                                                      "fsl,sec-v5.0-rtic-memory",
 254                                                      "fsl,sec-v4.0-rtic-memory";
 255                                         reg = <0x20 0x20>, <0x200 0x100>;
 256                                 };
 257
 258                                 rtic_c: rtic-c@40 {
 259                                         compatible = "fsl,sec-v5.4-rtic-memory",
 260                                                      "fsl,sec-v5.0-rtic-memory",
 261                                                      "fsl,sec-v4.0-rtic-memory";
 262                                         reg = <0x40 0x20>, <0x300 0x100>;
 263                                 };
 264
 265                                 rtic_d: rtic-d@60 {
 266                                         compatible = "fsl,sec-v5.4-rtic-memory",
 267                                                      "fsl,sec-v5.0-rtic-memory",
 268                                                      "fsl,sec-v4.0-rtic-memory";
 269                                         reg = <0x60 0x20>, <0x400 0x100>;
 270                                 };
 271                         };
 272                 };
 273
 274                 sfp: efuse@1e80000 {
 275                         compatible = "fsl,ls1021a-sfp";
 276                         reg = <0x0 0x1e80000 0x0 0x10000>;
 277                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 278                                             QORIQ_CLK_PLL_DIV(4)>;
 279                         clock-names = "sfp";
 280                 };
 281
 282                 sec_mon: sec_mon@1e90000 {
 283                         compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 284                                      "fsl,sec-v4.0-mon";
 285                         reg = <0x0 0x1e90000 0x0 0x10000>;
 286                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 287                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 288                 };
 289
 290                 dcfg: dcfg@1ee0000 {
 291                         compatible = "fsl,ls1012a-dcfg",
 292                                      "syscon";
 293                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 294                         big-endian;
 295                 };
 296
 297                 clockgen: clocking@1ee1000 {
 298                         compatible = "fsl,ls1012a-clockgen";
 299                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 300                         #clock-cells = <2>;
 301                         clocks = <&sysclk &coreclk>;
 302                         clock-names = "sysclk", "coreclk";
 303                 };
 304
 305                 tmu: tmu@1f00000 {
 306                         compatible = "fsl,qoriq-tmu";
 307                         reg = <0x0 0x1f00000 0x0 0x10000>;
 308                         interrupts = <0 33 0x4>;
 309                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
 310                         fsl,tmu-calibration = <0x00000000 0x00000025
 311                                                0x00000001 0x0000002c
 312                                                0x00000002 0x00000032
 313                                                0x00000003 0x00000039
 314                                                0x00000004 0x0000003f
 315                                                0x00000005 0x00000046
 316                                                0x00000006 0x0000004c
 317                                                0x00000007 0x00000053
 318                                                0x00000008 0x00000059
 319                                                0x00000009 0x0000005f
 320                                                0x0000000a 0x00000066
 321                                                0x0000000b 0x0000006c
 322
 323                                                0x00010000 0x00000026
 324                                                0x00010001 0x0000002d
 325                                                0x00010002 0x00000035
 326                                                0x00010003 0x0000003d
 327                                                0x00010004 0x00000045
 328                                                0x00010005 0x0000004d
 329                                                0x00010006 0x00000055
 330                                                0x00010007 0x0000005d
 331                                                0x00010008 0x00000065
 332                                                0x00010009 0x0000006d
 333
 334                                                0x00020000 0x00000026
 335                                                0x00020001 0x00000030
 336                                                0x00020002 0x0000003a
 337                                                0x00020003 0x00000044
 338                                                0x00020004 0x0000004e
 339                                                0x00020005 0x00000059
 340                                                0x00020006 0x00000063
 341
 342                                                0x00030000 0x00000014
 343                                                0x00030001 0x00000021
 344                                                0x00030002 0x0000002e
 345                                                0x00030003 0x0000003a
 346                                                0x00030004 0x00000047
 347                                                0x00030005 0x00000053
 348                                                0x00030006 0x00000060>;
 349                         big-endian;
 350                         #thermal-sensor-cells = <1>;
 351                 };
 352
 353                 i2c0: i2c@2180000 {
 354                         compatible = "fsl,vf610-i2c";
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         reg = <0x0 0x2180000 0x0 0x10000>;
 358                         interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 359                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 360                                             QORIQ_CLK_PLL_DIV(4)>;
 361                         status = "disabled";
 362                 };
 363
 364                 i2c1: i2c@2190000 {
 365                         compatible = "fsl,vf610-i2c";
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         reg = <0x0 0x2190000 0x0 0x10000>;
 369                         interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 371                                             QORIQ_CLK_PLL_DIV(4)>;
 372                         status = "disabled";
 373                 };
 374
 375                 dspi: spi@2100000 {
 376                         compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
 377                         #address-cells = <1>;
 378                         #size-cells = <0>;
 379                         reg = <0x0 0x2100000 0x0 0x10000>;
 380                         interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
 381                         clock-names = "dspi";
 382                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 383                                             QORIQ_CLK_PLL_DIV(1)>;
 384                         spi-num-chipselects = <5>;
 385                         big-endian;
 386                         status = "disabled";
 387                 };
 388
 389                 duart0: serial@21c0500 {
 390                         compatible = "fsl,ns16550", "ns16550a";
 391                         reg = <0x00 0x21c0500 0x0 0x100>;
 392                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 393                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 394                                             QORIQ_CLK_PLL_DIV(1)>;
 395                         status = "disabled";
 396                 };
 397
 398                 duart1: serial@21c0600 {
 399                         compatible = "fsl,ns16550", "ns16550a";
 400                         reg = <0x00 0x21c0600 0x0 0x100>;
 401                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 403                                             QORIQ_CLK_PLL_DIV(1)>;
 404                         status = "disabled";
 405                 };
 406
 407                 gpio0: gpio@2300000 {
 408                         compatible = "fsl,qoriq-gpio";
 409                         reg = <0x0 0x2300000 0x0 0x10000>;
 410                         interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
 411                         gpio-controller;
 412                         #gpio-cells = <2>;
 413                         interrupt-controller;
 414                         #interrupt-cells = <2>;
 415                 };
 416
 417                 gpio1: gpio@2310000 {
 418                         compatible = "fsl,qoriq-gpio";
 419                         reg = <0x0 0x2310000 0x0 0x10000>;
 420                         interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 421                         gpio-controller;
 422                         #gpio-cells = <2>;
 423                         interrupt-controller;
 424                         #interrupt-cells = <2>;
 425                 };
 426
 427                 wdog0: watchdog@2ad0000 {
 428                         compatible = "fsl,ls1012a-wdt",
 429                                      "fsl,imx21-wdt";
 430                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 431                         interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 432                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
 433                         big-endian;
 434                 };
 435
 436                 sai1: sai@2b50000 {
 437                         #sound-dai-cells = <0>;
 438                         compatible = "fsl,vf610-sai";
 439                         reg = <0x0 0x2b50000 0x0 0x10000>;
 440                         interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 441                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 442                                             QORIQ_CLK_PLL_DIV(4)>,
 443                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 444                                             QORIQ_CLK_PLL_DIV(4)>,
 445                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 446                                             QORIQ_CLK_PLL_DIV(4)>,
 447                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 448                                             QORIQ_CLK_PLL_DIV(4)>;
 449                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 450                         dma-names = "tx", "rx";
 451                         dmas = <&edma0 1 47>,
 452                                <&edma0 1 46>;
 453                         status = "disabled";
 454                 };
 455
 456                 sai2: sai@2b60000 {
 457                         #sound-dai-cells = <0>;
 458                         compatible = "fsl,vf610-sai";
 459                         reg = <0x0 0x2b60000 0x0 0x10000>;
 460                         interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 461                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 462                                             QORIQ_CLK_PLL_DIV(4)>,
 463                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 464                                             QORIQ_CLK_PLL_DIV(4)>,
 465                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 466                                             QORIQ_CLK_PLL_DIV(4)>,
 467                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 468                                             QORIQ_CLK_PLL_DIV(4)>;
 469                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 470                         dma-names = "tx", "rx";
 471                         dmas = <&edma0 1 45>,
 472                                <&edma0 1 44>;
 473                         status = "disabled";
 474                 };
 475
 476                 edma0: dma-controller@2c00000 {
 477                         #dma-cells = <2>;
 478                         compatible = "fsl,vf610-edma";
 479                         reg = <0x0 0x2c00000 0x0 0x10000>,
 480                               <0x0 0x2c10000 0x0 0x10000>,
 481                               <0x0 0x2c20000 0x0 0x10000>;
 482                         interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
 483                                      <0 103 IRQ_TYPE_LEVEL_HIGH>;
 484                         interrupt-names = "edma-tx", "edma-err";
 485                         dma-channels = <32>;
 486                         big-endian;
 487                         clock-names = "dmamux0", "dmamux1";
 488                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 489                                             QORIQ_CLK_PLL_DIV(4)>,
 490                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 491                                             QORIQ_CLK_PLL_DIV(4)>;
 492                 };
 493
 494                 usb0: usb@2f00000 {
 495                         compatible = "snps,dwc3";
 496                         reg = <0x0 0x2f00000 0x0 0x10000>;
 497                         interrupts = <0 60 0x4>;
 498                         dr_mode = "host";
 499                         snps,quirk-frame-length-adjustment = <0x20>;
 500                         snps,dis_rxdet_inp3_quirk;
 501                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 502                 };
 503
 504                 sata: sata@3200000 {
 505                         compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
 506                         reg = <0x0 0x3200000 0x0 0x10000>,
 507                                 <0x0 0x20140520 0x0 0x4>;
 508                         reg-names = "ahci", "sata-ecc";
 509                         interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 511                                             QORIQ_CLK_PLL_DIV(1)>;
 512                         dma-coherent;
 513                         status = "disabled";
 514                 };
 515
 516                 usb1: usb@8600000 {
 517                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 518                         reg = <0x0 0x8600000 0x0 0x1000>;
 519                         interrupts = <0 139 0x4>;
 520                         dr_mode = "host";
 521                         phy_type = "ulpi";
 522                 };
 523
 524                 msi: msi-controller1@1572000 {
 525                         compatible = "fsl,ls1012a-msi";
 526                         reg = <0x0 0x1572000 0x0 0x8>;
 527                         msi-controller;
 528                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 529                 };
 530
 531                 pcie1: pcie@3400000 {
 532                         compatible = "fsl,ls1012a-pcie";
 533                         reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
 534                               <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 535                         reg-names = "regs", "config";
 536                         interrupts = <0 118 0x4>, /* controller interrupt */
 537                                      <0 117 0x4>; /* PME interrupt */
 538                         interrupt-names = "aer", "pme";
 539                         #address-cells = <3>;
 540                         #size-cells = <2>;
 541                         device_type = "pci";
 542                         num-viewport = <2>;
 543                         bus-range = <0x0 0xff>;
 544                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 545                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 546                         msi-parent = <&msi>;
 547                         #interrupt-cells = <1>;
 548                         interrupt-map-mask = <0 0 0 7>;
 549                         interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
 550                                         <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
 551                                         <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
 552                                         <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
 553                         status = "disabled";
 554                 };
 555
 556                 rcpm: power-controller@1ee2140 {
 557                         compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
 558                         reg = <0x0 0x1ee2140 0x0 0x4>;
 559                         #fsl,rcpm-wakeup-cells = <1>;
 560                 };
 561
 562                 ftm_alarm0: timer@29d0000 {
 563                         compatible = "fsl,ls1012a-ftm-alarm";
 564                         reg = <0x0 0x29d0000 0x0 0x10000>;
 565                         fsl,rcpm-wakeup = <&rcpm 0x20000>;
 566                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 567                         big-endian;
 568                 };
 569         };
 570
 571         firmware {
 572                 optee {
 573                         compatible = "linaro,optee-tz";
 574                         method = "smc";
 575                 };
 576         };
 577 };