arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-1012A family SoC.
   3  *
   4  * Copyright 2016 Freescale Semiconductor, Inc.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPLv2 or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 / {
  49         compatible = "fsl,ls1012a";
  50         interrupt-parent = <&gic>;
  51         #address-cells = <2>;
  52         #size-cells = <2>;
  53
  54         aliases {
  55                 crypto = &crypto;
  56                 rtic_a = &rtic_a;
  57                 rtic_b = &rtic_b;
  58                 rtic_c = &rtic_c;
  59                 rtic_d = &rtic_d;
  60                 sec_mon = &sec_mon;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu0: cpu@0 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a53";
  70                         reg = <0x0>;
  71                         clocks = <&clockgen 1 0>;
  72                         #cooling-cells = <2>;
  73                 };
  74         };
  75
  76         sysclk: sysclk {
  77                 compatible = "fixed-clock";
  78                 #clock-cells = <0>;
  79                 clock-frequency = <125000000>;
  80                 clock-output-names = "sysclk";
  81         };
  82
  83         coreclk: coreclk {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency = <100000000>;
  87                 clock-output-names = "coreclk";
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv8-timer";
  92                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
  93                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
  94                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
  95                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
  96         };
  97
  98         pmu {
  99                 compatible = "arm,armv8-pmuv3";
 100                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 101         };
 102
 103         gic: interrupt-controller@1400000 {
 104                 compatible = "arm,gic-400";
 105                 #interrupt-cells = <3>;
 106                 interrupt-controller;
 107                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
 108                       <0x0 0x1402000 0 0x2000>, /* GICC */
 109                       <0x0 0x1404000 0 0x2000>, /* GICH */
 110                       <0x0 0x1406000 0 0x2000>; /* GICV */
 111                 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
 112         };
 113
 114         reboot {
 115                 compatible = "syscon-reboot";
 116                 regmap = <&dcfg>;
 117                 offset = <0xb0>;
 118                 mask = <0x02>;
 119         };
 120
 121         soc {
 122                 compatible = "simple-bus";
 123                 #address-cells = <2>;
 124                 #size-cells = <2>;
 125                 ranges;
 126
 127                 esdhc0: esdhc@1560000 {
 128                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 129                         reg = <0x0 0x1560000 0x0 0x10000>;
 130                         interrupts = <0 62 0x4>;
 131                         clocks = <&clockgen 4 0>;
 132                         voltage-ranges = <1800 1800 3300 3300>;
 133                         sdhci,auto-cmd12;
 134                         big-endian;
 135                         bus-width = <4>;
 136                         status = "disabled";
 137                 };
 138
 139                 scfg: scfg@1570000 {
 140                         compatible = "fsl,ls1012a-scfg", "syscon";
 141                         reg = <0x0 0x1570000 0x0 0x10000>;
 142                         big-endian;
 143                 };
 144
 145                 esdhc1: esdhc@1580000 {
 146                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 147                         reg = <0x0 0x1580000 0x0 0x10000>;
 148                         interrupts = <0 65 0x4>;
 149                         clocks = <&clockgen 4 0>;
 150                         voltage-ranges = <1800 1800 3300 3300>;
 151                         sdhci,auto-cmd12;
 152                         big-endian;
 153                         broken-cd;
 154                         bus-width = <4>;
 155                         status = "disabled";
 156                 };
 157
 158                 crypto: crypto@1700000 {
 159                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 160                                      "fsl,sec-v4.0";
 161                         fsl,sec-era = <8>;
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         ranges = <0x0 0x00 0x1700000 0x100000>;
 165                         reg = <0x00 0x1700000 0x0 0x100000>;
 166                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 167                         dma-coherent;
 168
 169                         sec_jr0: jr@10000 {
 170                                 compatible = "fsl,sec-v5.4-job-ring",
 171                                              "fsl,sec-v5.0-job-ring",
 172                                              "fsl,sec-v4.0-job-ring";
 173                                 reg        = <0x10000 0x10000>;
 174                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 175                         };
 176
 177                         sec_jr1: jr@20000 {
 178                                 compatible = "fsl,sec-v5.4-job-ring",
 179                                              "fsl,sec-v5.0-job-ring",
 180                                              "fsl,sec-v4.0-job-ring";
 181                                 reg        = <0x20000 0x10000>;
 182                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 183                         };
 184
 185                         sec_jr2: jr@30000 {
 186                                 compatible = "fsl,sec-v5.4-job-ring",
 187                                              "fsl,sec-v5.0-job-ring",
 188                                              "fsl,sec-v4.0-job-ring";
 189                                 reg        = <0x30000 0x10000>;
 190                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 191                         };
 192
 193                         sec_jr3: jr@40000 {
 194                                 compatible = "fsl,sec-v5.4-job-ring",
 195                                              "fsl,sec-v5.0-job-ring",
 196                                              "fsl,sec-v4.0-job-ring";
 197                                 reg        = <0x40000 0x10000>;
 198                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 199                         };
 200
 201                         rtic@60000 {
 202                                 compatible = "fsl,sec-v5.4-rtic",
 203                                              "fsl,sec-v5.0-rtic",
 204                                              "fsl,sec-v4.0-rtic";
 205                                 #address-cells = <1>;
 206                                 #size-cells = <1>;
 207                                 reg = <0x60000 0x100 0x60e00 0x18>;
 208                                 ranges = <0x0 0x60100 0x500>;
 209
 210                                 rtic_a: rtic-a@0 {
 211                                         compatible = "fsl,sec-v5.4-rtic-memory",
 212                                                      "fsl,sec-v5.0-rtic-memory",
 213                                                      "fsl,sec-v4.0-rtic-memory";
 214                                         reg = <0x00 0x20 0x100 0x100>;
 215                                 };
 216
 217                                 rtic_b: rtic-b@20 {
 218                                         compatible = "fsl,sec-v5.4-rtic-memory",
 219                                                      "fsl,sec-v5.0-rtic-memory",
 220                                                      "fsl,sec-v4.0-rtic-memory";
 221                                         reg = <0x20 0x20 0x200 0x100>;
 222                                 };
 223
 224                                 rtic_c: rtic-c@40 {
 225                                         compatible = "fsl,sec-v5.4-rtic-memory",
 226                                                      "fsl,sec-v5.0-rtic-memory",
 227                                                      "fsl,sec-v4.0-rtic-memory";
 228                                         reg = <0x40 0x20 0x300 0x100>;
 229                                 };
 230
 231                                 rtic_d: rtic-d@60 {
 232                                         compatible = "fsl,sec-v5.4-rtic-memory",
 233                                                      "fsl,sec-v5.0-rtic-memory",
 234                                                      "fsl,sec-v4.0-rtic-memory";
 235                                         reg = <0x60 0x20 0x400 0x100>;
 236                                 };
 237                         };
 238                 };
 239
 240                 sec_mon: sec_mon@1e90000 {
 241                         compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 242                                      "fsl,sec-v4.0-mon";
 243                         reg = <0x0 0x1e90000 0x0 0x10000>;
 244                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 246                 };
 247
 248                 dcfg: dcfg@1ee0000 {
 249                         compatible = "fsl,ls1012a-dcfg",
 250                                      "syscon";
 251                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 252                         big-endian;
 253                 };
 254
 255                 clockgen: clocking@1ee1000 {
 256                         compatible = "fsl,ls1012a-clockgen";
 257                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 258                         #clock-cells = <2>;
 259                         clocks = <&sysclk &coreclk>;
 260                         clock-names = "sysclk", "coreclk";
 261                 };
 262
 263                 tmu: tmu@1f00000 {
 264                         compatible = "fsl,qoriq-tmu";
 265                         reg = <0x0 0x1f00000 0x0 0x10000>;
 266                         interrupts = <0 33 0x4>;
 267                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 268                         fsl,tmu-calibration = <0x00000000 0x00000026
 269                                                0x00000001 0x0000002d
 270                                                0x00000002 0x00000032
 271                                                0x00000003 0x00000039
 272                                                0x00000004 0x0000003f
 273                                                0x00000005 0x00000046
 274                                                0x00000006 0x0000004d
 275                                                0x00000007 0x00000054
 276                                                0x00000008 0x0000005a
 277                                                0x00000009 0x00000061
 278                                                0x0000000a 0x0000006a
 279                                                0x0000000b 0x00000071
 280
 281                                                0x00010000 0x00000025
 282                                                0x00010001 0x0000002c
 283                                                0x00010002 0x00000035
 284                                                0x00010003 0x0000003d
 285                                                0x00010004 0x00000045
 286                                                0x00010005 0x0000004e
 287                                                0x00010006 0x00000057
 288                                                0x00010007 0x00000061
 289                                                0x00010008 0x0000006b
 290                                                0x00010009 0x00000076
 291
 292                                                0x00020000 0x00000029
 293                                                0x00020001 0x00000033
 294                                                0x00020002 0x0000003d
 295                                                0x00020003 0x00000049
 296                                                0x00020004 0x00000056
 297                                                0x00020005 0x00000061
 298                                                0x00020006 0x0000006d
 299
 300                                                0x00030000 0x00000021
 301                                                0x00030001 0x0000002a
 302                                                0x00030002 0x0000003c
 303                                                0x00030003 0x0000004e>;
 304                         big-endian;
 305                         #thermal-sensor-cells = <1>;
 306                 };
 307
 308                 thermal-zones {
 309                         cpu_thermal: cpu-thermal {
 310                                 polling-delay-passive = <1000>;
 311                                 polling-delay = <5000>;
 312                                 thermal-sensors = <&tmu 0>;
 313
 314                                 trips {
 315                                         cpu_alert: cpu-alert {
 316                                                 temperature = <85000>;
 317                                                 hysteresis = <2000>;
 318                                                 type = "passive";
 319                                         };
 320
 321                                         cpu_crit: cpu-crit {
 322                                                 temperature = <95000>;
 323                                                 hysteresis = <2000>;
 324                                                 type = "critical";
 325                                         };
 326                                 };
 327
 328                                 cooling-maps {
 329                                         map0 {
 330                                                 trip = <&cpu_alert>;
 331                                                 cooling-device =
 332                                                         <&cpu0 THERMAL_NO_LIMIT
 333                                                         THERMAL_NO_LIMIT>;
 334                                         };
 335                                 };
 336                         };
 337                 };
 338
 339                 i2c0: i2c@2180000 {
 340                         compatible = "fsl,vf610-i2c";
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                         reg = <0x0 0x2180000 0x0 0x10000>;
 344                         interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 345                         clocks = <&clockgen 4 0>;
 346                         status = "disabled";
 347                 };
 348
 349                 i2c1: i2c@2190000 {
 350                         compatible = "fsl,vf610-i2c";
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                         reg = <0x0 0x2190000 0x0 0x10000>;
 354                         interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&clockgen 4 0>;
 356                         status = "disabled";
 357                 };
 358
 359                 duart0: serial@21c0500 {
 360                         compatible = "fsl,ns16550", "ns16550a";
 361                         reg = <0x00 0x21c0500 0x0 0x100>;
 362                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 363                         clocks = <&clockgen 4 0>;
 364                         status = "disabled";
 365                 };
 366
 367                 duart1: serial@21c0600 {
 368                         compatible = "fsl,ns16550", "ns16550a";
 369                         reg = <0x00 0x21c0600 0x0 0x100>;
 370                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 371                         clocks = <&clockgen 4 0>;
 372                         status = "disabled";
 373                 };
 374
 375                 gpio0: gpio@2300000 {
 376                         compatible = "fsl,qoriq-gpio";
 377                         reg = <0x0 0x2300000 0x0 0x10000>;
 378                         interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
 379                         gpio-controller;
 380                         #gpio-cells = <2>;
 381                         interrupt-controller;
 382                         #interrupt-cells = <2>;
 383                 };
 384
 385                 gpio1: gpio@2310000 {
 386                         compatible = "fsl,qoriq-gpio";
 387                         reg = <0x0 0x2310000 0x0 0x10000>;
 388                         interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 389                         gpio-controller;
 390                         #gpio-cells = <2>;
 391                         interrupt-controller;
 392                         #interrupt-cells = <2>;
 393                 };
 394
 395                 wdog0: wdog@2ad0000 {
 396                         compatible = "fsl,ls1012a-wdt",
 397                                      "fsl,imx21-wdt";
 398                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 399                         interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&clockgen 4 0>;
 401                         big-endian;
 402                 };
 403
 404                 sai1: sai@2b50000 {
 405                         #sound-dai-cells = <0>;
 406                         compatible = "fsl,vf610-sai";
 407                         reg = <0x0 0x2b50000 0x0 0x10000>;
 408                         interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 409                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 410                                  <&clockgen 4 3>, <&clockgen 4 3>;
 411                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 412                         dma-names = "tx", "rx";
 413                         dmas = <&edma0 1 47>,
 414                                <&edma0 1 46>;
 415                         status = "disabled";
 416                 };
 417
 418                 sai2: sai@2b60000 {
 419                         #sound-dai-cells = <0>;
 420                         compatible = "fsl,vf610-sai";
 421                         reg = <0x0 0x2b60000 0x0 0x10000>;
 422                         interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 424                                  <&clockgen 4 3>, <&clockgen 4 3>;
 425                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 426                         dma-names = "tx", "rx";
 427                         dmas = <&edma0 1 45>,
 428                                <&edma0 1 44>;
 429                         status = "disabled";
 430                 };
 431
 432                 edma0: edma@2c00000 {
 433                         #dma-cells = <2>;
 434                         compatible = "fsl,vf610-edma";
 435                         reg = <0x0 0x2c00000 0x0 0x10000>,
 436                               <0x0 0x2c10000 0x0 0x10000>,
 437                               <0x0 0x2c20000 0x0 0x10000>;
 438                         interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
 439                                      <0 103 IRQ_TYPE_LEVEL_HIGH>;
 440                         interrupt-names = "edma-tx", "edma-err";
 441                         dma-channels = <32>;
 442                         big-endian;
 443                         clock-names = "dmamux0", "dmamux1";
 444                         clocks = <&clockgen 4 3>,
 445                                  <&clockgen 4 3>;
 446                 };
 447
 448                 usb0: usb3@2f00000 {
 449                         compatible = "snps,dwc3";
 450                         reg = <0x0 0x2f00000 0x0 0x10000>;
 451                         interrupts = <0 60 0x4>;
 452                         dr_mode = "host";
 453                         snps,quirk-frame-length-adjustment = <0x20>;
 454                         snps,dis_rxdet_inp3_quirk;
 455                 };
 456
 457                 sata: sata@3200000 {
 458                         compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
 459                         reg = <0x0 0x3200000 0x0 0x10000>,
 460                                 <0x0 0x20140520 0x0 0x4>;
 461                         reg-names = "ahci", "sata-ecc";
 462                         interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&clockgen 4 0>;
 464                         dma-coherent;
 465                         status = "disabled";
 466                 };
 467
 468                 usb1: usb2@8600000 {
 469                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 470                         reg = <0x0 0x8600000 0x0 0x1000>;
 471                         interrupts = <0 139 0x4>;
 472                         dr_mode = "host";
 473                         phy_type = "ulpi";
 474                 };
 475         };
 476 };