arch/arm64/boot/dts/exynos/exynos7.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS7 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 #include <dt-bindings/clock/exynos7-clk.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "samsung,exynos7";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 pinctrl0 = &pinctrl_alive;
  20                 pinctrl1 = &pinctrl_bus0;
  21                 pinctrl2 = &pinctrl_nfc;
  22                 pinctrl3 = &pinctrl_touch;
  23                 pinctrl4 = &pinctrl_ff;
  24                 pinctrl5 = &pinctrl_ese;
  25                 pinctrl6 = &pinctrl_fsys0;
  26                 pinctrl7 = &pinctrl_fsys1;
  27                 pinctrl8 = &pinctrl_bus1;
  28                 tmuctrl0 = &tmuctrl_0;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu_atlas0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a57", "arm,armv8";
  38                         reg = <0x0>;
  39                         enable-method = "psci";
  40                 };
  41
  42                 cpu_atlas1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a57", "arm,armv8";
  45                         reg = <0x1>;
  46                         enable-method = "psci";
  47                 };
  48
  49                 cpu_atlas2: cpu@2 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a57", "arm,armv8";
  52                         reg = <0x2>;
  53                         enable-method = "psci";
  54                 };
  55
  56                 cpu_atlas3: cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a57", "arm,armv8";
  59                         reg = <0x3>;
  60                         enable-method = "psci";
  61                 };
  62         };
  63
  64         psci {
  65                 compatible = "arm,psci";
  66                 method = "smc";
  67                 cpu_off = <0x84000002>;
  68                 cpu_on = <0xC4000003>;
  69         };
  70
  71         soc: soc {
  72                 compatible = "simple-bus";
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 ranges = <0 0 0 0x18000000>;
  76
  77                 chipid@10000000 {
  78                         compatible = "samsung,exynos4210-chipid";
  79                         reg = <0x10000000 0x100>;
  80                 };
  81
  82                 fin_pll: xxti {
  83                         compatible = "fixed-clock";
  84                         clock-output-names = "fin_pll";
  85                         #clock-cells = <0>;
  86                 };
  87
  88                 gic: interrupt-controller@11001000 {
  89                         compatible = "arm,gic-400";
  90                         #interrupt-cells = <3>;
  91                         #address-cells = <0>;
  92                         interrupt-controller;
  93                         reg =   <0x11001000 0x1000>,
  94                                 <0x11002000 0x2000>,
  95                                 <0x11004000 0x2000>,
  96                                 <0x11006000 0x2000>;
  97                 };
  98
  99                 amba {
 100                         compatible = "simple-bus";
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103                         ranges;
 104
 105                         pdma0: pdma@10e10000 {
 106                                 compatible = "arm,pl330", "arm,primecell";
 107                                 reg = <0x10E10000 0x1000>;
 108                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 109                                 clocks = <&clock_fsys0 ACLK_PDMA0>;
 110                                 clock-names = "apb_pclk";
 111                                 #dma-cells = <1>;
 112                                 #dma-channels = <8>;
 113                                 #dma-requests = <32>;
 114                         };
 115
 116                         pdma1: pdma@10eb0000 {
 117                                 compatible = "arm,pl330", "arm,primecell";
 118                                 reg = <0x10EB0000 0x1000>;
 119                                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 120                                 clocks = <&clock_fsys0 ACLK_PDMA1>;
 121                                 clock-names = "apb_pclk";
 122                                 #dma-cells = <1>;
 123                                 #dma-channels = <8>;
 124                                 #dma-requests = <32>;
 125                         };
 126                 };
 127
 128                 clock_topc: clock-controller@10570000 {
 129                         compatible = "samsung,exynos7-clock-topc";
 130                         reg = <0x10570000 0x10000>;
 131                         #clock-cells = <1>;
 132                 };
 133
 134                 clock_top0: clock-controller@105d0000 {
 135                         compatible = "samsung,exynos7-clock-top0";
 136                         reg = <0x105d0000 0xb000>;
 137                         #clock-cells = <1>;
 138                         clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
 139                                  <&clock_topc DOUT_SCLK_BUS1_PLL>,
 140                                  <&clock_topc DOUT_SCLK_CC_PLL>,
 141                                  <&clock_topc DOUT_SCLK_MFC_PLL>;
 142                         clock-names = "fin_pll", "dout_sclk_bus0_pll",
 143                                       "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
 144                                       "dout_sclk_mfc_pll";
 145                 };
 146
 147                 clock_top1: clock-controller@105e0000 {
 148                         compatible = "samsung,exynos7-clock-top1";
 149                         reg = <0x105e0000 0xb000>;
 150                         #clock-cells = <1>;
 151                         clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
 152                                  <&clock_topc DOUT_SCLK_BUS1_PLL>,
 153                                  <&clock_topc DOUT_SCLK_CC_PLL>,
 154                                  <&clock_topc DOUT_SCLK_MFC_PLL>;
 155                         clock-names = "fin_pll", "dout_sclk_bus0_pll",
 156                                       "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
 157                                       "dout_sclk_mfc_pll";
 158                 };
 159
 160                 clock_ccore: clock-controller@105b0000 {
 161                         compatible = "samsung,exynos7-clock-ccore";
 162                         reg = <0x105b0000 0xd00>;
 163                         #clock-cells = <1>;
 164                         clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
 165                         clock-names = "fin_pll", "dout_aclk_ccore_133";
 166                 };
 167
 168                 clock_peric0: clock-controller@13610000 {
 169                         compatible = "samsung,exynos7-clock-peric0";
 170                         reg = <0x13610000 0xd00>;
 171                         #clock-cells = <1>;
 172                         clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
 173                                  <&clock_top0 CLK_SCLK_UART0>;
 174                         clock-names = "fin_pll", "dout_aclk_peric0_66",
 175                                       "sclk_uart0";
 176                 };
 177
 178                 clock_peric1: clock-controller@14c80000 {
 179                         compatible = "samsung,exynos7-clock-peric1";
 180                         reg = <0x14c80000 0xd00>;
 181                         #clock-cells = <1>;
 182                         clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
 183                                  <&clock_top0 CLK_SCLK_UART1>,
 184                                  <&clock_top0 CLK_SCLK_UART2>,
 185                                  <&clock_top0 CLK_SCLK_UART3>;
 186                         clock-names = "fin_pll", "dout_aclk_peric1_66",
 187                                       "sclk_uart1", "sclk_uart2", "sclk_uart3";
 188                 };
 189
 190                 clock_peris: clock-controller@10040000 {
 191                         compatible = "samsung,exynos7-clock-peris";
 192                         reg = <0x10040000 0xd00>;
 193                         #clock-cells = <1>;
 194                         clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
 195                         clock-names = "fin_pll", "dout_aclk_peris_66";
 196                 };
 197
 198                 clock_fsys0: clock-controller@10e90000 {
 199                         compatible = "samsung,exynos7-clock-fsys0";
 200                         reg = <0x10e90000 0xd00>;
 201                         #clock-cells = <1>;
 202                         clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
 203                                  <&clock_top1 DOUT_SCLK_MMC2>;
 204                         clock-names = "fin_pll", "dout_aclk_fsys0_200",
 205                                       "dout_sclk_mmc2";
 206                 };
 207
 208                 clock_fsys1: clock-controller@156e0000 {
 209                         compatible = "samsung,exynos7-clock-fsys1";
 210                         reg = <0x156e0000 0xd00>;
 211                         #clock-cells = <1>;
 212                         clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
 213                                  <&clock_top1 DOUT_SCLK_MMC0>,
 214                                  <&clock_top1 DOUT_SCLK_MMC1>;
 215                         clock-names = "fin_pll", "dout_aclk_fsys1_200",
 216                                       "dout_sclk_mmc0", "dout_sclk_mmc1";
 217                 };
 218
 219                 serial_0: serial@13630000 {
 220                         compatible = "samsung,exynos4210-uart";
 221                         reg = <0x13630000 0x100>;
 222                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 223                         clocks = <&clock_peric0 PCLK_UART0>,
 224                                  <&clock_peric0 SCLK_UART0>;
 225                         clock-names = "uart", "clk_uart_baud0";
 226                         status = "disabled";
 227                 };
 228
 229                 serial_1: serial@14c20000 {
 230                         compatible = "samsung,exynos4210-uart";
 231                         reg = <0x14c20000 0x100>;
 232                         interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
 233                         clocks = <&clock_peric1 PCLK_UART1>,
 234                                  <&clock_peric1 SCLK_UART1>;
 235                         clock-names = "uart", "clk_uart_baud0";
 236                         status = "disabled";
 237                 };
 238
 239                 serial_2: serial@14c30000 {
 240                         compatible = "samsung,exynos4210-uart";
 241                         reg = <0x14c30000 0x100>;
 242                         interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
 243                         clocks = <&clock_peric1 PCLK_UART2>,
 244                                  <&clock_peric1 SCLK_UART2>;
 245                         clock-names = "uart", "clk_uart_baud0";
 246                         status = "disabled";
 247                 };
 248
 249                 serial_3: serial@14c40000 {
 250                         compatible = "samsung,exynos4210-uart";
 251                         reg = <0x14c40000 0x100>;
 252                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&clock_peric1 PCLK_UART3>,
 254                                  <&clock_peric1 SCLK_UART3>;
 255                         clock-names = "uart", "clk_uart_baud0";
 256                         status = "disabled";
 257                 };
 258
 259                 pinctrl_alive: pinctrl@10580000 {
 260                         compatible = "samsung,exynos7-pinctrl";
 261                         reg = <0x10580000 0x1000>;
 262
 263                         wakeup-interrupt-controller {
 264                                 compatible = "samsung,exynos7-wakeup-eint";
 265                                 interrupt-parent = <&gic>;
 266                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 267                         };
 268                 };
 269
 270                 pinctrl_bus0: pinctrl@13470000 {
 271                         compatible = "samsung,exynos7-pinctrl";
 272                         reg = <0x13470000 0x1000>;
 273                         interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
 274                 };
 275
 276                 pinctrl_nfc: pinctrl@14cd0000 {
 277                         compatible = "samsung,exynos7-pinctrl";
 278                         reg = <0x14cd0000 0x1000>;
 279                         interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
 280                 };
 281
 282                 pinctrl_touch: pinctrl@14ce0000 {
 283                         compatible = "samsung,exynos7-pinctrl";
 284                         reg = <0x14ce0000 0x1000>;
 285                         interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
 286                 };
 287
 288                 pinctrl_ff: pinctrl@14c90000 {
 289                         compatible = "samsung,exynos7-pinctrl";
 290                         reg = <0x14c90000 0x1000>;
 291                         interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
 292                 };
 293
 294                 pinctrl_ese: pinctrl@14ca0000 {
 295                         compatible = "samsung,exynos7-pinctrl";
 296                         reg = <0x14ca0000 0x1000>;
 297                         interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
 298                 };
 299
 300                 pinctrl_fsys0: pinctrl@10e60000 {
 301                         compatible = "samsung,exynos7-pinctrl";
 302                         reg = <0x10e60000 0x1000>;
 303                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 304                 };
 305
 306                 pinctrl_fsys1: pinctrl@15690000 {
 307                         compatible = "samsung,exynos7-pinctrl";
 308                         reg = <0x15690000 0x1000>;
 309                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 310                 };
 311
 312                 pinctrl_bus1: pinctrl@14870000 {
 313                         compatible = "samsung,exynos7-pinctrl";
 314                         reg = <0x14870000 0x1000>;
 315                         interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 316                 };
 317
 318                 hsi2c_0: hsi2c@13640000 {
 319                         compatible = "samsung,exynos7-hsi2c";
 320                         reg = <0x13640000 0x1000>;
 321                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                         pinctrl-names = "default";
 325                         pinctrl-0 = <&hs_i2c0_bus>;
 326                         clocks = <&clock_peric0 PCLK_HSI2C0>;
 327                         clock-names = "hsi2c";
 328                         status = "disabled";
 329                 };
 330
 331                 hsi2c_1: hsi2c@13650000 {
 332                         compatible = "samsung,exynos7-hsi2c";
 333                         reg = <0x13650000 0x1000>;
 334                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         pinctrl-names = "default";
 338                         pinctrl-0 = <&hs_i2c1_bus>;
 339                         clocks = <&clock_peric0 PCLK_HSI2C1>;
 340                         clock-names = "hsi2c";
 341                         status = "disabled";
 342                 };
 343
 344                 hsi2c_2: hsi2c@14e60000 {
 345                         compatible = "samsung,exynos7-hsi2c";
 346                         reg = <0x14e60000 0x1000>;
 347                         interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         pinctrl-names = "default";
 351                         pinctrl-0 = <&hs_i2c2_bus>;
 352                         clocks = <&clock_peric1 PCLK_HSI2C2>;
 353                         clock-names = "hsi2c";
 354                         status = "disabled";
 355                 };
 356
 357                 hsi2c_3: hsi2c@14e70000 {
 358                         compatible = "samsung,exynos7-hsi2c";
 359                         reg = <0x14e70000 0x1000>;
 360                         interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         pinctrl-names = "default";
 364                         pinctrl-0 = <&hs_i2c3_bus>;
 365                         clocks = <&clock_peric1 PCLK_HSI2C3>;
 366                         clock-names = "hsi2c";
 367                         status = "disabled";
 368                 };
 369
 370                 hsi2c_4: hsi2c@13660000 {
 371                         compatible = "samsung,exynos7-hsi2c";
 372                         reg = <0x13660000 0x1000>;
 373                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         pinctrl-names = "default";
 377                         pinctrl-0 = <&hs_i2c4_bus>;
 378                         clocks = <&clock_peric0 PCLK_HSI2C4>;
 379                         clock-names = "hsi2c";
 380                         status = "disabled";
 381                 };
 382
 383                 hsi2c_5: hsi2c@13670000 {
 384                         compatible = "samsung,exynos7-hsi2c";
 385                         reg = <0x13670000 0x1000>;
 386                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389                         pinctrl-names = "default";
 390                         pinctrl-0 = <&hs_i2c5_bus>;
 391                         clocks = <&clock_peric0 PCLK_HSI2C5>;
 392                         clock-names = "hsi2c";
 393                         status = "disabled";
 394                 };
 395
 396                 hsi2c_6: hsi2c@14e00000 {
 397                         compatible = "samsung,exynos7-hsi2c";
 398                         reg = <0x14e00000 0x1000>;
 399                         interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         pinctrl-names = "default";
 403                         pinctrl-0 = <&hs_i2c6_bus>;
 404                         clocks = <&clock_peric1 PCLK_HSI2C6>;
 405                         clock-names = "hsi2c";
 406                         status = "disabled";
 407                 };
 408
 409                 hsi2c_7: hsi2c@13e10000 {
 410                         compatible = "samsung,exynos7-hsi2c";
 411                         reg = <0x13e10000 0x1000>;
 412                         interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         pinctrl-names = "default";
 416                         pinctrl-0 = <&hs_i2c7_bus>;
 417                         clocks = <&clock_peric1 PCLK_HSI2C7>;
 418                         clock-names = "hsi2c";
 419                         status = "disabled";
 420                 };
 421
 422                 hsi2c_8: hsi2c@14e20000 {
 423                         compatible = "samsung,exynos7-hsi2c";
 424                         reg = <0x14e20000 0x1000>;
 425                         interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         pinctrl-names = "default";
 429                         pinctrl-0 = <&hs_i2c8_bus>;
 430                         clocks = <&clock_peric1 PCLK_HSI2C8>;
 431                         clock-names = "hsi2c";
 432                         status = "disabled";
 433                 };
 434
 435                 hsi2c_9: hsi2c@13680000 {
 436                         compatible = "samsung,exynos7-hsi2c";
 437                         reg = <0x13680000 0x1000>;
 438                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         pinctrl-names = "default";
 442                         pinctrl-0 = <&hs_i2c9_bus>;
 443                         clocks = <&clock_peric0 PCLK_HSI2C9>;
 444                         clock-names = "hsi2c";
 445                         status = "disabled";
 446                 };
 447
 448                 hsi2c_10: hsi2c@13690000 {
 449                         compatible = "samsung,exynos7-hsi2c";
 450                         reg = <0x13690000 0x1000>;
 451                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         pinctrl-names = "default";
 455                         pinctrl-0 = <&hs_i2c10_bus>;
 456                         clocks = <&clock_peric0 PCLK_HSI2C10>;
 457                         clock-names = "hsi2c";
 458                         status = "disabled";
 459                 };
 460
 461                 hsi2c_11: hsi2c@136a0000 {
 462                         compatible = "samsung,exynos7-hsi2c";
 463                         reg = <0x136a0000 0x1000>;
 464                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         pinctrl-names = "default";
 468                         pinctrl-0 = <&hs_i2c11_bus>;
 469                         clocks = <&clock_peric0 PCLK_HSI2C11>;
 470                         clock-names = "hsi2c";
 471                         status = "disabled";
 472                 };
 473
 474                 arm-pmu {
 475                         compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
 476                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 477                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 478                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 479                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 480                         interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
 481                                              <&cpu_atlas2>, <&cpu_atlas3>;
 482                 };
 483
 484                 timer {
 485                         compatible = "arm,armv8-timer";
 486                         interrupts = <GIC_PPI 13
 487                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 488                                      <GIC_PPI 14
 489                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 490                                      <GIC_PPI 11
 491                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 492                                      <GIC_PPI 10
 493                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 494                 };
 495
 496                 pmu_system_controller: system-controller@105c0000 {
 497                         compatible = "samsung,exynos7-pmu", "syscon";
 498                         reg = <0x105c0000 0x5000>;
 499                 };
 500
 501                 rtc: rtc@10590000 {
 502                         compatible = "samsung,s3c6410-rtc";
 503                         reg = <0x10590000 0x100>;
 504                         interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&clock_ccore PCLK_RTC>;
 507                         clock-names = "rtc";
 508                         status = "disabled";
 509                 };
 510
 511                 watchdog: watchdog@101d0000 {
 512                         compatible = "samsung,exynos7-wdt";
 513                         reg = <0x101d0000 0x100>;
 514                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 515                         clocks = <&clock_peris PCLK_WDT>;
 516                         clock-names = "watchdog";
 517                         samsung,syscon-phandle = <&pmu_system_controller>;
 518                         status = "disabled";
 519                 };
 520
 521                 mmc_0: mmc@15740000 {
 522                         compatible = "samsung,exynos7-dw-mshc-smu";
 523                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         reg = <0x15740000 0x2000>;
 527                         clocks = <&clock_fsys1 ACLK_MMC0>,
 528                                  <&clock_top1 CLK_SCLK_MMC0>;
 529                         clock-names = "biu", "ciu";
 530                         fifo-depth = <0x40>;
 531                         status = "disabled";
 532                 };
 533
 534                 mmc_1: mmc@15750000 {
 535                         compatible = "samsung,exynos7-dw-mshc";
 536                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                         reg = <0x15750000 0x2000>;
 540                         clocks = <&clock_fsys1 ACLK_MMC1>,
 541                                  <&clock_top1 CLK_SCLK_MMC1>;
 542                         clock-names = "biu", "ciu";
 543                         fifo-depth = <0x40>;
 544                         status = "disabled";
 545                 };
 546
 547                 mmc_2: mmc@15560000 {
 548                         compatible = "samsung,exynos7-dw-mshc-smu";
 549                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         reg = <0x15560000 0x2000>;
 553                         clocks = <&clock_fsys0 ACLK_MMC2>,
 554                                  <&clock_top1 CLK_SCLK_MMC2>;
 555                         clock-names = "biu", "ciu";
 556                         fifo-depth = <0x40>;
 557                         status = "disabled";
 558                 };
 559
 560                 adc: adc@13620000 {
 561                         compatible = "samsung,exynos7-adc";
 562                         reg = <0x13620000 0x100>;
 563                         interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&clock_peric0 PCLK_ADCIF>;
 565                         clock-names = "adc";
 566                         #io-channel-cells = <1>;
 567                         io-channel-ranges;
 568                         status = "disabled";
 569                 };
 570
 571                 pwm: pwm@136c0000 {
 572                         compatible = "samsung,exynos4210-pwm";
 573                         reg = <0x136c0000 0x100>;
 574                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 575                         #pwm-cells = <3>;
 576                         clocks = <&clock_peric0 PCLK_PWM>;
 577                         clock-names = "timers";
 578                 };
 579
 580                 tmuctrl_0: tmu@10060000 {
 581                         compatible = "samsung,exynos7-tmu";
 582                         reg = <0x10060000 0x200>;
 583                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 584                         clocks = <&clock_peris PCLK_TMU>,
 585                                  <&clock_peris SCLK_TMU>;
 586                         clock-names = "tmu_apbif", "tmu_sclk";
 587                         #thermal-sensor-cells = <0>;
 588                 };
 589
 590                 thermal-zones {
 591                         atlas_thermal: cluster0-thermal {
 592                                 polling-delay-passive = <0>; /* milliseconds */
 593                                 polling-delay = <0>; /* milliseconds */
 594                                 thermal-sensors = <&tmuctrl_0>;
 595                                 #include "exynos7-trip-points.dtsi"
 596                         };
 597                 };
 598
 599                 usbdrd_phy: phy@15500000 {
 600                         compatible = "samsung,exynos7-usbdrd-phy";
 601                         reg = <0x15500000 0x100>;
 602                         clocks = <&clock_fsys0 ACLK_USBDRD300>,
 603                                <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
 604                                <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
 605                                <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
 606                                <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
 607                         clock-names = "phy", "ref", "phy_pipe",
 608                                 "phy_utmi", "itp";
 609                         samsung,pmu-syscon = <&pmu_system_controller>;
 610                         #phy-cells = <1>;
 611                 };
 612
 613                 usbdrd3 {
 614                         compatible = "samsung,exynos7-dwusb3";
 615                         clocks = <&clock_fsys0 ACLK_USBDRD300>,
 616                                <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
 617                                <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
 618                         clock-names = "usbdrd30", "usbdrd30_susp_clk",
 619                                 "usbdrd30_axius_clk";
 620                         #address-cells = <1>;
 621                         #size-cells = <1>;
 622                         ranges;
 623
 624                         dwc3@15400000 {
 625                                 compatible = "snps,dwc3";
 626                                 reg = <0x15400000 0x10000>;
 627                                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 628                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 629                                 phy-names = "usb2-phy", "usb3-phy";
 630                         };
 631                 };
 632         };
 633 };
 634
 635 #include "exynos7-pinctrl.dtsi"
 636 #include "arm/exynos-syscon-restart.dtsi"