arch/arm64/boot/dts/exynos/exynos7.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS7 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 #include <dt-bindings/clock/exynos7-clk.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "samsung,exynos7";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 pinctrl0 = &pinctrl_alive;
  20                 pinctrl1 = &pinctrl_bus0;
  21                 pinctrl2 = &pinctrl_nfc;
  22                 pinctrl3 = &pinctrl_touch;
  23                 pinctrl4 = &pinctrl_ff;
  24                 pinctrl5 = &pinctrl_ese;
  25                 pinctrl6 = &pinctrl_fsys0;
  26                 pinctrl7 = &pinctrl_fsys1;
  27                 pinctrl8 = &pinctrl_bus1;
  28                 tmuctrl0 = &tmuctrl_0;
  29         };
  30
  31         arm-pmu {
  32                 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
  33                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  34                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  35                              <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  36                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  37                 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
  38                                      <&cpu_atlas2>, <&cpu_atlas3>;
  39         };
  40
  41         fin_pll: clock {
  42                 /* XXTI */
  43                 compatible = "fixed-clock";
  44                 clock-output-names = "fin_pll";
  45                 #clock-cells = <0>;
  46         };
  47
  48         cpus {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 cpu_atlas0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a57";
  55                         reg = <0x0>;
  56                         enable-method = "psci";
  57                 };
  58
  59                 cpu_atlas1: cpu@1 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a57";
  62                         reg = <0x1>;
  63                         enable-method = "psci";
  64                 };
  65
  66                 cpu_atlas2: cpu@2 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a57";
  69                         reg = <0x2>;
  70                         enable-method = "psci";
  71                 };
  72
  73                 cpu_atlas3: cpu@3 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a57";
  76                         reg = <0x3>;
  77                         enable-method = "psci";
  78                 };
  79         };
  80
  81         gpu: gpu@14ac0000 {
  82                 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
  83                 reg = <0x14ac0000 0x5000>;
  84                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
  87                 interrupt-names = "job", "mmu", "gpu";
  88                 status = "disabled";
  89                 /* TODO: operating points for DVFS, cooling device */
  90         };
  91
  92         psci {
  93                 compatible = "arm,psci";
  94                 method = "smc";
  95                 cpu_off = <0x84000002>;
  96                 cpu_on = <0xC4000003>;
  97         };
  98
  99         soc: soc {
 100                 compatible = "simple-bus";
 101                 #address-cells = <1>;
 102                 #size-cells = <1>;
 103                 ranges = <0 0 0 0x18000000>;
 104
 105                 chipid@10000000 {
 106                         compatible = "samsung,exynos4210-chipid";
 107                         reg = <0x10000000 0x100>;
 108                 };
 109
 110                 gic: interrupt-controller@11001000 {
 111                         compatible = "arm,gic-400";
 112                         #interrupt-cells = <3>;
 113                         #address-cells = <0>;
 114                         interrupt-controller;
 115                         reg =   <0x11001000 0x1000>,
 116                                 <0x11002000 0x2000>,
 117                                 <0x11004000 0x2000>,
 118                                 <0x11006000 0x2000>;
 119                 };
 120
 121                 amba {
 122                         compatible = "simple-bus";
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         ranges;
 126
 127                         pdma0: pdma@10e10000 {
 128                                 compatible = "arm,pl330", "arm,primecell";
 129                                 reg = <0x10E10000 0x1000>;
 130                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 131                                 clocks = <&clock_fsys0 ACLK_PDMA0>;
 132                                 clock-names = "apb_pclk";
 133                                 #dma-cells = <1>;
 134                                 #dma-channels = <8>;
 135                                 #dma-requests = <32>;
 136                         };
 137
 138                         pdma1: pdma@10eb0000 {
 139                                 compatible = "arm,pl330", "arm,primecell";
 140                                 reg = <0x10EB0000 0x1000>;
 141                                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 142                                 clocks = <&clock_fsys0 ACLK_PDMA1>;
 143                                 clock-names = "apb_pclk";
 144                                 #dma-cells = <1>;
 145                                 #dma-channels = <8>;
 146                                 #dma-requests = <32>;
 147                         };
 148                 };
 149
 150                 clock_topc: clock-controller@10570000 {
 151                         compatible = "samsung,exynos7-clock-topc";
 152                         reg = <0x10570000 0x10000>;
 153                         #clock-cells = <1>;
 154                 };
 155
 156                 clock_top0: clock-controller@105d0000 {
 157                         compatible = "samsung,exynos7-clock-top0";
 158                         reg = <0x105d0000 0xb000>;
 159                         #clock-cells = <1>;
 160                         clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
 161                                  <&clock_topc DOUT_SCLK_BUS1_PLL>,
 162                                  <&clock_topc DOUT_SCLK_CC_PLL>,
 163                                  <&clock_topc DOUT_SCLK_MFC_PLL>;
 164                         clock-names = "fin_pll", "dout_sclk_bus0_pll",
 165                                       "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
 166                                       "dout_sclk_mfc_pll";
 167                 };
 168
 169                 clock_top1: clock-controller@105e0000 {
 170                         compatible = "samsung,exynos7-clock-top1";
 171                         reg = <0x105e0000 0xb000>;
 172                         #clock-cells = <1>;
 173                         clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
 174                                  <&clock_topc DOUT_SCLK_BUS1_PLL>,
 175                                  <&clock_topc DOUT_SCLK_CC_PLL>,
 176                                  <&clock_topc DOUT_SCLK_MFC_PLL>;
 177                         clock-names = "fin_pll", "dout_sclk_bus0_pll",
 178                                       "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
 179                                       "dout_sclk_mfc_pll";
 180                 };
 181
 182                 clock_ccore: clock-controller@105b0000 {
 183                         compatible = "samsung,exynos7-clock-ccore";
 184                         reg = <0x105b0000 0xd00>;
 185                         #clock-cells = <1>;
 186                         clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
 187                         clock-names = "fin_pll", "dout_aclk_ccore_133";
 188                 };
 189
 190                 clock_peric0: clock-controller@13610000 {
 191                         compatible = "samsung,exynos7-clock-peric0";
 192                         reg = <0x13610000 0xd00>;
 193                         #clock-cells = <1>;
 194                         clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
 195                                  <&clock_top0 CLK_SCLK_UART0>;
 196                         clock-names = "fin_pll", "dout_aclk_peric0_66",
 197                                       "sclk_uart0";
 198                 };
 199
 200                 clock_peric1: clock-controller@14c80000 {
 201                         compatible = "samsung,exynos7-clock-peric1";
 202                         reg = <0x14c80000 0xd00>;
 203                         #clock-cells = <1>;
 204                         clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
 205                                  <&clock_top0 CLK_SCLK_UART1>,
 206                                  <&clock_top0 CLK_SCLK_UART2>,
 207                                  <&clock_top0 CLK_SCLK_UART3>;
 208                         clock-names = "fin_pll", "dout_aclk_peric1_66",
 209                                       "sclk_uart1", "sclk_uart2", "sclk_uart3";
 210                 };
 211
 212                 clock_peris: clock-controller@10040000 {
 213                         compatible = "samsung,exynos7-clock-peris";
 214                         reg = <0x10040000 0xd00>;
 215                         #clock-cells = <1>;
 216                         clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
 217                         clock-names = "fin_pll", "dout_aclk_peris_66";
 218                 };
 219
 220                 clock_fsys0: clock-controller@10e90000 {
 221                         compatible = "samsung,exynos7-clock-fsys0";
 222                         reg = <0x10e90000 0xd00>;
 223                         #clock-cells = <1>;
 224                         clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
 225                                  <&clock_top1 DOUT_SCLK_MMC2>;
 226                         clock-names = "fin_pll", "dout_aclk_fsys0_200",
 227                                       "dout_sclk_mmc2";
 228                 };
 229
 230                 clock_fsys1: clock-controller@156e0000 {
 231                         compatible = "samsung,exynos7-clock-fsys1";
 232                         reg = <0x156e0000 0xd00>;
 233                         #clock-cells = <1>;
 234                         clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
 235                                  <&clock_top1 DOUT_SCLK_MMC0>,
 236                                  <&clock_top1 DOUT_SCLK_MMC1>;
 237                         clock-names = "fin_pll", "dout_aclk_fsys1_200",
 238                                       "dout_sclk_mmc0", "dout_sclk_mmc1";
 239                 };
 240
 241                 serial_0: serial@13630000 {
 242                         compatible = "samsung,exynos4210-uart";
 243                         reg = <0x13630000 0x100>;
 244                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&clock_peric0 PCLK_UART0>,
 246                                  <&clock_peric0 SCLK_UART0>;
 247                         clock-names = "uart", "clk_uart_baud0";
 248                         status = "disabled";
 249                 };
 250
 251                 serial_1: serial@14c20000 {
 252                         compatible = "samsung,exynos4210-uart";
 253                         reg = <0x14c20000 0x100>;
 254                         interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
 255                         clocks = <&clock_peric1 PCLK_UART1>,
 256                                  <&clock_peric1 SCLK_UART1>;
 257                         clock-names = "uart", "clk_uart_baud0";
 258                         status = "disabled";
 259                 };
 260
 261                 serial_2: serial@14c30000 {
 262                         compatible = "samsung,exynos4210-uart";
 263                         reg = <0x14c30000 0x100>;
 264                         interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
 265                         clocks = <&clock_peric1 PCLK_UART2>,
 266                                  <&clock_peric1 SCLK_UART2>;
 267                         clock-names = "uart", "clk_uart_baud0";
 268                         status = "disabled";
 269                 };
 270
 271                 serial_3: serial@14c40000 {
 272                         compatible = "samsung,exynos4210-uart";
 273                         reg = <0x14c40000 0x100>;
 274                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&clock_peric1 PCLK_UART3>,
 276                                  <&clock_peric1 SCLK_UART3>;
 277                         clock-names = "uart", "clk_uart_baud0";
 278                         status = "disabled";
 279                 };
 280
 281                 pinctrl_alive: pinctrl@10580000 {
 282                         compatible = "samsung,exynos7-pinctrl";
 283                         reg = <0x10580000 0x1000>;
 284
 285                         wakeup-interrupt-controller {
 286                                 compatible = "samsung,exynos7-wakeup-eint";
 287                                 interrupt-parent = <&gic>;
 288                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 289                         };
 290                 };
 291
 292                 pinctrl_bus0: pinctrl@13470000 {
 293                         compatible = "samsung,exynos7-pinctrl";
 294                         reg = <0x13470000 0x1000>;
 295                         interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
 296                 };
 297
 298                 pinctrl_nfc: pinctrl@14cd0000 {
 299                         compatible = "samsung,exynos7-pinctrl";
 300                         reg = <0x14cd0000 0x1000>;
 301                         interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
 302                 };
 303
 304                 pinctrl_touch: pinctrl@14ce0000 {
 305                         compatible = "samsung,exynos7-pinctrl";
 306                         reg = <0x14ce0000 0x1000>;
 307                         interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
 308                 };
 309
 310                 pinctrl_ff: pinctrl@14c90000 {
 311                         compatible = "samsung,exynos7-pinctrl";
 312                         reg = <0x14c90000 0x1000>;
 313                         interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
 314                 };
 315
 316                 pinctrl_ese: pinctrl@14ca0000 {
 317                         compatible = "samsung,exynos7-pinctrl";
 318                         reg = <0x14ca0000 0x1000>;
 319                         interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
 320                 };
 321
 322                 pinctrl_fsys0: pinctrl@10e60000 {
 323                         compatible = "samsung,exynos7-pinctrl";
 324                         reg = <0x10e60000 0x1000>;
 325                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 326                 };
 327
 328                 pinctrl_fsys1: pinctrl@15690000 {
 329                         compatible = "samsung,exynos7-pinctrl";
 330                         reg = <0x15690000 0x1000>;
 331                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 332                 };
 333
 334                 pinctrl_bus1: pinctrl@14870000 {
 335                         compatible = "samsung,exynos7-pinctrl";
 336                         reg = <0x14870000 0x1000>;
 337                         interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 338                 };
 339
 340                 hsi2c_0: hsi2c@13640000 {
 341                         compatible = "samsung,exynos7-hsi2c";
 342                         reg = <0x13640000 0x1000>;
 343                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         pinctrl-names = "default";
 347                         pinctrl-0 = <&hs_i2c0_bus>;
 348                         clocks = <&clock_peric0 PCLK_HSI2C0>;
 349                         clock-names = "hsi2c";
 350                         status = "disabled";
 351                 };
 352
 353                 hsi2c_1: hsi2c@13650000 {
 354                         compatible = "samsung,exynos7-hsi2c";
 355                         reg = <0x13650000 0x1000>;
 356                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                         pinctrl-names = "default";
 360                         pinctrl-0 = <&hs_i2c1_bus>;
 361                         clocks = <&clock_peric0 PCLK_HSI2C1>;
 362                         clock-names = "hsi2c";
 363                         status = "disabled";
 364                 };
 365
 366                 hsi2c_2: hsi2c@14e60000 {
 367                         compatible = "samsung,exynos7-hsi2c";
 368                         reg = <0x14e60000 0x1000>;
 369                         interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         pinctrl-names = "default";
 373                         pinctrl-0 = <&hs_i2c2_bus>;
 374                         clocks = <&clock_peric1 PCLK_HSI2C2>;
 375                         clock-names = "hsi2c";
 376                         status = "disabled";
 377                 };
 378
 379                 hsi2c_3: hsi2c@14e70000 {
 380                         compatible = "samsung,exynos7-hsi2c";
 381                         reg = <0x14e70000 0x1000>;
 382                         interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         pinctrl-names = "default";
 386                         pinctrl-0 = <&hs_i2c3_bus>;
 387                         clocks = <&clock_peric1 PCLK_HSI2C3>;
 388                         clock-names = "hsi2c";
 389                         status = "disabled";
 390                 };
 391
 392                 hsi2c_4: hsi2c@13660000 {
 393                         compatible = "samsung,exynos7-hsi2c";
 394                         reg = <0x13660000 0x1000>;
 395                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         pinctrl-names = "default";
 399                         pinctrl-0 = <&hs_i2c4_bus>;
 400                         clocks = <&clock_peric0 PCLK_HSI2C4>;
 401                         clock-names = "hsi2c";
 402                         status = "disabled";
 403                 };
 404
 405                 hsi2c_5: hsi2c@13670000 {
 406                         compatible = "samsung,exynos7-hsi2c";
 407                         reg = <0x13670000 0x1000>;
 408                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         pinctrl-names = "default";
 412                         pinctrl-0 = <&hs_i2c5_bus>;
 413                         clocks = <&clock_peric0 PCLK_HSI2C5>;
 414                         clock-names = "hsi2c";
 415                         status = "disabled";
 416                 };
 417
 418                 hsi2c_6: hsi2c@14e00000 {
 419                         compatible = "samsung,exynos7-hsi2c";
 420                         reg = <0x14e00000 0x1000>;
 421                         interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         pinctrl-names = "default";
 425                         pinctrl-0 = <&hs_i2c6_bus>;
 426                         clocks = <&clock_peric1 PCLK_HSI2C6>;
 427                         clock-names = "hsi2c";
 428                         status = "disabled";
 429                 };
 430
 431                 hsi2c_7: hsi2c@13e10000 {
 432                         compatible = "samsung,exynos7-hsi2c";
 433                         reg = <0x13e10000 0x1000>;
 434                         interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         pinctrl-names = "default";
 438                         pinctrl-0 = <&hs_i2c7_bus>;
 439                         clocks = <&clock_peric1 PCLK_HSI2C7>;
 440                         clock-names = "hsi2c";
 441                         status = "disabled";
 442                 };
 443
 444                 hsi2c_8: hsi2c@14e20000 {
 445                         compatible = "samsung,exynos7-hsi2c";
 446                         reg = <0x14e20000 0x1000>;
 447                         interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         pinctrl-names = "default";
 451                         pinctrl-0 = <&hs_i2c8_bus>;
 452                         clocks = <&clock_peric1 PCLK_HSI2C8>;
 453                         clock-names = "hsi2c";
 454                         status = "disabled";
 455                 };
 456
 457                 hsi2c_9: hsi2c@13680000 {
 458                         compatible = "samsung,exynos7-hsi2c";
 459                         reg = <0x13680000 0x1000>;
 460                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         pinctrl-names = "default";
 464                         pinctrl-0 = <&hs_i2c9_bus>;
 465                         clocks = <&clock_peric0 PCLK_HSI2C9>;
 466                         clock-names = "hsi2c";
 467                         status = "disabled";
 468                 };
 469
 470                 hsi2c_10: hsi2c@13690000 {
 471                         compatible = "samsung,exynos7-hsi2c";
 472                         reg = <0x13690000 0x1000>;
 473                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         pinctrl-names = "default";
 477                         pinctrl-0 = <&hs_i2c10_bus>;
 478                         clocks = <&clock_peric0 PCLK_HSI2C10>;
 479                         clock-names = "hsi2c";
 480                         status = "disabled";
 481                 };
 482
 483                 hsi2c_11: hsi2c@136a0000 {
 484                         compatible = "samsung,exynos7-hsi2c";
 485                         reg = <0x136a0000 0x1000>;
 486                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
 487                         #address-cells = <1>;
 488                         #size-cells = <0>;
 489                         pinctrl-names = "default";
 490                         pinctrl-0 = <&hs_i2c11_bus>;
 491                         clocks = <&clock_peric0 PCLK_HSI2C11>;
 492                         clock-names = "hsi2c";
 493                         status = "disabled";
 494                 };
 495
 496                 pmu_system_controller: system-controller@105c0000 {
 497                         compatible = "samsung,exynos7-pmu", "syscon";
 498                         reg = <0x105c0000 0x5000>;
 499                 };
 500
 501                 rtc: rtc@10590000 {
 502                         compatible = "samsung,s3c6410-rtc";
 503                         reg = <0x10590000 0x100>;
 504                         interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&clock_ccore PCLK_RTC>;
 507                         clock-names = "rtc";
 508                         status = "disabled";
 509                 };
 510
 511                 watchdog: watchdog@101d0000 {
 512                         compatible = "samsung,exynos7-wdt";
 513                         reg = <0x101d0000 0x100>;
 514                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 515                         clocks = <&clock_peris PCLK_WDT>;
 516                         clock-names = "watchdog";
 517                         samsung,syscon-phandle = <&pmu_system_controller>;
 518                         status = "disabled";
 519                 };
 520
 521                 mmc_0: mmc@15740000 {
 522                         compatible = "samsung,exynos7-dw-mshc-smu";
 523                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         reg = <0x15740000 0x2000>;
 527                         clocks = <&clock_fsys1 ACLK_MMC0>,
 528                                  <&clock_top1 CLK_SCLK_MMC0>;
 529                         clock-names = "biu", "ciu";
 530                         fifo-depth = <0x40>;
 531                         status = "disabled";
 532                 };
 533
 534                 mmc_1: mmc@15750000 {
 535                         compatible = "samsung,exynos7-dw-mshc";
 536                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                         reg = <0x15750000 0x2000>;
 540                         clocks = <&clock_fsys1 ACLK_MMC1>,
 541                                  <&clock_top1 CLK_SCLK_MMC1>;
 542                         clock-names = "biu", "ciu";
 543                         fifo-depth = <0x40>;
 544                         status = "disabled";
 545                 };
 546
 547                 mmc_2: mmc@15560000 {
 548                         compatible = "samsung,exynos7-dw-mshc-smu";
 549                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         reg = <0x15560000 0x2000>;
 553                         clocks = <&clock_fsys0 ACLK_MMC2>,
 554                                  <&clock_top1 CLK_SCLK_MMC2>;
 555                         clock-names = "biu", "ciu";
 556                         fifo-depth = <0x40>;
 557                         status = "disabled";
 558                 };
 559
 560                 adc: adc@13620000 {
 561                         compatible = "samsung,exynos7-adc";
 562                         reg = <0x13620000 0x100>;
 563                         interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&clock_peric0 PCLK_ADCIF>;
 565                         clock-names = "adc";
 566                         #io-channel-cells = <1>;
 567                         io-channel-ranges;
 568                         status = "disabled";
 569                 };
 570
 571                 pwm: pwm@136c0000 {
 572                         compatible = "samsung,exynos4210-pwm";
 573                         reg = <0x136c0000 0x100>;
 574                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 575                         #pwm-cells = <3>;
 576                         clocks = <&clock_peric0 PCLK_PWM>;
 577                         clock-names = "timers";
 578                 };
 579
 580                 tmuctrl_0: tmu@10060000 {
 581                         compatible = "samsung,exynos7-tmu";
 582                         reg = <0x10060000 0x200>;
 583                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 584                         clocks = <&clock_peris PCLK_TMU>,
 585                                  <&clock_peris SCLK_TMU>;
 586                         clock-names = "tmu_apbif", "tmu_sclk";
 587                         #thermal-sensor-cells = <0>;
 588                 };
 589
 590                 thermal-zones {
 591                         atlas_thermal: cluster0-thermal {
 592                                 polling-delay-passive = <0>; /* milliseconds */
 593                                 polling-delay = <0>; /* milliseconds */
 594                                 thermal-sensors = <&tmuctrl_0>;
 595                                 #include "exynos7-trip-points.dtsi"
 596                         };
 597                 };
 598
 599                 usbdrd_phy: phy@15500000 {
 600                         compatible = "samsung,exynos7-usbdrd-phy";
 601                         reg = <0x15500000 0x100>;
 602                         clocks = <&clock_fsys0 ACLK_USBDRD300>,
 603                                <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
 604                                <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
 605                                <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
 606                                <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
 607                         clock-names = "phy", "ref", "phy_pipe",
 608                                 "phy_utmi", "itp";
 609                         samsung,pmu-syscon = <&pmu_system_controller>;
 610                         #phy-cells = <1>;
 611                 };
 612
 613                 usbdrd3 {
 614                         compatible = "samsung,exynos7-dwusb3";
 615                         clocks = <&clock_fsys0 ACLK_USBDRD300>,
 616                                <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
 617                                <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
 618                         clock-names = "usbdrd30", "usbdrd30_susp_clk",
 619                                 "usbdrd30_axius_clk";
 620                         #address-cells = <1>;
 621                         #size-cells = <1>;
 622                         ranges;
 623
 624                         dwc3@15400000 {
 625                                 compatible = "snps,dwc3";
 626                                 reg = <0x15400000 0x10000>;
 627                                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 628                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 629                                 phy-names = "usb2-phy", "usb3-phy";
 630                         };
 631                 };
 632         };
 633
 634         timer {
 635                 compatible = "arm,armv8-timer";
 636                 interrupts = <GIC_PPI 13
 637                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 638                              <GIC_PPI 14
 639                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 640                              <GIC_PPI 11
 641                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 642                              <GIC_PPI 10
 643                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 644         };
 645 };
 646
 647 #include "exynos7-pinctrl.dtsi"
 648 #include "arm/exynos-syscon-restart.dtsi"