arch/arm64/boot/dts/exynos/exynos7.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos7 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 #include <dt-bindings/clock/exynos7-clk.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "samsung,exynos7";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 pinctrl0 = &pinctrl_alive;
  20                 pinctrl1 = &pinctrl_bus0;
  21                 pinctrl2 = &pinctrl_nfc;
  22                 pinctrl3 = &pinctrl_touch;
  23                 pinctrl4 = &pinctrl_ff;
  24                 pinctrl5 = &pinctrl_ese;
  25                 pinctrl6 = &pinctrl_fsys0;
  26                 pinctrl7 = &pinctrl_fsys1;
  27                 pinctrl8 = &pinctrl_bus1;
  28         };
  29
  30         arm-pmu {
  31                 compatible = "arm,cortex-a57-pmu";
  32                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  33                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  34                              <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  35                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  36                 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
  37                                      <&cpu_atlas2>, <&cpu_atlas3>;
  38         };
  39
  40         fin_pll: clock {
  41                 /* XXTI */
  42                 compatible = "fixed-clock";
  43                 clock-output-names = "fin_pll";
  44                 #clock-cells = <0>;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu_atlas0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a57";
  54                         reg = <0x0>;
  55                         enable-method = "psci";
  56                         i-cache-size = <0xc000>;
  57                         i-cache-line-size = <64>;
  58                         i-cache-sets = <256>;
  59                         d-cache-size = <0x8000>;
  60                         d-cache-line-size = <64>;
  61                         d-cache-sets = <256>;
  62                         next-level-cache = <&atlas_l2>;
  63                 };
  64
  65                 cpu_atlas1: cpu@1 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a57";
  68                         reg = <0x1>;
  69                         enable-method = "psci";
  70                         i-cache-size = <0xc000>;
  71                         i-cache-line-size = <64>;
  72                         i-cache-sets = <256>;
  73                         d-cache-size = <0x8000>;
  74                         d-cache-line-size = <64>;
  75                         d-cache-sets = <256>;
  76                         next-level-cache = <&atlas_l2>;
  77                 };
  78
  79                 cpu_atlas2: cpu@2 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a57";
  82                         reg = <0x2>;
  83                         enable-method = "psci";
  84                         i-cache-size = <0xc000>;
  85                         i-cache-line-size = <64>;
  86                         i-cache-sets = <256>;
  87                         d-cache-size = <0x8000>;
  88                         d-cache-line-size = <64>;
  89                         d-cache-sets = <256>;
  90                         next-level-cache = <&atlas_l2>;
  91                 };
  92
  93                 cpu_atlas3: cpu@3 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a57";
  96                         reg = <0x3>;
  97                         enable-method = "psci";
  98                         i-cache-size = <0xc000>;
  99                         i-cache-line-size = <64>;
 100                         i-cache-sets = <256>;
 101                         d-cache-size = <0x8000>;
 102                         d-cache-line-size = <64>;
 103                         d-cache-sets = <256>;
 104                         next-level-cache = <&atlas_l2>;
 105                 };
 106
 107                 atlas_l2: l2-cache0 {
 108                         compatible = "cache";
 109                         cache-level = <2>;
 110                         cache-unified;
 111                         cache-size = <0x200000>;
 112                         cache-line-size = <64>;
 113                         cache-sets = <2048>;
 114                 };
 115         };
 116
 117         psci {
 118                 compatible = "arm,psci";
 119                 method = "smc";
 120                 cpu_off = <0x84000002>;
 121                 cpu_on = <0xc4000003>;
 122         };
 123
 124         soc: soc@0 {
 125                 compatible = "simple-bus";
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 ranges = <0 0 0 0x18000000>;
 129
 130                 chipid@10000000 {
 131                         compatible = "samsung,exynos4210-chipid";
 132                         reg = <0x10000000 0x100>;
 133                 };
 134
 135                 gic: interrupt-controller@11001000 {
 136                         compatible = "arm,gic-400";
 137                         #interrupt-cells = <3>;
 138                         #address-cells = <0>;
 139                         interrupt-controller;
 140                         reg = <0x11001000 0x1000>,
 141                               <0x11002000 0x2000>,
 142                               <0x11004000 0x2000>,
 143                               <0x11006000 0x2000>;
 144                 };
 145
 146                 pdma0: dma-controller@10e10000 {
 147                         compatible = "arm,pl330", "arm,primecell";
 148                         reg = <0x10e10000 0x1000>;
 149                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&clock_fsys0 ACLK_PDMA0>;
 151                         clock-names = "apb_pclk";
 152                         #dma-cells = <1>;
 153                 };
 154
 155                 pdma1: dma-controller@10eb0000 {
 156                         compatible = "arm,pl330", "arm,primecell";
 157                         reg = <0x10eb0000 0x1000>;
 158                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&clock_fsys0 ACLK_PDMA1>;
 160                         clock-names = "apb_pclk";
 161                         #dma-cells = <1>;
 162                 };
 163
 164                 clock_topc: clock-controller@10570000 {
 165                         compatible = "samsung,exynos7-clock-topc";
 166                         reg = <0x10570000 0x10000>;
 167                         #clock-cells = <1>;
 168                 };
 169
 170                 clock_top0: clock-controller@105d0000 {
 171                         compatible = "samsung,exynos7-clock-top0";
 172                         reg = <0x105d0000 0xb000>;
 173                         #clock-cells = <1>;
 174                         clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
 175                                  <&clock_topc DOUT_SCLK_BUS1_PLL>,
 176                                  <&clock_topc DOUT_SCLK_CC_PLL>,
 177                                  <&clock_topc DOUT_SCLK_MFC_PLL>,
 178                                  <&clock_topc DOUT_SCLK_AUD_PLL>;
 179                         clock-names = "fin_pll", "dout_sclk_bus0_pll",
 180                                       "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
 181                                       "dout_sclk_mfc_pll", "dout_sclk_aud_pll";
 182                 };
 183
 184                 clock_top1: clock-controller@105e0000 {
 185                         compatible = "samsung,exynos7-clock-top1";
 186                         reg = <0x105e0000 0xb000>;
 187                         #clock-cells = <1>;
 188                         clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
 189                                  <&clock_topc DOUT_SCLK_BUS1_PLL>,
 190                                  <&clock_topc DOUT_SCLK_CC_PLL>,
 191                                  <&clock_topc DOUT_SCLK_MFC_PLL>;
 192                         clock-names = "fin_pll", "dout_sclk_bus0_pll",
 193                                       "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
 194                                       "dout_sclk_mfc_pll";
 195                 };
 196
 197                 clock_ccore: clock-controller@105b0000 {
 198                         compatible = "samsung,exynos7-clock-ccore";
 199                         reg = <0x105b0000 0xd00>;
 200                         #clock-cells = <1>;
 201                         clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
 202                         clock-names = "fin_pll", "dout_aclk_ccore_133";
 203                 };
 204
 205                 clock_peric0: clock-controller@13610000 {
 206                         compatible = "samsung,exynos7-clock-peric0";
 207                         reg = <0x13610000 0xd00>;
 208                         #clock-cells = <1>;
 209                         clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
 210                                  <&clock_top0 CLK_SCLK_UART0>;
 211                         clock-names = "fin_pll", "dout_aclk_peric0_66",
 212                                       "sclk_uart0";
 213                 };
 214
 215                 clock_peric1: clock-controller@14c80000 {
 216                         compatible = "samsung,exynos7-clock-peric1";
 217                         reg = <0x14c80000 0xd00>;
 218                         #clock-cells = <1>;
 219                         clocks = <&fin_pll>,
 220                                  <&clock_top0 DOUT_ACLK_PERIC1>,
 221                                  <&clock_top0 CLK_SCLK_UART1>,
 222                                  <&clock_top0 CLK_SCLK_UART2>,
 223                                  <&clock_top0 CLK_SCLK_UART3>,
 224                                  <&clock_top0 CLK_SCLK_SPI0>,
 225                                  <&clock_top0 CLK_SCLK_SPI1>,
 226                                  <&clock_top0 CLK_SCLK_SPI2>,
 227                                  <&clock_top0 CLK_SCLK_SPI3>,
 228                                  <&clock_top0 CLK_SCLK_SPI4>,
 229                                  <&clock_top0 CLK_SCLK_I2S1>,
 230                                  <&clock_top0 CLK_SCLK_PCM1>,
 231                                  <&clock_top0 CLK_SCLK_SPDIF>;
 232                         clock-names = "fin_pll",
 233                                       "dout_aclk_peric1_66",
 234                                       "sclk_uart1",
 235                                       "sclk_uart2",
 236                                       "sclk_uart3",
 237                                       "sclk_spi0",
 238                                       "sclk_spi1",
 239                                       "sclk_spi2",
 240                                       "sclk_spi3",
 241                                       "sclk_spi4",
 242                                       "sclk_i2s1",
 243                                       "sclk_pcm1",
 244                                       "sclk_spdif";
 245                 };
 246
 247                 clock_peris: clock-controller@10040000 {
 248                         compatible = "samsung,exynos7-clock-peris";
 249                         reg = <0x10040000 0xd00>;
 250                         #clock-cells = <1>;
 251                         clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
 252                         clock-names = "fin_pll", "dout_aclk_peris_66";
 253                 };
 254
 255                 clock_fsys0: clock-controller@10e90000 {
 256                         compatible = "samsung,exynos7-clock-fsys0";
 257                         reg = <0x10e90000 0xd00>;
 258                         #clock-cells = <1>;
 259                         clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
 260                                  <&clock_top1 DOUT_SCLK_MMC2>;
 261                         clock-names = "fin_pll", "dout_aclk_fsys0_200",
 262                                       "dout_sclk_mmc2";
 263                 };
 264
 265                 clock_fsys1: clock-controller@156e0000 {
 266                         compatible = "samsung,exynos7-clock-fsys1";
 267                         reg = <0x156e0000 0xd00>;
 268                         #clock-cells = <1>;
 269                         clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
 270                                  <&clock_top1 DOUT_SCLK_MMC0>,
 271                                  <&clock_top1 DOUT_SCLK_MMC1>,
 272                                  <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
 273                                  <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
 274                                  <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
 275                         clock-names = "fin_pll", "dout_aclk_fsys1_200",
 276                                       "dout_sclk_mmc0", "dout_sclk_mmc1",
 277                                       "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
 278                                       "dout_sclk_phy_fsys1_26m";
 279                 };
 280
 281                 serial_0: serial@13630000 {
 282                         compatible = "samsung,exynos4210-uart";
 283                         reg = <0x13630000 0x100>;
 284                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 285                         clocks = <&clock_peric0 PCLK_UART0>,
 286                                  <&clock_peric0 SCLK_UART0>;
 287                         clock-names = "uart", "clk_uart_baud0";
 288                         status = "disabled";
 289                 };
 290
 291                 serial_1: serial@14c20000 {
 292                         compatible = "samsung,exynos4210-uart";
 293                         reg = <0x14c20000 0x100>;
 294                         interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
 295                         clocks = <&clock_peric1 PCLK_UART1>,
 296                                  <&clock_peric1 SCLK_UART1>;
 297                         clock-names = "uart", "clk_uart_baud0";
 298                         status = "disabled";
 299                 };
 300
 301                 serial_2: serial@14c30000 {
 302                         compatible = "samsung,exynos4210-uart";
 303                         reg = <0x14c30000 0x100>;
 304                         interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&clock_peric1 PCLK_UART2>,
 306                                  <&clock_peric1 SCLK_UART2>;
 307                         clock-names = "uart", "clk_uart_baud0";
 308                         status = "disabled";
 309                 };
 310
 311                 serial_3: serial@14c40000 {
 312                         compatible = "samsung,exynos4210-uart";
 313                         reg = <0x14c40000 0x100>;
 314                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
 315                         clocks = <&clock_peric1 PCLK_UART3>,
 316                                  <&clock_peric1 SCLK_UART3>;
 317                         clock-names = "uart", "clk_uart_baud0";
 318                         status = "disabled";
 319                 };
 320
 321                 pinctrl_alive: pinctrl@10580000 {
 322                         compatible = "samsung,exynos7-pinctrl";
 323                         reg = <0x10580000 0x1000>;
 324
 325                         wakeup-interrupt-controller {
 326                                 compatible = "samsung,exynos7-wakeup-eint";
 327                                 interrupt-parent = <&gic>;
 328                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 329                         };
 330                 };
 331
 332                 pinctrl_bus0: pinctrl@13470000 {
 333                         compatible = "samsung,exynos7-pinctrl";
 334                         reg = <0x13470000 0x1000>;
 335                         interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
 336                 };
 337
 338                 pinctrl_nfc: pinctrl@14cd0000 {
 339                         compatible = "samsung,exynos7-pinctrl";
 340                         reg = <0x14cd0000 0x1000>;
 341                         interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
 342                 };
 343
 344                 pinctrl_touch: pinctrl@14ce0000 {
 345                         compatible = "samsung,exynos7-pinctrl";
 346                         reg = <0x14ce0000 0x1000>;
 347                         interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
 348                 };
 349
 350                 pinctrl_ff: pinctrl@14c90000 {
 351                         compatible = "samsung,exynos7-pinctrl";
 352                         reg = <0x14c90000 0x1000>;
 353                         interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
 354                 };
 355
 356                 pinctrl_ese: pinctrl@14ca0000 {
 357                         compatible = "samsung,exynos7-pinctrl";
 358                         reg = <0x14ca0000 0x1000>;
 359                         interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
 360                 };
 361
 362                 pinctrl_fsys0: pinctrl@10e60000 {
 363                         compatible = "samsung,exynos7-pinctrl";
 364                         reg = <0x10e60000 0x1000>;
 365                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 366                 };
 367
 368                 pinctrl_fsys1: pinctrl@15690000 {
 369                         compatible = "samsung,exynos7-pinctrl";
 370                         reg = <0x15690000 0x1000>;
 371                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 372                 };
 373
 374                 pinctrl_bus1: pinctrl@14870000 {
 375                         compatible = "samsung,exynos7-pinctrl";
 376                         reg = <0x14870000 0x1000>;
 377                         interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 378                 };
 379
 380                 hsi2c_0: i2c@13640000 {
 381                         compatible = "samsung,exynos7-hsi2c";
 382                         reg = <0x13640000 0x1000>;
 383                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         pinctrl-names = "default";
 387                         pinctrl-0 = <&hs_i2c0_bus>;
 388                         clocks = <&clock_peric0 PCLK_HSI2C0>;
 389                         clock-names = "hsi2c";
 390                         status = "disabled";
 391                 };
 392
 393                 hsi2c_1: i2c@13650000 {
 394                         compatible = "samsung,exynos7-hsi2c";
 395                         reg = <0x13650000 0x1000>;
 396                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         pinctrl-names = "default";
 400                         pinctrl-0 = <&hs_i2c1_bus>;
 401                         clocks = <&clock_peric0 PCLK_HSI2C1>;
 402                         clock-names = "hsi2c";
 403                         status = "disabled";
 404                 };
 405
 406                 hsi2c_2: i2c@14e60000 {
 407                         compatible = "samsung,exynos7-hsi2c";
 408                         reg = <0x14e60000 0x1000>;
 409                         interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         pinctrl-names = "default";
 413                         pinctrl-0 = <&hs_i2c2_bus>;
 414                         clocks = <&clock_peric1 PCLK_HSI2C2>;
 415                         clock-names = "hsi2c";
 416                         status = "disabled";
 417                 };
 418
 419                 hsi2c_3: i2c@14e70000 {
 420                         compatible = "samsung,exynos7-hsi2c";
 421                         reg = <0x14e70000 0x1000>;
 422                         interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425                         pinctrl-names = "default";
 426                         pinctrl-0 = <&hs_i2c3_bus>;
 427                         clocks = <&clock_peric1 PCLK_HSI2C3>;
 428                         clock-names = "hsi2c";
 429                         status = "disabled";
 430                 };
 431
 432                 hsi2c_4: i2c@13660000 {
 433                         compatible = "samsung,exynos7-hsi2c";
 434                         reg = <0x13660000 0x1000>;
 435                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         pinctrl-names = "default";
 439                         pinctrl-0 = <&hs_i2c4_bus>;
 440                         clocks = <&clock_peric0 PCLK_HSI2C4>;
 441                         clock-names = "hsi2c";
 442                         status = "disabled";
 443                 };
 444
 445                 hsi2c_5: i2c@13670000 {
 446                         compatible = "samsung,exynos7-hsi2c";
 447                         reg = <0x13670000 0x1000>;
 448                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         pinctrl-names = "default";
 452                         pinctrl-0 = <&hs_i2c5_bus>;
 453                         clocks = <&clock_peric0 PCLK_HSI2C5>;
 454                         clock-names = "hsi2c";
 455                         status = "disabled";
 456                 };
 457
 458                 hsi2c_6: i2c@14e00000 {
 459                         compatible = "samsung,exynos7-hsi2c";
 460                         reg = <0x14e00000 0x1000>;
 461                         interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         pinctrl-names = "default";
 465                         pinctrl-0 = <&hs_i2c6_bus>;
 466                         clocks = <&clock_peric1 PCLK_HSI2C6>;
 467                         clock-names = "hsi2c";
 468                         status = "disabled";
 469                 };
 470
 471                 hsi2c_7: i2c@13e10000 {
 472                         compatible = "samsung,exynos7-hsi2c";
 473                         reg = <0x13e10000 0x1000>;
 474                         interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                         pinctrl-names = "default";
 478                         pinctrl-0 = <&hs_i2c7_bus>;
 479                         clocks = <&clock_peric1 PCLK_HSI2C7>;
 480                         clock-names = "hsi2c";
 481                         status = "disabled";
 482                 };
 483
 484                 hsi2c_8: i2c@14e20000 {
 485                         compatible = "samsung,exynos7-hsi2c";
 486                         reg = <0x14e20000 0x1000>;
 487                         interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         pinctrl-names = "default";
 491                         pinctrl-0 = <&hs_i2c8_bus>;
 492                         clocks = <&clock_peric1 PCLK_HSI2C8>;
 493                         clock-names = "hsi2c";
 494                         status = "disabled";
 495                 };
 496
 497                 hsi2c_9: i2c@13680000 {
 498                         compatible = "samsung,exynos7-hsi2c";
 499                         reg = <0x13680000 0x1000>;
 500                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         pinctrl-names = "default";
 504                         pinctrl-0 = <&hs_i2c9_bus>;
 505                         clocks = <&clock_peric0 PCLK_HSI2C9>;
 506                         clock-names = "hsi2c";
 507                         status = "disabled";
 508                 };
 509
 510                 hsi2c_10: i2c@13690000 {
 511                         compatible = "samsung,exynos7-hsi2c";
 512                         reg = <0x13690000 0x1000>;
 513                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         pinctrl-names = "default";
 517                         pinctrl-0 = <&hs_i2c10_bus>;
 518                         clocks = <&clock_peric0 PCLK_HSI2C10>;
 519                         clock-names = "hsi2c";
 520                         status = "disabled";
 521                 };
 522
 523                 hsi2c_11: i2c@136a0000 {
 524                         compatible = "samsung,exynos7-hsi2c";
 525                         reg = <0x136a0000 0x1000>;
 526                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         pinctrl-names = "default";
 530                         pinctrl-0 = <&hs_i2c11_bus>;
 531                         clocks = <&clock_peric0 PCLK_HSI2C11>;
 532                         clock-names = "hsi2c";
 533                         status = "disabled";
 534                 };
 535
 536                 pmu_system_controller: system-controller@105c0000 {
 537                         compatible = "samsung,exynos7-pmu", "syscon";
 538                         reg = <0x105c0000 0x5000>;
 539                 };
 540
 541                 rtc: rtc@10590000 {
 542                         compatible = "samsung,s3c6410-rtc";
 543                         reg = <0x10590000 0x100>;
 544                         interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
 545                                      <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 546                         clocks = <&clock_ccore PCLK_RTC>;
 547                         clock-names = "rtc";
 548                         status = "disabled";
 549                 };
 550
 551                 watchdog: watchdog@101d0000 {
 552                         compatible = "samsung,exynos7-wdt";
 553                         reg = <0x101d0000 0x100>;
 554                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&clock_peris PCLK_WDT>;
 556                         clock-names = "watchdog";
 557                         samsung,syscon-phandle = <&pmu_system_controller>;
 558                         status = "disabled";
 559                 };
 560
 561                 gpu: gpu@14ac0000 {
 562                         compatible = "samsung,exynos5433-mali", "arm,mali-t760";
 563                         reg = <0x14ac0000 0x5000>;
 564                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 567                         interrupt-names = "job", "mmu", "gpu";
 568                         status = "disabled";
 569                         /* TODO: operating points for DVFS, cooling device */
 570                 };
 571
 572                 mmc_0: mmc@15740000 {
 573                         compatible = "samsung,exynos7-dw-mshc-smu";
 574                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 575                         #address-cells = <1>;
 576                         #size-cells = <0>;
 577                         reg = <0x15740000 0x2000>;
 578                         clocks = <&clock_fsys1 ACLK_MMC0>,
 579                                  <&clock_top1 CLK_SCLK_MMC0>;
 580                         clock-names = "biu", "ciu";
 581                         fifo-depth = <0x40>;
 582                         status = "disabled";
 583                 };
 584
 585                 mmc_1: mmc@15750000 {
 586                         compatible = "samsung,exynos7-dw-mshc";
 587                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                         reg = <0x15750000 0x2000>;
 591                         clocks = <&clock_fsys1 ACLK_MMC1>,
 592                                  <&clock_top1 CLK_SCLK_MMC1>;
 593                         clock-names = "biu", "ciu";
 594                         fifo-depth = <0x40>;
 595                         status = "disabled";
 596                 };
 597
 598                 mmc_2: mmc@15560000 {
 599                         compatible = "samsung,exynos7-dw-mshc-smu";
 600                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                         reg = <0x15560000 0x2000>;
 604                         clocks = <&clock_fsys0 ACLK_MMC2>,
 605                                  <&clock_top1 CLK_SCLK_MMC2>;
 606                         clock-names = "biu", "ciu";
 607                         fifo-depth = <0x40>;
 608                         status = "disabled";
 609                 };
 610
 611                 adc: adc@13620000 {
 612                         compatible = "samsung,exynos7-adc";
 613                         reg = <0x13620000 0x100>;
 614                         interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
 615                         clocks = <&clock_peric0 PCLK_ADCIF>;
 616                         clock-names = "adc";
 617                         #io-channel-cells = <1>;
 618                         status = "disabled";
 619                 };
 620
 621                 pwm: pwm@136c0000 {
 622                         compatible = "samsung,exynos4210-pwm";
 623                         reg = <0x136c0000 0x100>;
 624                         interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
 625                                      <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
 626                                      <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
 627                                      <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
 628                                      <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
 629                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 630                         #pwm-cells = <3>;
 631                         clocks = <&clock_peric0 PCLK_PWM>;
 632                         clock-names = "timers";
 633                 };
 634
 635                 tmuctrl_0: tmu@10060000 {
 636                         compatible = "samsung,exynos7-tmu";
 637                         reg = <0x10060000 0x200>;
 638                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 639                         clocks = <&clock_peris PCLK_TMU>,
 640                                  <&clock_peris SCLK_TMU>;
 641                         clock-names = "tmu_apbif", "tmu_sclk";
 642                         #thermal-sensor-cells = <0>;
 643                 };
 644
 645                 ufs: ufs@15570000 {
 646                         compatible = "samsung,exynos7-ufs";
 647                         reg = <0x15570000 0x100>,  /* 0: HCI standard */
 648                                 <0x15570100 0x100>,  /* 1: Vendor specificed */
 649                                 <0x15571000 0x200>,  /* 2: UNIPRO */
 650                                 <0x15572000 0x300>;  /* 3: UFS protector */
 651                         reg-names = "hci", "vs_hci", "unipro", "ufsp";
 652                         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 653                         clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
 654                                 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
 655                         clock-names = "core_clk", "sclk_unipro_main";
 656                         freq-table-hz = <0 0>, <0 0>;
 657                         pinctrl-names = "default";
 658                         pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
 659                         phys = <&ufs_phy>;
 660                         phy-names = "ufs-phy";
 661                         status = "disabled";
 662                 };
 663
 664                 ufs_phy: ufs-phy@15571800 {
 665                         compatible = "samsung,exynos7-ufs-phy";
 666                         reg = <0x15571800 0x240>;
 667                         reg-names = "phy-pma";
 668                         samsung,pmu-syscon = <&pmu_system_controller>;
 669                         #phy-cells = <0>;
 670                         clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
 671                                  <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
 672                                  <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
 673                                  <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
 674                         clock-names = "ref_clk", "rx1_symbol_clk",
 675                                       "rx0_symbol_clk",
 676                                       "tx0_symbol_clk";
 677                 };
 678
 679                 usbdrd_phy: phy@15500000 {
 680                         compatible = "samsung,exynos7-usbdrd-phy";
 681                         reg = <0x15500000 0x100>;
 682                         clocks = <&clock_fsys0 ACLK_USBDRD300>,
 683                                <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
 684                                <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
 685                                <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
 686                                <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
 687                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
 688                         samsung,pmu-syscon = <&pmu_system_controller>;
 689                         #phy-cells = <1>;
 690                 };
 691
 692                 usbdrd: usb@15400000 {
 693                         compatible = "samsung,exynos7-dwusb3";
 694                         clocks = <&clock_fsys0 ACLK_USBDRD300>,
 695                                <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
 696                                <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
 697                         clock-names = "usbdrd30", "usbdrd30_susp_clk",
 698                                 "usbdrd30_axius_clk";
 699                         #address-cells = <1>;
 700                         #size-cells = <1>;
 701                         ranges = <0x0 0x15400000 0x10000>;
 702
 703                         usb@0 {
 704                                 compatible = "snps,dwc3";
 705                                 reg = <0x0 0x10000>;
 706                                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 707                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 708                                 phy-names = "usb2-phy", "usb3-phy";
 709                         };
 710                 };
 711         };
 712
 713         thermal-zones {
 714                 atlas_thermal: cluster0-thermal {
 715                         polling-delay-passive = <0>; /* milliseconds */
 716                         polling-delay = <0>; /* milliseconds */
 717                         thermal-sensors = <&tmuctrl_0>;
 718                         #include "exynos7-trip-points.dtsi"
 719                 };
 720         };
 721
 722         timer {
 723                 compatible = "arm,armv8-timer";
 724                 interrupts = <GIC_PPI 13
 725                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 726                              <GIC_PPI 14
 727                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 728                              <GIC_PPI 11
 729                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 730                              <GIC_PPI 10
 731                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 732         };
 733 };
 734
 735 #include "exynos7-pinctrl.dtsi"
 736 #include "arm/samsung/exynos-syscon-restart.dtsi"