2 * SAMSUNG EXYNOS7 SoC device tree source
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <dt-bindings/clock/exynos7-clk.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 compatible = "samsung,exynos7";
17 interrupt-parent = <&gic>;
22 pinctrl0 = &pinctrl_alive;
23 pinctrl1 = &pinctrl_bus0;
24 pinctrl2 = &pinctrl_nfc;
25 pinctrl3 = &pinctrl_touch;
26 pinctrl4 = &pinctrl_ff;
27 pinctrl5 = &pinctrl_ese;
28 pinctrl6 = &pinctrl_fsys0;
29 pinctrl7 = &pinctrl_fsys1;
30 pinctrl8 = &pinctrl_bus1;
31 tmuctrl0 = &tmuctrl_0;
40 compatible = "arm,cortex-a57", "arm,armv8";
42 enable-method = "psci";
47 compatible = "arm,cortex-a57", "arm,armv8";
49 enable-method = "psci";
54 compatible = "arm,cortex-a57", "arm,armv8";
56 enable-method = "psci";
61 compatible = "arm,cortex-a57", "arm,armv8";
63 enable-method = "psci";
68 compatible = "arm,psci";
70 cpu_off = <0x84000002>;
71 cpu_on = <0xC4000003>;
75 compatible = "simple-bus";
78 ranges = <0 0 0 0x18000000>;
81 compatible = "samsung,exynos4210-chipid";
82 reg = <0x10000000 0x100>;
86 compatible = "fixed-clock";
87 clock-output-names = "fin_pll";
91 gic: interrupt-controller@11001000 {
92 compatible = "arm,gic-400";
93 #interrupt-cells = <3>;
96 reg = <0x11001000 0x1000>,
103 compatible = "simple-bus";
104 #address-cells = <1>;
108 pdma0: pdma@10E10000 {
109 compatible = "arm,pl330", "arm,primecell";
110 reg = <0x10E10000 0x1000>;
111 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clock_fsys0 ACLK_PDMA0>;
113 clock-names = "apb_pclk";
116 #dma-requests = <32>;
119 pdma1: pdma@10EB0000 {
120 compatible = "arm,pl330", "arm,primecell";
121 reg = <0x10EB0000 0x1000>;
122 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&clock_fsys0 ACLK_PDMA1>;
124 clock-names = "apb_pclk";
127 #dma-requests = <32>;
131 clock_topc: clock-controller@10570000 {
132 compatible = "samsung,exynos7-clock-topc";
133 reg = <0x10570000 0x10000>;
137 clock_top0: clock-controller@105d0000 {
138 compatible = "samsung,exynos7-clock-top0";
139 reg = <0x105d0000 0xb000>;
141 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
142 <&clock_topc DOUT_SCLK_BUS1_PLL>,
143 <&clock_topc DOUT_SCLK_CC_PLL>,
144 <&clock_topc DOUT_SCLK_MFC_PLL>;
145 clock-names = "fin_pll", "dout_sclk_bus0_pll",
146 "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
150 clock_top1: clock-controller@105e0000 {
151 compatible = "samsung,exynos7-clock-top1";
152 reg = <0x105e0000 0xb000>;
154 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
155 <&clock_topc DOUT_SCLK_BUS1_PLL>,
156 <&clock_topc DOUT_SCLK_CC_PLL>,
157 <&clock_topc DOUT_SCLK_MFC_PLL>;
158 clock-names = "fin_pll", "dout_sclk_bus0_pll",
159 "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
163 clock_ccore: clock-controller@105b0000 {
164 compatible = "samsung,exynos7-clock-ccore";
165 reg = <0x105b0000 0xd00>;
167 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
168 clock-names = "fin_pll", "dout_aclk_ccore_133";
171 clock_peric0: clock-controller@13610000 {
172 compatible = "samsung,exynos7-clock-peric0";
173 reg = <0x13610000 0xd00>;
175 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
176 <&clock_top0 CLK_SCLK_UART0>;
177 clock-names = "fin_pll", "dout_aclk_peric0_66",
181 clock_peric1: clock-controller@14c80000 {
182 compatible = "samsung,exynos7-clock-peric1";
183 reg = <0x14c80000 0xd00>;
185 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
186 <&clock_top0 CLK_SCLK_UART1>,
187 <&clock_top0 CLK_SCLK_UART2>,
188 <&clock_top0 CLK_SCLK_UART3>;
189 clock-names = "fin_pll", "dout_aclk_peric1_66",
190 "sclk_uart1", "sclk_uart2", "sclk_uart3";
193 clock_peris: clock-controller@10040000 {
194 compatible = "samsung,exynos7-clock-peris";
195 reg = <0x10040000 0xd00>;
197 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
198 clock-names = "fin_pll", "dout_aclk_peris_66";
201 clock_fsys0: clock-controller@10e90000 {
202 compatible = "samsung,exynos7-clock-fsys0";
203 reg = <0x10e90000 0xd00>;
205 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
206 <&clock_top1 DOUT_SCLK_MMC2>;
207 clock-names = "fin_pll", "dout_aclk_fsys0_200",
211 clock_fsys1: clock-controller@156e0000 {
212 compatible = "samsung,exynos7-clock-fsys1";
213 reg = <0x156e0000 0xd00>;
215 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
216 <&clock_top1 DOUT_SCLK_MMC0>,
217 <&clock_top1 DOUT_SCLK_MMC1>;
218 clock-names = "fin_pll", "dout_aclk_fsys1_200",
219 "dout_sclk_mmc0", "dout_sclk_mmc1";
222 serial_0: serial@13630000 {
223 compatible = "samsung,exynos4210-uart";
224 reg = <0x13630000 0x100>;
225 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clock_peric0 PCLK_UART0>,
227 <&clock_peric0 SCLK_UART0>;
228 clock-names = "uart", "clk_uart_baud0";
232 serial_1: serial@14c20000 {
233 compatible = "samsung,exynos4210-uart";
234 reg = <0x14c20000 0x100>;
235 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clock_peric1 PCLK_UART1>,
237 <&clock_peric1 SCLK_UART1>;
238 clock-names = "uart", "clk_uart_baud0";
242 serial_2: serial@14c30000 {
243 compatible = "samsung,exynos4210-uart";
244 reg = <0x14c30000 0x100>;
245 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clock_peric1 PCLK_UART2>,
247 <&clock_peric1 SCLK_UART2>;
248 clock-names = "uart", "clk_uart_baud0";
252 serial_3: serial@14c40000 {
253 compatible = "samsung,exynos4210-uart";
254 reg = <0x14c40000 0x100>;
255 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&clock_peric1 PCLK_UART3>,
257 <&clock_peric1 SCLK_UART3>;
258 clock-names = "uart", "clk_uart_baud0";
262 pinctrl_alive: pinctrl@10580000 {
263 compatible = "samsung,exynos7-pinctrl";
264 reg = <0x10580000 0x1000>;
266 wakeup-interrupt-controller {
267 compatible = "samsung,exynos7-wakeup-eint";
268 interrupt-parent = <&gic>;
269 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
273 pinctrl_bus0: pinctrl@13470000 {
274 compatible = "samsung,exynos7-pinctrl";
275 reg = <0x13470000 0x1000>;
276 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
279 pinctrl_nfc: pinctrl@14cd0000 {
280 compatible = "samsung,exynos7-pinctrl";
281 reg = <0x14cd0000 0x1000>;
282 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
285 pinctrl_touch: pinctrl@14ce0000 {
286 compatible = "samsung,exynos7-pinctrl";
287 reg = <0x14ce0000 0x1000>;
288 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
291 pinctrl_ff: pinctrl@14c90000 {
292 compatible = "samsung,exynos7-pinctrl";
293 reg = <0x14c90000 0x1000>;
294 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl_ese: pinctrl@14ca0000 {
298 compatible = "samsung,exynos7-pinctrl";
299 reg = <0x14ca0000 0x1000>;
300 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
303 pinctrl_fsys0: pinctrl@10e60000 {
304 compatible = "samsung,exynos7-pinctrl";
305 reg = <0x10e60000 0x1000>;
306 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
309 pinctrl_fsys1: pinctrl@15690000 {
310 compatible = "samsung,exynos7-pinctrl";
311 reg = <0x15690000 0x1000>;
312 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
315 pinctrl_bus1: pinctrl@14870000 {
316 compatible = "samsung,exynos7-pinctrl";
317 reg = <0x14870000 0x1000>;
318 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
321 hsi2c_0: hsi2c@13640000 {
322 compatible = "samsung,exynos7-hsi2c";
323 reg = <0x13640000 0x1000>;
324 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&hs_i2c0_bus>;
329 clocks = <&clock_peric0 PCLK_HSI2C0>;
330 clock-names = "hsi2c";
334 hsi2c_1: hsi2c@13650000 {
335 compatible = "samsung,exynos7-hsi2c";
336 reg = <0x13650000 0x1000>;
337 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&hs_i2c1_bus>;
342 clocks = <&clock_peric0 PCLK_HSI2C1>;
343 clock-names = "hsi2c";
347 hsi2c_2: hsi2c@14e60000 {
348 compatible = "samsung,exynos7-hsi2c";
349 reg = <0x14e60000 0x1000>;
350 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&hs_i2c2_bus>;
355 clocks = <&clock_peric1 PCLK_HSI2C2>;
356 clock-names = "hsi2c";
360 hsi2c_3: hsi2c@14e70000 {
361 compatible = "samsung,exynos7-hsi2c";
362 reg = <0x14e70000 0x1000>;
363 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&hs_i2c3_bus>;
368 clocks = <&clock_peric1 PCLK_HSI2C3>;
369 clock-names = "hsi2c";
373 hsi2c_4: hsi2c@13660000 {
374 compatible = "samsung,exynos7-hsi2c";
375 reg = <0x13660000 0x1000>;
376 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&hs_i2c4_bus>;
381 clocks = <&clock_peric0 PCLK_HSI2C4>;
382 clock-names = "hsi2c";
386 hsi2c_5: hsi2c@13670000 {
387 compatible = "samsung,exynos7-hsi2c";
388 reg = <0x13670000 0x1000>;
389 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
390 #address-cells = <1>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&hs_i2c5_bus>;
394 clocks = <&clock_peric0 PCLK_HSI2C5>;
395 clock-names = "hsi2c";
399 hsi2c_6: hsi2c@14e00000 {
400 compatible = "samsung,exynos7-hsi2c";
401 reg = <0x14e00000 0x1000>;
402 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&hs_i2c6_bus>;
407 clocks = <&clock_peric1 PCLK_HSI2C6>;
408 clock-names = "hsi2c";
412 hsi2c_7: hsi2c@13e10000 {
413 compatible = "samsung,exynos7-hsi2c";
414 reg = <0x13e10000 0x1000>;
415 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&hs_i2c7_bus>;
420 clocks = <&clock_peric1 PCLK_HSI2C7>;
421 clock-names = "hsi2c";
425 hsi2c_8: hsi2c@14e20000 {
426 compatible = "samsung,exynos7-hsi2c";
427 reg = <0x14e20000 0x1000>;
428 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
429 #address-cells = <1>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&hs_i2c8_bus>;
433 clocks = <&clock_peric1 PCLK_HSI2C8>;
434 clock-names = "hsi2c";
438 hsi2c_9: hsi2c@13680000 {
439 compatible = "samsung,exynos7-hsi2c";
440 reg = <0x13680000 0x1000>;
441 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&hs_i2c9_bus>;
446 clocks = <&clock_peric0 PCLK_HSI2C9>;
447 clock-names = "hsi2c";
451 hsi2c_10: hsi2c@13690000 {
452 compatible = "samsung,exynos7-hsi2c";
453 reg = <0x13690000 0x1000>;
454 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&hs_i2c10_bus>;
459 clocks = <&clock_peric0 PCLK_HSI2C10>;
460 clock-names = "hsi2c";
464 hsi2c_11: hsi2c@136a0000 {
465 compatible = "samsung,exynos7-hsi2c";
466 reg = <0x136a0000 0x1000>;
467 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
468 #address-cells = <1>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&hs_i2c11_bus>;
472 clocks = <&clock_peric0 PCLK_HSI2C11>;
473 clock-names = "hsi2c";
478 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
479 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
483 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
484 <&cpu_atlas2>, <&cpu_atlas3>;
488 compatible = "arm,armv8-timer";
489 interrupts = <GIC_PPI 13
490 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
492 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
494 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
496 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
499 pmu_system_controller: system-controller@105c0000 {
500 compatible = "samsung,exynos7-pmu", "syscon";
501 reg = <0x105c0000 0x5000>;
504 reboot: syscon-reboot {
505 compatible = "syscon-reboot";
506 regmap = <&pmu_system_controller>;
512 compatible = "samsung,s3c6410-rtc";
513 reg = <0x10590000 0x100>;
514 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clock_ccore PCLK_RTC>;
521 watchdog: watchdog@101d0000 {
522 compatible = "samsung,exynos7-wdt";
523 reg = <0x101d0000 0x100>;
524 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clock_peris PCLK_WDT>;
526 clock-names = "watchdog";
527 samsung,syscon-phandle = <&pmu_system_controller>;
531 mmc_0: mmc@15740000 {
532 compatible = "samsung,exynos7-dw-mshc-smu";
533 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
534 #address-cells = <1>;
536 reg = <0x15740000 0x2000>;
537 clocks = <&clock_fsys1 ACLK_MMC0>,
538 <&clock_top1 CLK_SCLK_MMC0>;
539 clock-names = "biu", "ciu";
544 mmc_1: mmc@15750000 {
545 compatible = "samsung,exynos7-dw-mshc";
546 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <1>;
549 reg = <0x15750000 0x2000>;
550 clocks = <&clock_fsys1 ACLK_MMC1>,
551 <&clock_top1 CLK_SCLK_MMC1>;
552 clock-names = "biu", "ciu";
557 mmc_2: mmc@15560000 {
558 compatible = "samsung,exynos7-dw-mshc-smu";
559 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
562 reg = <0x15560000 0x2000>;
563 clocks = <&clock_fsys0 ACLK_MMC2>,
564 <&clock_top1 CLK_SCLK_MMC2>;
565 clock-names = "biu", "ciu";
571 compatible = "samsung,exynos7-adc";
572 reg = <0x13620000 0x100>;
573 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&clock_peric0 PCLK_ADCIF>;
576 #io-channel-cells = <1>;
582 compatible = "samsung,exynos4210-pwm";
583 reg = <0x136c0000 0x100>;
584 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
586 clocks = <&clock_peric0 PCLK_PWM>;
587 clock-names = "timers";
590 tmuctrl_0: tmu@10060000 {
591 compatible = "samsung,exynos7-tmu";
592 reg = <0x10060000 0x200>;
593 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clock_peris PCLK_TMU>,
595 <&clock_peris SCLK_TMU>;
596 clock-names = "tmu_apbif", "tmu_sclk";
597 #include "exynos7-tmu-sensor-conf.dtsi"
601 atlas_thermal: cluster0-thermal {
602 polling-delay-passive = <0>; /* milliseconds */
603 polling-delay = <0>; /* milliseconds */
604 thermal-sensors = <&tmuctrl_0>;
605 #include "exynos7-trip-points.dtsi"
609 usbdrd_phy: phy@15500000 {
610 compatible = "samsung,exynos7-usbdrd-phy";
611 reg = <0x15500000 0x100>;
612 clocks = <&clock_fsys0 ACLK_USBDRD300>,
613 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
614 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
615 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
616 <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
617 clock-names = "phy", "ref", "phy_pipe",
619 samsung,pmu-syscon = <&pmu_system_controller>;
624 compatible = "samsung,exynos7-dwusb3";
625 clocks = <&clock_fsys0 ACLK_USBDRD300>,
626 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
627 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
628 clock-names = "usbdrd30", "usbdrd30_susp_clk",
629 "usbdrd30_axius_clk";
630 #address-cells = <1>;
635 compatible = "snps,dwc3";
636 reg = <0x15400000 0x10000>;
637 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
638 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
639 phy-names = "usb2-phy", "usb3-phy";
645 #include "exynos7-pinctrl.dtsi"