arch/arm64/boot/dts/exynos/exynos5433.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos5433 SoC device tree source
   4  *
   5  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
   6  *
   7  * Samsung's Exynos5433 SoC device nodes are listed in this file.
   8  * Exynos5433 based board files can include this file and provide
   9  * values for board specific bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
  13  * additional nodes can be added to this file.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5433.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18
  19 / {
  20         compatible = "samsung,exynos5433";
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         interrupt-parent = <&gic>;
  25
  26         arm-a53-pmu {
  27                 compatible = "arm,cortex-a53-pmu";
  28                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  29                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  30                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  31                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  32                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  33         };
  34
  35         arm-a57-pmu {
  36                 compatible = "arm,cortex-a57-pmu";
  37                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  38                              <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  39                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  40                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  41                 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
  42         };
  43
  44         xxti: clock {
  45                 /* XXTI */
  46                 compatible = "fixed-clock";
  47                 clock-output-names = "oscclk";
  48                 #clock-cells = <0>;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu-map {
  56                         cluster0 {
  57                                 core0 {
  58                                         cpu = <&cpu0>;
  59                                 };
  60                                 core1 {
  61                                         cpu = <&cpu1>;
  62                                 };
  63                                 core2 {
  64                                         cpu = <&cpu2>;
  65                                 };
  66                                 core3 {
  67                                         cpu = <&cpu3>;
  68                                 };
  69                         };
  70
  71                         cluster1 {
  72                                 core0 {
  73                                         cpu = <&cpu4>;
  74                                 };
  75                                 core1 {
  76                                         cpu = <&cpu5>;
  77                                 };
  78                                 core2 {
  79                                         cpu = <&cpu6>;
  80                                 };
  81                                 core3 {
  82                                         cpu = <&cpu7>;
  83                                 };
  84                         };
  85                 };
  86
  87                 cpu0: cpu@100 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53";
  90                         enable-method = "psci";
  91                         reg = <0x100>;
  92                         clock-frequency = <1300000000>;
  93                         clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
  94                         clock-names = "apolloclk";
  95                         operating-points-v2 = <&cluster_a53_opp_table>;
  96                         #cooling-cells = <2>;
  97                         i-cache-size = <0x8000>;
  98                         i-cache-line-size = <64>;
  99                         i-cache-sets = <256>;
 100                         d-cache-size = <0x8000>;
 101                         d-cache-line-size = <64>;
 102                         d-cache-sets = <128>;
 103                         next-level-cache = <&cluster_a53_l2>;
 104                 };
 105
 106                 cpu1: cpu@101 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a53";
 109                         enable-method = "psci";
 110                         reg = <0x101>;
 111                         clock-frequency = <1300000000>;
 112                         operating-points-v2 = <&cluster_a53_opp_table>;
 113                         #cooling-cells = <2>;
 114                         i-cache-size = <0x8000>;
 115                         i-cache-line-size = <64>;
 116                         i-cache-sets = <256>;
 117                         d-cache-size = <0x8000>;
 118                         d-cache-line-size = <64>;
 119                         d-cache-sets = <128>;
 120                         next-level-cache = <&cluster_a53_l2>;
 121                 };
 122
 123                 cpu2: cpu@102 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53";
 126                         enable-method = "psci";
 127                         reg = <0x102>;
 128                         clock-frequency = <1300000000>;
 129                         operating-points-v2 = <&cluster_a53_opp_table>;
 130                         #cooling-cells = <2>;
 131                         i-cache-size = <0x8000>;
 132                         i-cache-line-size = <64>;
 133                         i-cache-sets = <256>;
 134                         d-cache-size = <0x8000>;
 135                         d-cache-line-size = <64>;
 136                         d-cache-sets = <128>;
 137                         next-level-cache = <&cluster_a53_l2>;
 138                 };
 139
 140                 cpu3: cpu@103 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a53";
 143                         enable-method = "psci";
 144                         reg = <0x103>;
 145                         clock-frequency = <1300000000>;
 146                         operating-points-v2 = <&cluster_a53_opp_table>;
 147                         #cooling-cells = <2>;
 148                         i-cache-size = <0x8000>;
 149                         i-cache-line-size = <64>;
 150                         i-cache-sets = <256>;
 151                         d-cache-size = <0x8000>;
 152                         d-cache-line-size = <64>;
 153                         d-cache-sets = <128>;
 154                         next-level-cache = <&cluster_a53_l2>;
 155                 };
 156
 157                 cpu4: cpu@0 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a57";
 160                         enable-method = "psci";
 161                         reg = <0x0>;
 162                         clock-frequency = <1900000000>;
 163                         clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
 164                         clock-names = "atlasclk";
 165                         operating-points-v2 = <&cluster_a57_opp_table>;
 166                         #cooling-cells = <2>;
 167                         i-cache-size = <0xc000>;
 168                         i-cache-line-size = <64>;
 169                         i-cache-sets = <256>;
 170                         d-cache-size = <0x8000>;
 171                         d-cache-line-size = <64>;
 172                         d-cache-sets = <256>;
 173                         next-level-cache = <&cluster_a57_l2>;
 174                 };
 175
 176                 cpu5: cpu@1 {
 177                         device_type = "cpu";
 178                         compatible = "arm,cortex-a57";
 179                         enable-method = "psci";
 180                         reg = <0x1>;
 181                         clock-frequency = <1900000000>;
 182                         operating-points-v2 = <&cluster_a57_opp_table>;
 183                         #cooling-cells = <2>;
 184                         i-cache-size = <0xc000>;
 185                         i-cache-line-size = <64>;
 186                         i-cache-sets = <256>;
 187                         d-cache-size = <0x8000>;
 188                         d-cache-line-size = <64>;
 189                         d-cache-sets = <256>;
 190                         next-level-cache = <&cluster_a57_l2>;
 191                 };
 192
 193                 cpu6: cpu@2 {
 194                         device_type = "cpu";
 195                         compatible = "arm,cortex-a57";
 196                         enable-method = "psci";
 197                         reg = <0x2>;
 198                         clock-frequency = <1900000000>;
 199                         operating-points-v2 = <&cluster_a57_opp_table>;
 200                         #cooling-cells = <2>;
 201                         i-cache-size = <0xc000>;
 202                         i-cache-line-size = <64>;
 203                         i-cache-sets = <256>;
 204                         d-cache-size = <0x8000>;
 205                         d-cache-line-size = <64>;
 206                         d-cache-sets = <256>;
 207                         next-level-cache = <&cluster_a57_l2>;
 208                 };
 209
 210                 cpu7: cpu@3 {
 211                         device_type = "cpu";
 212                         compatible = "arm,cortex-a57";
 213                         enable-method = "psci";
 214                         reg = <0x3>;
 215                         clock-frequency = <1900000000>;
 216                         operating-points-v2 = <&cluster_a57_opp_table>;
 217                         #cooling-cells = <2>;
 218                         i-cache-size = <0xc000>;
 219                         i-cache-line-size = <64>;
 220                         i-cache-sets = <256>;
 221                         d-cache-size = <0x8000>;
 222                         d-cache-line-size = <64>;
 223                         d-cache-sets = <256>;
 224                         next-level-cache = <&cluster_a57_l2>;
 225                 };
 226
 227                 cluster_a57_l2: l2-cache0 {
 228                         compatible = "cache";
 229                         cache-size = <0x200000>;
 230                         cache-line-size = <64>;
 231                         cache-sets = <2048>;
 232                 };
 233
 234                 cluster_a53_l2: l2-cache1 {
 235                         compatible = "cache";
 236                         cache-size = <0x40000>;
 237                         cache-line-size = <64>;
 238                         cache-sets = <256>;
 239                 };
 240         };
 241
 242         cluster_a53_opp_table: opp-table-0 {
 243                 compatible = "operating-points-v2";
 244                 opp-shared;
 245
 246                 opp-400000000 {
 247                         opp-hz = /bits/ 64 <400000000>;
 248                         opp-microvolt = <900000>;
 249                 };
 250                 opp-500000000 {
 251                         opp-hz = /bits/ 64 <500000000>;
 252                         opp-microvolt = <925000>;
 253                 };
 254                 opp-600000000 {
 255                         opp-hz = /bits/ 64 <600000000>;
 256                         opp-microvolt = <950000>;
 257                 };
 258                 opp-700000000 {
 259                         opp-hz = /bits/ 64 <700000000>;
 260                         opp-microvolt = <975000>;
 261                 };
 262                 opp-800000000 {
 263                         opp-hz = /bits/ 64 <800000000>;
 264                         opp-microvolt = <1000000>;
 265                 };
 266                 opp-900000000 {
 267                         opp-hz = /bits/ 64 <900000000>;
 268                         opp-microvolt = <1050000>;
 269                 };
 270                 opp-1000000000 {
 271                         opp-hz = /bits/ 64 <1000000000>;
 272                         opp-microvolt = <1075000>;
 273                 };
 274                 opp-1100000000 {
 275                         opp-hz = /bits/ 64 <1100000000>;
 276                         opp-microvolt = <1112500>;
 277                 };
 278                 opp-1200000000 {
 279                         opp-hz = /bits/ 64 <1200000000>;
 280                         opp-microvolt = <1112500>;
 281                 };
 282                 opp-1300000000 {
 283                         opp-hz = /bits/ 64 <1300000000>;
 284                         opp-microvolt = <1150000>;
 285                 };
 286         };
 287
 288         cluster_a57_opp_table: opp-table-1 {
 289                 compatible = "operating-points-v2";
 290                 opp-shared;
 291
 292                 opp-500000000 {
 293                         opp-hz = /bits/ 64 <500000000>;
 294                         opp-microvolt = <900000>;
 295                 };
 296                 opp-600000000 {
 297                         opp-hz = /bits/ 64 <600000000>;
 298                         opp-microvolt = <900000>;
 299                 };
 300                 opp-700000000 {
 301                         opp-hz = /bits/ 64 <700000000>;
 302                         opp-microvolt = <912500>;
 303                 };
 304                 opp-800000000 {
 305                         opp-hz = /bits/ 64 <800000000>;
 306                         opp-microvolt = <912500>;
 307                 };
 308                 opp-900000000 {
 309                         opp-hz = /bits/ 64 <900000000>;
 310                         opp-microvolt = <937500>;
 311                 };
 312                 opp-1000000000 {
 313                         opp-hz = /bits/ 64 <1000000000>;
 314                         opp-microvolt = <975000>;
 315                 };
 316                 opp-1100000000 {
 317                         opp-hz = /bits/ 64 <1100000000>;
 318                         opp-microvolt = <1012500>;
 319                 };
 320                 opp-1200000000 {
 321                         opp-hz = /bits/ 64 <1200000000>;
 322                         opp-microvolt = <1037500>;
 323                 };
 324                 opp-1300000000 {
 325                         opp-hz = /bits/ 64 <1300000000>;
 326                         opp-microvolt = <1062500>;
 327                 };
 328                 opp-1400000000 {
 329                         opp-hz = /bits/ 64 <1400000000>;
 330                         opp-microvolt = <1087500>;
 331                 };
 332                 opp-1500000000 {
 333                         opp-hz = /bits/ 64 <1500000000>;
 334                         opp-microvolt = <1125000>;
 335                 };
 336                 opp-1600000000 {
 337                         opp-hz = /bits/ 64 <1600000000>;
 338                         opp-microvolt = <1137500>;
 339                 };
 340                 opp-1700000000 {
 341                         opp-hz = /bits/ 64 <1700000000>;
 342                         opp-microvolt = <1175000>;
 343                 };
 344                 opp-1800000000 {
 345                         opp-hz = /bits/ 64 <1800000000>;
 346                         opp-microvolt = <1212500>;
 347                 };
 348                 opp-1900000000 {
 349                         opp-hz = /bits/ 64 <1900000000>;
 350                         opp-microvolt = <1262500>;
 351                 };
 352         };
 353
 354         psci {
 355                 compatible = "arm,psci";
 356                 method = "smc";
 357                 cpu_off = <0x84000002>;
 358                 cpu_on = <0xC4000003>;
 359         };
 360
 361         soc: soc@0 {
 362                 compatible = "simple-bus";
 363                 #address-cells = <1>;
 364                 #size-cells = <1>;
 365                 ranges = <0x0 0x0 0x0 0x18000000>;
 366
 367                 chipid@10000000 {
 368                         compatible = "samsung,exynos4210-chipid";
 369                         reg = <0x10000000 0x100>;
 370                 };
 371
 372                 cmu_top: clock-controller@10030000 {
 373                         compatible = "samsung,exynos5433-cmu-top";
 374                         reg = <0x10030000 0x1000>;
 375                         #clock-cells = <1>;
 376
 377                         clock-names = "oscclk",
 378                                 "sclk_mphy_pll",
 379                                 "sclk_mfc_pll",
 380                                 "sclk_bus_pll";
 381                         clocks = <&xxti>,
 382                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
 383                                 <&cmu_mif CLK_SCLK_MFC_PLL>,
 384                                 <&cmu_mif CLK_SCLK_BUS_PLL>;
 385                 };
 386
 387                 cmu_cpif: clock-controller@10fc0000 {
 388                         compatible = "samsung,exynos5433-cmu-cpif";
 389                         reg = <0x10fc0000 0x1000>;
 390                         #clock-cells = <1>;
 391
 392                         clock-names = "oscclk";
 393                         clocks = <&xxti>;
 394                 };
 395
 396                 cmu_mif: clock-controller@105b0000 {
 397                         compatible = "samsung,exynos5433-cmu-mif";
 398                         reg = <0x105b0000 0x2000>;
 399                         #clock-cells = <1>;
 400
 401                         clock-names = "oscclk",
 402                                 "sclk_mphy_pll";
 403                         clocks = <&xxti>,
 404                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
 405                 };
 406
 407                 cmu_peric: clock-controller@14c80000 {
 408                         compatible = "samsung,exynos5433-cmu-peric";
 409                         reg = <0x14c80000 0x1000>;
 410                         #clock-cells = <1>;
 411                 };
 412
 413                 cmu_peris: clock-controller@10040000 {
 414                         compatible = "samsung,exynos5433-cmu-peris";
 415                         reg = <0x10040000 0x1000>;
 416                         #clock-cells = <1>;
 417                 };
 418
 419                 cmu_fsys: clock-controller@156e0000 {
 420                         compatible = "samsung,exynos5433-cmu-fsys";
 421                         reg = <0x156e0000 0x1000>;
 422                         #clock-cells = <1>;
 423
 424                         clock-names = "oscclk",
 425                                 "sclk_ufs_mphy",
 426                                 "aclk_fsys_200",
 427                                 "sclk_pcie_100_fsys",
 428                                 "sclk_ufsunipro_fsys",
 429                                 "sclk_mmc2_fsys",
 430                                 "sclk_mmc1_fsys",
 431                                 "sclk_mmc0_fsys",
 432                                 "sclk_usbhost30_fsys",
 433                                 "sclk_usbdrd30_fsys";
 434                         clocks = <&xxti>,
 435                                 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
 436                                 <&cmu_top CLK_ACLK_FSYS_200>,
 437                                 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 438                                 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 439                                 <&cmu_top CLK_SCLK_MMC2_FSYS>,
 440                                 <&cmu_top CLK_SCLK_MMC1_FSYS>,
 441                                 <&cmu_top CLK_SCLK_MMC0_FSYS>,
 442                                 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 443                                 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
 444                 };
 445
 446                 cmu_g2d: clock-controller@12460000 {
 447                         compatible = "samsung,exynos5433-cmu-g2d";
 448                         reg = <0x12460000 0x1000>;
 449                         #clock-cells = <1>;
 450
 451                         clock-names = "oscclk",
 452                                 "aclk_g2d_266",
 453                                 "aclk_g2d_400";
 454                         clocks = <&xxti>,
 455                                 <&cmu_top CLK_ACLK_G2D_266>,
 456                                 <&cmu_top CLK_ACLK_G2D_400>;
 457                         power-domains = <&pd_g2d>;
 458                 };
 459
 460                 cmu_disp: clock-controller@13b90000 {
 461                         compatible = "samsung,exynos5433-cmu-disp";
 462                         reg = <0x13b90000 0x1000>;
 463                         #clock-cells = <1>;
 464
 465                         clock-names = "oscclk",
 466                                 "sclk_dsim1_disp",
 467                                 "sclk_dsim0_disp",
 468                                 "sclk_dsd_disp",
 469                                 "sclk_decon_tv_eclk_disp",
 470                                 "sclk_decon_vclk_disp",
 471                                 "sclk_decon_eclk_disp",
 472                                 "sclk_decon_tv_vclk_disp",
 473                                 "aclk_disp_333";
 474                         clocks = <&xxti>,
 475                                 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
 476                                 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
 477                                 <&cmu_mif CLK_SCLK_DSD_DISP>,
 478                                 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 479                                 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
 480                                 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 481                                 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 482                                 <&cmu_mif CLK_ACLK_DISP_333>;
 483                         power-domains = <&pd_disp>;
 484                 };
 485
 486                 cmu_aud: clock-controller@114c0000 {
 487                         compatible = "samsung,exynos5433-cmu-aud";
 488                         reg = <0x114c0000 0x1000>;
 489                         #clock-cells = <1>;
 490                         clock-names = "oscclk", "fout_aud_pll";
 491                         clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
 492                         power-domains = <&pd_aud>;
 493                 };
 494
 495                 cmu_bus0: clock-controller@13600000 {
 496                         compatible = "samsung,exynos5433-cmu-bus0";
 497                         reg = <0x13600000 0x1000>;
 498                         #clock-cells = <1>;
 499
 500                         clock-names = "aclk_bus0_400";
 501                         clocks = <&cmu_top CLK_ACLK_BUS0_400>;
 502                 };
 503
 504                 cmu_bus1: clock-controller@14800000 {
 505                         compatible = "samsung,exynos5433-cmu-bus1";
 506                         reg = <0x14800000 0x1000>;
 507                         #clock-cells = <1>;
 508
 509                         clock-names = "aclk_bus1_400";
 510                         clocks = <&cmu_top CLK_ACLK_BUS1_400>;
 511                 };
 512
 513                 cmu_bus2: clock-controller@13400000 {
 514                         compatible = "samsung,exynos5433-cmu-bus2";
 515                         reg = <0x13400000 0x1000>;
 516                         #clock-cells = <1>;
 517
 518                         clock-names = "oscclk", "aclk_bus2_400";
 519                         clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
 520                 };
 521
 522                 cmu_g3d: clock-controller@14aa0000 {
 523                         compatible = "samsung,exynos5433-cmu-g3d";
 524                         reg = <0x14aa0000 0x2000>;
 525                         #clock-cells = <1>;
 526
 527                         clock-names = "oscclk", "aclk_g3d_400";
 528                         clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
 529                         power-domains = <&pd_g3d>;
 530                 };
 531
 532                 cmu_gscl: clock-controller@13cf0000 {
 533                         compatible = "samsung,exynos5433-cmu-gscl";
 534                         reg = <0x13cf0000 0x1000>;
 535                         #clock-cells = <1>;
 536
 537                         clock-names = "oscclk",
 538                                 "aclk_gscl_111",
 539                                 "aclk_gscl_333";
 540                         clocks = <&xxti>,
 541                                 <&cmu_top CLK_ACLK_GSCL_111>,
 542                                 <&cmu_top CLK_ACLK_GSCL_333>;
 543                         power-domains = <&pd_gscl>;
 544                 };
 545
 546                 cmu_apollo: clock-controller@11900000 {
 547                         compatible = "samsung,exynos5433-cmu-apollo";
 548                         reg = <0x11900000 0x2000>;
 549                         #clock-cells = <1>;
 550
 551                         clock-names = "oscclk", "sclk_bus_pll_apollo";
 552                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
 553                 };
 554
 555                 cmu_atlas: clock-controller@11800000 {
 556                         compatible = "samsung,exynos5433-cmu-atlas";
 557                         reg = <0x11800000 0x2000>;
 558                         #clock-cells = <1>;
 559
 560                         clock-names = "oscclk", "sclk_bus_pll_atlas";
 561                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
 562                 };
 563
 564                 cmu_mscl: clock-controller@150d0000 {
 565                         compatible = "samsung,exynos5433-cmu-mscl";
 566                         reg = <0x150d0000 0x1000>;
 567                         #clock-cells = <1>;
 568
 569                         clock-names = "oscclk",
 570                                 "sclk_jpeg_mscl",
 571                                 "aclk_mscl_400";
 572                         clocks = <&xxti>,
 573                                 <&cmu_top CLK_SCLK_JPEG_MSCL>,
 574                                 <&cmu_top CLK_ACLK_MSCL_400>;
 575                         power-domains = <&pd_mscl>;
 576                 };
 577
 578                 cmu_mfc: clock-controller@15280000 {
 579                         compatible = "samsung,exynos5433-cmu-mfc";
 580                         reg = <0x15280000 0x1000>;
 581                         #clock-cells = <1>;
 582
 583                         clock-names = "oscclk", "aclk_mfc_400";
 584                         clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
 585                         power-domains = <&pd_mfc>;
 586                 };
 587
 588                 cmu_hevc: clock-controller@14f80000 {
 589                         compatible = "samsung,exynos5433-cmu-hevc";
 590                         reg = <0x14f80000 0x1000>;
 591                         #clock-cells = <1>;
 592
 593                         clock-names = "oscclk", "aclk_hevc_400";
 594                         clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
 595                         power-domains = <&pd_hevc>;
 596                 };
 597
 598                 cmu_isp: clock-controller@146d0000 {
 599                         compatible = "samsung,exynos5433-cmu-isp";
 600                         reg = <0x146d0000 0x1000>;
 601                         #clock-cells = <1>;
 602
 603                         clock-names = "oscclk",
 604                                 "aclk_isp_dis_400",
 605                                 "aclk_isp_400";
 606                         clocks = <&xxti>,
 607                                 <&cmu_top CLK_ACLK_ISP_DIS_400>,
 608                                 <&cmu_top CLK_ACLK_ISP_400>;
 609                         power-domains = <&pd_isp>;
 610                 };
 611
 612                 cmu_cam0: clock-controller@120d0000 {
 613                         compatible = "samsung,exynos5433-cmu-cam0";
 614                         reg = <0x120d0000 0x1000>;
 615                         #clock-cells = <1>;
 616
 617                         clock-names = "oscclk",
 618                                 "aclk_cam0_333",
 619                                 "aclk_cam0_400",
 620                                 "aclk_cam0_552";
 621                         clocks = <&xxti>,
 622                                 <&cmu_top CLK_ACLK_CAM0_333>,
 623                                 <&cmu_top CLK_ACLK_CAM0_400>,
 624                                 <&cmu_top CLK_ACLK_CAM0_552>;
 625                         power-domains = <&pd_cam0>;
 626                 };
 627
 628                 cmu_cam1: clock-controller@145d0000 {
 629                         compatible = "samsung,exynos5433-cmu-cam1";
 630                         reg = <0x145d0000 0x1000>;
 631                         #clock-cells = <1>;
 632
 633                         clock-names = "oscclk",
 634                                 "sclk_isp_uart_cam1",
 635                                 "sclk_isp_spi1_cam1",
 636                                 "sclk_isp_spi0_cam1",
 637                                 "aclk_cam1_333",
 638                                 "aclk_cam1_400",
 639                                 "aclk_cam1_552";
 640                         clocks = <&xxti>,
 641                                 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
 642                                 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
 643                                 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
 644                                 <&cmu_top CLK_ACLK_CAM1_333>,
 645                                 <&cmu_top CLK_ACLK_CAM1_400>,
 646                                 <&cmu_top CLK_ACLK_CAM1_552>;
 647                         power-domains = <&pd_cam1>;
 648                 };
 649
 650                 cmu_imem: clock-controller@11060000 {
 651                         compatible = "samsung,exynos5433-cmu-imem";
 652                         reg = <0x11060000 0x1000>;
 653                         #clock-cells = <1>;
 654
 655                         clock-names = "oscclk",
 656                                 "aclk_imem_sssx_266",
 657                                 "aclk_imem_266",
 658                                 "aclk_imem_200";
 659                         clocks = <&xxti>,
 660                                 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
 661                                 <&cmu_top CLK_DIV_ACLK_IMEM_266>,
 662                                 <&cmu_top CLK_DIV_ACLK_IMEM_200>;
 663                 };
 664
 665                 slim_sss: slim-sss@11140000 {
 666                         compatible = "samsung,exynos5433-slim-sss";
 667                         reg = <0x11140000 0x1000>;
 668                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
 669                         clock-names = "pclk", "aclk";
 670                         clocks = <&cmu_imem CLK_PCLK_SLIMSSS>,
 671                                  <&cmu_imem CLK_ACLK_SLIMSSS>;
 672                 };
 673
 674                 pd_gscl: power-domain@105c4000 {
 675                         compatible = "samsung,exynos5433-pd";
 676                         reg = <0x105c4000 0x20>;
 677                         #power-domain-cells = <0>;
 678                         label = "GSCL";
 679                 };
 680
 681                 pd_cam0: power-domain@105c4020 {
 682                         compatible = "samsung,exynos5433-pd";
 683                         reg = <0x105c4020 0x20>;
 684                         #power-domain-cells = <0>;
 685                         power-domains = <&pd_cam1>;
 686                         label = "CAM0";
 687                 };
 688
 689                 pd_mscl: power-domain@105c4040 {
 690                         compatible = "samsung,exynos5433-pd";
 691                         reg = <0x105c4040 0x20>;
 692                         #power-domain-cells = <0>;
 693                         label = "MSCL";
 694                 };
 695
 696                 pd_g3d: power-domain@105c4060 {
 697                         compatible = "samsung,exynos5433-pd";
 698                         reg = <0x105c4060 0x20>;
 699                         #power-domain-cells = <0>;
 700                         label = "G3D";
 701                 };
 702
 703                 pd_disp: power-domain@105c4080 {
 704                         compatible = "samsung,exynos5433-pd";
 705                         reg = <0x105c4080 0x20>;
 706                         #power-domain-cells = <0>;
 707                         label = "DISP";
 708                 };
 709
 710                 pd_cam1: power-domain@105c40a0 {
 711                         compatible = "samsung,exynos5433-pd";
 712                         reg = <0x105c40a0 0x20>;
 713                         #power-domain-cells = <0>;
 714                         label = "CAM1";
 715                 };
 716
 717                 pd_aud: power-domain@105c40c0 {
 718                         compatible = "samsung,exynos5433-pd";
 719                         reg = <0x105c40c0 0x20>;
 720                         #power-domain-cells = <0>;
 721                         label = "AUD";
 722                 };
 723
 724                 pd_g2d: power-domain@105c4120 {
 725                         compatible = "samsung,exynos5433-pd";
 726                         reg = <0x105c4120 0x20>;
 727                         #power-domain-cells = <0>;
 728                         label = "G2D";
 729                 };
 730
 731                 pd_isp: power-domain@105c4140 {
 732                         compatible = "samsung,exynos5433-pd";
 733                         reg = <0x105c4140 0x20>;
 734                         #power-domain-cells = <0>;
 735                         power-domains = <&pd_cam0>;
 736                         label = "ISP";
 737                 };
 738
 739                 pd_mfc: power-domain@105c4180 {
 740                         compatible = "samsung,exynos5433-pd";
 741                         reg = <0x105c4180 0x20>;
 742                         #power-domain-cells = <0>;
 743                         label = "MFC";
 744                 };
 745
 746                 pd_hevc: power-domain@105c41c0 {
 747                         compatible = "samsung,exynos5433-pd";
 748                         reg = <0x105c41c0 0x20>;
 749                         #power-domain-cells = <0>;
 750                         label = "HEVC";
 751                 };
 752
 753                 tmu_atlas0: tmu@10060000 {
 754                         compatible = "samsung,exynos5433-tmu";
 755                         reg = <0x10060000 0x200>;
 756                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 757                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 758                                 <&cmu_peris CLK_SCLK_TMU0>;
 759                         clock-names = "tmu_apbif", "tmu_sclk";
 760                         #thermal-sensor-cells = <0>;
 761                         status = "disabled";
 762                 };
 763
 764                 tmu_atlas1: tmu@10068000 {
 765                         compatible = "samsung,exynos5433-tmu";
 766                         reg = <0x10068000 0x200>;
 767                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 768                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 769                                 <&cmu_peris CLK_SCLK_TMU0>;
 770                         clock-names = "tmu_apbif", "tmu_sclk";
 771                         #thermal-sensor-cells = <0>;
 772                         status = "disabled";
 773                 };
 774
 775                 tmu_g3d: tmu@10070000 {
 776                         compatible = "samsung,exynos5433-tmu";
 777                         reg = <0x10070000 0x200>;
 778                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 779                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 780                                 <&cmu_peris CLK_SCLK_TMU1>;
 781                         clock-names = "tmu_apbif", "tmu_sclk";
 782                         #thermal-sensor-cells = <0>;
 783                         status = "disabled";
 784                 };
 785
 786                 tmu_apollo: tmu@10078000 {
 787                         compatible = "samsung,exynos5433-tmu";
 788                         reg = <0x10078000 0x200>;
 789                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 790                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 791                                 <&cmu_peris CLK_SCLK_TMU1>;
 792                         clock-names = "tmu_apbif", "tmu_sclk";
 793                         #thermal-sensor-cells = <0>;
 794                         status = "disabled";
 795                 };
 796
 797                 tmu_isp: tmu@1007c000 {
 798                         compatible = "samsung,exynos5433-tmu";
 799                         reg = <0x1007c000 0x200>;
 800                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 801                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 802                                 <&cmu_peris CLK_SCLK_TMU1>;
 803                         clock-names = "tmu_apbif", "tmu_sclk";
 804                         #thermal-sensor-cells = <0>;
 805                         status = "disabled";
 806                 };
 807
 808                 timer@101c0000 {
 809                         compatible = "samsung,exynos5433-mct",
 810                                      "samsung,exynos4210-mct";
 811                         reg = <0x101c0000 0x800>;
 812                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 813                                 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 814                                 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 815                                 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 816                                 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 817                                 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 818                                 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 819                                 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 820                                 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 821                                 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 822                                 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 823                                 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 824                         clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
 825                         clock-names = "fin_pll", "mct";
 826                 };
 827
 828                 ppmu_d0_cpu: ppmu@10480000 {
 829                         compatible = "samsung,exynos-ppmu-v2";
 830                         reg = <0x10480000 0x2000>;
 831                         status = "disabled";
 832                 };
 833
 834                 ppmu_d0_general: ppmu@10490000 {
 835                         compatible = "samsung,exynos-ppmu-v2";
 836                         reg = <0x10490000 0x2000>;
 837                         status = "disabled";
 838                 };
 839
 840                 ppmu_d1_cpu: ppmu@104b0000 {
 841                         compatible = "samsung,exynos-ppmu-v2";
 842                         reg = <0x104b0000 0x2000>;
 843                         status = "disabled";
 844                 };
 845
 846                 ppmu_d1_general: ppmu@104c0000 {
 847                         compatible = "samsung,exynos-ppmu-v2";
 848                         reg = <0x104c0000 0x2000>;
 849                         status = "disabled";
 850                 };
 851
 852                 pinctrl_alive: pinctrl@10580000 {
 853                         compatible = "samsung,exynos5433-pinctrl";
 854                         reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
 855
 856                         wakeup-interrupt-controller {
 857                                 compatible = "samsung,exynos7-wakeup-eint";
 858                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 859                         };
 860                 };
 861
 862                 pinctrl_aud: pinctrl@114b0000 {
 863                         compatible = "samsung,exynos5433-pinctrl";
 864                         reg = <0x114b0000 0x1000>;
 865                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 866                         power-domains = <&pd_aud>;
 867                 };
 868
 869                 pinctrl_cpif: pinctrl@10fe0000 {
 870                         compatible = "samsung,exynos5433-pinctrl";
 871                         reg = <0x10fe0000 0x1000>;
 872                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 873                 };
 874
 875                 pinctrl_ese: pinctrl@14ca0000 {
 876                         compatible = "samsung,exynos5433-pinctrl";
 877                         reg = <0x14ca0000 0x1000>;
 878                         interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
 879                 };
 880
 881                 pinctrl_finger: pinctrl@14cb0000 {
 882                         compatible = "samsung,exynos5433-pinctrl";
 883                         reg = <0x14cb0000 0x1000>;
 884                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 885                 };
 886
 887                 pinctrl_fsys: pinctrl@15690000 {
 888                         compatible = "samsung,exynos5433-pinctrl";
 889                         reg = <0x15690000 0x1000>;
 890                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 891                 };
 892
 893                 pinctrl_imem: pinctrl@11090000 {
 894                         compatible = "samsung,exynos5433-pinctrl";
 895                         reg = <0x11090000 0x1000>;
 896                         interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
 897                 };
 898
 899                 pinctrl_nfc: pinctrl@14cd0000 {
 900                         compatible = "samsung,exynos5433-pinctrl";
 901                         reg = <0x14cd0000 0x1000>;
 902                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 903                 };
 904
 905                 pinctrl_peric: pinctrl@14cc0000 {
 906                         compatible = "samsung,exynos5433-pinctrl";
 907                         reg = <0x14cc0000 0x1100>;
 908                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 909                 };
 910
 911                 pinctrl_touch: pinctrl@14ce0000 {
 912                         compatible = "samsung,exynos5433-pinctrl";
 913                         reg = <0x14ce0000 0x1100>;
 914                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 915                 };
 916
 917                 pmu_system_controller: system-controller@105c0000 {
 918                         compatible = "samsung,exynos5433-pmu", "syscon";
 919                         reg = <0x105c0000 0x5008>;
 920                         #clock-cells = <1>;
 921                         clock-names = "clkout16";
 922                         clocks = <&xxti>;
 923
 924                         reboot: syscon-reboot {
 925                                 compatible = "syscon-reboot";
 926                                 regmap = <&pmu_system_controller>;
 927                                 offset = <0x400>; /* SWRESET */
 928                                 mask = <0x1>;
 929                         };
 930                 };
 931
 932                 gic: interrupt-controller@11001000 {
 933                         compatible = "arm,gic-400";
 934                         #interrupt-cells = <3>;
 935                         interrupt-controller;
 936                         reg = <0x11001000 0x1000>,
 937                                 <0x11002000 0x2000>,
 938                                 <0x11004000 0x2000>,
 939                                 <0x11006000 0x2000>;
 940                         interrupts = <GIC_PPI 9 0xf04>;
 941                 };
 942
 943                 mipi_phy: video-phy {
 944                         compatible = "samsung,exynos5433-mipi-video-phy";
 945                         #phy-cells = <1>;
 946                         samsung,pmu-syscon = <&pmu_system_controller>;
 947                         samsung,cam0-sysreg = <&syscon_cam0>;
 948                         samsung,cam1-sysreg = <&syscon_cam1>;
 949                         samsung,disp-sysreg = <&syscon_disp>;
 950                 };
 951
 952                 decon: decon@13800000 {
 953                         compatible = "samsung,exynos5433-decon";
 954                         reg = <0x13800000 0x2104>;
 955                         clocks = <&cmu_disp CLK_PCLK_DECON>,
 956                                 <&cmu_disp CLK_ACLK_DECON>,
 957                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
 958                                 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
 959                                 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 960                                 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
 961                                 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
 962                                 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 963                                 <&cmu_disp CLK_SCLK_DECON_VCLK>,
 964                                 <&cmu_disp CLK_SCLK_DECON_ECLK>,
 965                                 <&cmu_disp CLK_SCLK_DSD>;
 966                         clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 967                                 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 968                                 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
 969                                 "pclk_smmu_decon1x", "sclk_decon_vclk",
 970                                 "sclk_decon_eclk", "dsd";
 971                         power-domains = <&pd_disp>;
 972                         interrupt-names = "fifo", "vsync", "lcd_sys";
 973                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 974                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 975                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 976                         samsung,disp-sysreg = <&syscon_disp>;
 977                         status = "disabled";
 978                         iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
 979                         iommu-names = "m0", "m1";
 980
 981                         ports {
 982                                 #address-cells = <1>;
 983                                 #size-cells = <0>;
 984
 985                                 port@0 {
 986                                         reg = <0>;
 987                                         decon_to_mic: endpoint {
 988                                                 remote-endpoint =
 989                                                         <&mic_to_decon>;
 990                                         };
 991                                 };
 992                         };
 993                 };
 994
 995                 decon_tv: decon@13880000 {
 996                         compatible = "samsung,exynos5433-decon-tv";
 997                         reg = <0x13880000 0x20b8>;
 998                         clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
 999                                  <&cmu_disp CLK_ACLK_DECON_TV>,
1000                                  <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1001                                  <&cmu_disp CLK_ACLK_XIU_TV0X>,
1002                                  <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1003                                  <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1004                                  <&cmu_disp CLK_ACLK_XIU_TV1X>,
1005                                  <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1006                                  <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
1007                                  <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
1008                                  <&cmu_disp CLK_SCLK_DSD>;
1009                         clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
1010                                       "aclk_xiu_decon0x", "pclk_smmu_decon0x",
1011                                       "aclk_smmu_decon1x", "aclk_xiu_decon1x",
1012                                       "pclk_smmu_decon1x", "sclk_decon_vclk",
1013                                       "sclk_decon_eclk", "dsd";
1014                         samsung,disp-sysreg = <&syscon_disp>;
1015                         power-domains = <&pd_disp>;
1016                         interrupt-names = "fifo", "vsync", "lcd_sys";
1017                         interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1018                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1019                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1020                         status = "disabled";
1021                         iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
1022                         iommu-names = "m0", "m1";
1023                 };
1024
1025                 dsi: dsi@13900000 {
1026                         compatible = "samsung,exynos5433-mipi-dsi";
1027                         reg = <0x13900000 0xC0>;
1028                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1029                         phys = <&mipi_phy 1>;
1030                         phy-names = "dsim";
1031                         clocks = <&cmu_disp CLK_PCLK_DSIM0>,
1032                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
1033                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
1034                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
1035                                 <&cmu_disp CLK_SCLK_DSIM0>;
1036                         clock-names = "bus_clk",
1037                                         "phyclk_mipidphy0_bitclkdiv8",
1038                                         "phyclk_mipidphy0_rxclkesc0",
1039                                         "sclk_rgb_vclk_to_dsim0",
1040                                         "sclk_mipi";
1041                         power-domains = <&pd_disp>;
1042                         status = "disabled";
1043                         #address-cells = <1>;
1044                         #size-cells = <0>;
1045
1046                         ports {
1047                                 #address-cells = <1>;
1048                                 #size-cells = <0>;
1049
1050                                 port@0 {
1051                                         reg = <0>;
1052                                         dsi_to_mic: endpoint {
1053                                                 remote-endpoint = <&mic_to_dsi>;
1054                                         };
1055                                 };
1056                         };
1057                 };
1058
1059                 mic: mic@13930000 {
1060                         compatible = "samsung,exynos5433-mic";
1061                         reg = <0x13930000 0x48>;
1062                         clocks = <&cmu_disp CLK_PCLK_MIC0>,
1063                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
1064                         clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
1065                         power-domains = <&pd_disp>;
1066                         samsung,disp-syscon = <&syscon_disp>;
1067                         status = "disabled";
1068
1069                         ports {
1070                                 #address-cells = <1>;
1071                                 #size-cells = <0>;
1072
1073                                 port@0 {
1074                                         reg = <0>;
1075                                         mic_to_decon: endpoint {
1076                                                 remote-endpoint =
1077                                                         <&decon_to_mic>;
1078                                         };
1079                                 };
1080
1081                                 port@1 {
1082                                         reg = <1>;
1083                                         mic_to_dsi: endpoint {
1084                                                 remote-endpoint = <&dsi_to_mic>;
1085                                         };
1086                                 };
1087                         };
1088                 };
1089
1090                 hdmi: hdmi@13970000 {
1091                         compatible = "samsung,exynos5433-hdmi";
1092                         reg = <0x13970000 0x70000>;
1093                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1094                         clocks = <&cmu_disp CLK_PCLK_HDMI>,
1095                                 <&cmu_disp CLK_PCLK_HDMIPHY>,
1096                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
1097                                 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
1098                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
1099                                 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
1100                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
1101                                 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
1102                                 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
1103                         clock-names = "hdmi_pclk", "hdmi_i_pclk",
1104                                 "i_tmds_clk", "i_pixel_clk",
1105                                 "tmds_clko", "tmds_clko_user",
1106                                 "pixel_clko", "pixel_clko_user",
1107                                 "oscclk", "i_spdif_clk";
1108                         phy = <&hdmiphy>;
1109                         ddc = <&hsi2c_11>;
1110                         samsung,syscon-phandle = <&pmu_system_controller>;
1111                         samsung,sysreg-phandle = <&syscon_disp>;
1112                         #sound-dai-cells = <0>;
1113                         status = "disabled";
1114                 };
1115
1116                 hdmiphy: hdmiphy@13af0000 {
1117                         reg = <0x13af0000 0x80>;
1118                 };
1119
1120                 syscon_disp: syscon@13b80000 {
1121                         compatible = "samsung,exynos5433-sysreg", "syscon";
1122                         reg = <0x13b80000 0x1010>;
1123                 };
1124
1125                 syscon_cam0: syscon@120f0000 {
1126                         compatible = "samsung,exynos5433-sysreg", "syscon";
1127                         reg = <0x120f0000 0x1020>;
1128                 };
1129
1130                 syscon_cam1: syscon@145f0000 {
1131                         compatible = "samsung,exynos5433-sysreg", "syscon";
1132                         reg = <0x145f0000 0x1038>;
1133                 };
1134
1135                 syscon_fsys: syscon@156f0000 {
1136                         compatible = "samsung,exynos5433-sysreg", "syscon";
1137                         reg = <0x156f0000 0x1044>;
1138                 };
1139
1140                 gsc_0: video-scaler@13c00000 {
1141                         compatible = "samsung,exynos5433-gsc";
1142                         reg = <0x13c00000 0x1000>;
1143                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1144                         clock-names = "pclk", "aclk", "aclk_xiu",
1145                                       "aclk_gsclbend", "gsd";
1146                         clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1147                                  <&cmu_gscl CLK_ACLK_GSCL0>,
1148                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1149                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1150                                  <&cmu_gscl CLK_ACLK_GSD>;
1151                         iommus = <&sysmmu_gscl0>;
1152                         power-domains = <&pd_gscl>;
1153                 };
1154
1155                 gsc_1: video-scaler@13c10000 {
1156                         compatible = "samsung,exynos5433-gsc";
1157                         reg = <0x13c10000 0x1000>;
1158                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1159                         clock-names = "pclk", "aclk", "aclk_xiu",
1160                                       "aclk_gsclbend", "gsd";
1161                         clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1162                                  <&cmu_gscl CLK_ACLK_GSCL1>,
1163                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1164                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1165                                  <&cmu_gscl CLK_ACLK_GSD>;
1166                         iommus = <&sysmmu_gscl1>;
1167                         power-domains = <&pd_gscl>;
1168                 };
1169
1170                 gsc_2: video-scaler@13c20000 {
1171                         compatible = "samsung,exynos5433-gsc";
1172                         reg = <0x13c20000 0x1000>;
1173                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1174                         clock-names = "pclk", "aclk", "aclk_xiu",
1175                                       "aclk_gsclbend", "gsd";
1176                         clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1177                                  <&cmu_gscl CLK_ACLK_GSCL2>,
1178                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1179                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1180                                  <&cmu_gscl CLK_ACLK_GSD>;
1181                         iommus = <&sysmmu_gscl2>;
1182                         power-domains = <&pd_gscl>;
1183                 };
1184
1185                 gpu: gpu@14ac0000 {
1186                         compatible = "samsung,exynos5433-mali", "arm,mali-t760";
1187                         reg = <0x14ac0000 0x5000>;
1188                         interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1189                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1190                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
1191                         interrupt-names = "job", "mmu", "gpu";
1192                         clocks = <&cmu_g3d CLK_ACLK_G3D>;
1193                         clock-names = "core";
1194                         power-domains = <&pd_g3d>;
1195                         operating-points-v2 = <&gpu_opp_table>;
1196                         status = "disabled";
1197
1198                         gpu_opp_table: opp-table {
1199                                 compatible = "operating-points-v2";
1200
1201                                 opp-160000000 {
1202                                         opp-hz = /bits/ 64 <160000000>;
1203                                         opp-microvolt = <1000000>;
1204                                 };
1205                                 opp-267000000 {
1206                                         opp-hz = /bits/ 64 <267000000>;
1207                                         opp-microvolt = <1000000>;
1208                                 };
1209                                 opp-350000000 {
1210                                         opp-hz = /bits/ 64 <350000000>;
1211                                         opp-microvolt = <1025000>;
1212                                 };
1213                                 opp-420000000 {
1214                                         opp-hz = /bits/ 64 <420000000>;
1215                                         opp-microvolt = <1025000>;
1216                                 };
1217                                 opp-500000000 {
1218                                         opp-hz = /bits/ 64 <500000000>;
1219                                         opp-microvolt = <1075000>;
1220                                 };
1221                                 opp-550000000 {
1222                                         opp-hz = /bits/ 64 <550000000>;
1223                                         opp-microvolt = <1125000>;
1224                                 };
1225                                 opp-600000000 {
1226                                         opp-hz = /bits/ 64 <600000000>;
1227                                         opp-microvolt = <1150000>;
1228                                 };
1229                                 opp-700000000 {
1230                                         opp-hz = /bits/ 64 <700000000>;
1231                                         opp-microvolt = <1150000>;
1232                                 };
1233                         };
1234                 };
1235
1236                 scaler_0: scaler@15000000 {
1237                         compatible = "samsung,exynos5433-scaler";
1238                         reg = <0x15000000 0x1294>;
1239                         interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1240                         clock-names = "pclk", "aclk", "aclk_xiu";
1241                         clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>,
1242                                  <&cmu_mscl CLK_ACLK_M2MSCALER0>,
1243                                  <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1244                         iommus = <&sysmmu_scaler_0>;
1245                         power-domains = <&pd_mscl>;
1246                 };
1247
1248                 scaler_1: scaler@15010000 {
1249                         compatible = "samsung,exynos5433-scaler";
1250                         reg = <0x15010000 0x1294>;
1251                         interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1252                         clock-names = "pclk", "aclk", "aclk_xiu";
1253                         clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>,
1254                                  <&cmu_mscl CLK_ACLK_M2MSCALER1>,
1255                                  <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1256                         iommus = <&sysmmu_scaler_1>;
1257                         power-domains = <&pd_mscl>;
1258                 };
1259
1260                 jpeg: codec@15020000 {
1261                         compatible = "samsung,exynos5433-jpeg";
1262                         reg = <0x15020000 0x10000>;
1263                         interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1264                         clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1265                         clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1266                                  <&cmu_mscl CLK_ACLK_JPEG>,
1267                                  <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1268                                  <&cmu_mscl CLK_SCLK_JPEG>;
1269                         iommus = <&sysmmu_jpeg>;
1270                         power-domains = <&pd_mscl>;
1271                 };
1272
1273                 mfc: codec@152e0000 {
1274                         compatible = "samsung,exynos5433-mfc";
1275                         reg = <0x152E0000 0x10000>;
1276                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1277                         clock-names = "pclk", "aclk", "aclk_xiu";
1278                         clocks = <&cmu_mfc CLK_PCLK_MFC>,
1279                                  <&cmu_mfc CLK_ACLK_MFC>,
1280                                  <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1281                         iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1282                         iommu-names = "left", "right";
1283                         power-domains = <&pd_mfc>;
1284                 };
1285
1286                 sysmmu_decon0x: sysmmu@13a00000 {
1287                         compatible = "samsung,exynos-sysmmu";
1288                         reg = <0x13a00000 0x1000>;
1289                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1290                         clock-names = "aclk", "pclk";
1291                         clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
1292                                 <&cmu_disp CLK_PCLK_SMMU_DECON0X>;
1293                         power-domains = <&pd_disp>;
1294                         #iommu-cells = <0>;
1295                 };
1296
1297                 sysmmu_decon1x: sysmmu@13a10000 {
1298                         compatible = "samsung,exynos-sysmmu";
1299                         reg = <0x13a10000 0x1000>;
1300                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1301                         clock-names = "aclk", "pclk";
1302                         clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
1303                                 <&cmu_disp CLK_PCLK_SMMU_DECON1X>;
1304                         #iommu-cells = <0>;
1305                         power-domains = <&pd_disp>;
1306                 };
1307
1308                 sysmmu_tv0x: sysmmu@13a20000 {
1309                         compatible = "samsung,exynos-sysmmu";
1310                         reg = <0x13a20000 0x1000>;
1311                         interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1312                         clock-names = "aclk", "pclk";
1313                         clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1314                                 <&cmu_disp CLK_PCLK_SMMU_TV0X>;
1315                         #iommu-cells = <0>;
1316                         power-domains = <&pd_disp>;
1317                 };
1318
1319                 sysmmu_tv1x: sysmmu@13a30000 {
1320                         compatible = "samsung,exynos-sysmmu";
1321                         reg = <0x13a30000 0x1000>;
1322                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1323                         clock-names = "aclk", "pclk";
1324                         clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1325                                 <&cmu_disp CLK_PCLK_SMMU_TV1X>;
1326                         #iommu-cells = <0>;
1327                         power-domains = <&pd_disp>;
1328                 };
1329
1330                 sysmmu_gscl0: sysmmu@13c80000 {
1331                         compatible = "samsung,exynos-sysmmu";
1332                         reg = <0x13C80000 0x1000>;
1333                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1334                         clock-names = "aclk", "pclk";
1335                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1336                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1337                         #iommu-cells = <0>;
1338                         power-domains = <&pd_gscl>;
1339                 };
1340
1341                 sysmmu_gscl1: sysmmu@13c90000 {
1342                         compatible = "samsung,exynos-sysmmu";
1343                         reg = <0x13C90000 0x1000>;
1344                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1345                         clock-names = "aclk", "pclk";
1346                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1347                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1348                         #iommu-cells = <0>;
1349                         power-domains = <&pd_gscl>;
1350                 };
1351
1352                 sysmmu_gscl2: sysmmu@13ca0000 {
1353                         compatible = "samsung,exynos-sysmmu";
1354                         reg = <0x13CA0000 0x1000>;
1355                         interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1356                         clock-names = "aclk", "pclk";
1357                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1358                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1359                         #iommu-cells = <0>;
1360                         power-domains = <&pd_gscl>;
1361                 };
1362
1363                 sysmmu_scaler_0: sysmmu@15040000 {
1364                         compatible = "samsung,exynos-sysmmu";
1365                         reg = <0x15040000 0x1000>;
1366                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1367                         clock-names = "aclk", "pclk";
1368                         clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>,
1369                                 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>;
1370                         #iommu-cells = <0>;
1371                         power-domains = <&pd_mscl>;
1372                 };
1373
1374                 sysmmu_scaler_1: sysmmu@15050000 {
1375                         compatible = "samsung,exynos-sysmmu";
1376                         reg = <0x15050000 0x1000>;
1377                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
1378                         clock-names = "aclk", "pclk";
1379                         clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>,
1380                                 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>;
1381                         #iommu-cells = <0>;
1382                         power-domains = <&pd_mscl>;
1383                 };
1384
1385                 sysmmu_jpeg: sysmmu@15060000 {
1386                         compatible = "samsung,exynos-sysmmu";
1387                         reg = <0x15060000 0x1000>;
1388                         interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1389                         clock-names = "aclk", "pclk";
1390                         clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>,
1391                                 <&cmu_mscl CLK_PCLK_SMMU_JPEG>;
1392                         #iommu-cells = <0>;
1393                         power-domains = <&pd_mscl>;
1394                 };
1395
1396                 sysmmu_mfc_0: sysmmu@15200000 {
1397                         compatible = "samsung,exynos-sysmmu";
1398                         reg = <0x15200000 0x1000>;
1399                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1400                         clock-names = "aclk", "pclk";
1401                         clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>,
1402                                 <&cmu_mfc CLK_PCLK_SMMU_MFC_0>;
1403                         #iommu-cells = <0>;
1404                         power-domains = <&pd_mfc>;
1405                 };
1406
1407                 sysmmu_mfc_1: sysmmu@15210000 {
1408                         compatible = "samsung,exynos-sysmmu";
1409                         reg = <0x15210000 0x1000>;
1410                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1411                         clock-names = "aclk", "pclk";
1412                         clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>,
1413                                 <&cmu_mfc CLK_PCLK_SMMU_MFC_1>;
1414                         #iommu-cells = <0>;
1415                         power-domains = <&pd_mfc>;
1416                 };
1417
1418                 serial_0: serial@14c10000 {
1419                         compatible = "samsung,exynos5433-uart";
1420                         reg = <0x14c10000 0x100>;
1421                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1422                         clocks = <&cmu_peric CLK_PCLK_UART0>,
1423                                 <&cmu_peric CLK_SCLK_UART0>;
1424                         clock-names = "uart", "clk_uart_baud0";
1425                         pinctrl-names = "default";
1426                         pinctrl-0 = <&uart0_bus>;
1427                         status = "disabled";
1428                 };
1429
1430                 serial_1: serial@14c20000 {
1431                         compatible = "samsung,exynos5433-uart";
1432                         reg = <0x14c20000 0x100>;
1433                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1434                         clocks = <&cmu_peric CLK_PCLK_UART1>,
1435                                 <&cmu_peric CLK_SCLK_UART1>;
1436                         clock-names = "uart", "clk_uart_baud0";
1437                         pinctrl-names = "default";
1438                         pinctrl-0 = <&uart1_bus>;
1439                         status = "disabled";
1440                 };
1441
1442                 serial_2: serial@14c30000 {
1443                         compatible = "samsung,exynos5433-uart";
1444                         reg = <0x14c30000 0x100>;
1445                         interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1446                         clocks = <&cmu_peric CLK_PCLK_UART2>,
1447                                 <&cmu_peric CLK_SCLK_UART2>;
1448                         clock-names = "uart", "clk_uart_baud0";
1449                         pinctrl-names = "default";
1450                         pinctrl-0 = <&uart2_bus>;
1451                         status = "disabled";
1452                 };
1453
1454                 spi_0: spi@14d20000 {
1455                         compatible = "samsung,exynos5433-spi";
1456                         reg = <0x14d20000 0x100>;
1457                         interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1458                         dmas = <&pdma0 9>, <&pdma0 8>;
1459                         dma-names = "tx", "rx";
1460                         #address-cells = <1>;
1461                         #size-cells = <0>;
1462                         clocks = <&cmu_peric CLK_PCLK_SPI0>,
1463                                 <&cmu_peric CLK_SCLK_SPI0>,
1464                                 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1465                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1466                         samsung,spi-src-clk = <0>;
1467                         pinctrl-names = "default";
1468                         pinctrl-0 = <&spi0_bus>;
1469                         num-cs = <1>;
1470                         status = "disabled";
1471                 };
1472
1473                 spi_1: spi@14d30000 {
1474                         compatible = "samsung,exynos5433-spi";
1475                         reg = <0x14d30000 0x100>;
1476                         interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1477                         dmas = <&pdma0 11>, <&pdma0 10>;
1478                         dma-names = "tx", "rx";
1479                         #address-cells = <1>;
1480                         #size-cells = <0>;
1481                         clocks = <&cmu_peric CLK_PCLK_SPI1>,
1482                                 <&cmu_peric CLK_SCLK_SPI1>,
1483                                 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1484                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1485                         samsung,spi-src-clk = <0>;
1486                         pinctrl-names = "default";
1487                         pinctrl-0 = <&spi1_bus>;
1488                         num-cs = <1>;
1489                         status = "disabled";
1490                 };
1491
1492                 spi_2: spi@14d40000 {
1493                         compatible = "samsung,exynos5433-spi";
1494                         reg = <0x14d40000 0x100>;
1495                         interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1496                         dmas = <&pdma0 13>, <&pdma0 12>;
1497                         dma-names = "tx", "rx";
1498                         #address-cells = <1>;
1499                         #size-cells = <0>;
1500                         clocks = <&cmu_peric CLK_PCLK_SPI2>,
1501                                 <&cmu_peric CLK_SCLK_SPI2>,
1502                                 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1503                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1504                         samsung,spi-src-clk = <0>;
1505                         pinctrl-names = "default";
1506                         pinctrl-0 = <&spi2_bus>;
1507                         num-cs = <1>;
1508                         status = "disabled";
1509                 };
1510
1511                 spi_3: spi@14d50000 {
1512                         compatible = "samsung,exynos5433-spi";
1513                         reg = <0x14d50000 0x100>;
1514                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1515                         dmas = <&pdma0 23>, <&pdma0 22>;
1516                         dma-names = "tx", "rx";
1517                         #address-cells = <1>;
1518                         #size-cells = <0>;
1519                         clocks = <&cmu_peric CLK_PCLK_SPI3>,
1520                                 <&cmu_peric CLK_SCLK_SPI3>,
1521                                 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1522                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1523                         samsung,spi-src-clk = <0>;
1524                         pinctrl-names = "default";
1525                         pinctrl-0 = <&spi3_bus>;
1526                         num-cs = <1>;
1527                         status = "disabled";
1528                 };
1529
1530                 spi_4: spi@14d00000 {
1531                         compatible = "samsung,exynos5433-spi";
1532                         reg = <0x14d00000 0x100>;
1533                         interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1534                         dmas = <&pdma0 25>, <&pdma0 24>;
1535                         dma-names = "tx", "rx";
1536                         #address-cells = <1>;
1537                         #size-cells = <0>;
1538                         clocks = <&cmu_peric CLK_PCLK_SPI4>,
1539                                 <&cmu_peric CLK_SCLK_SPI4>,
1540                                 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1541                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1542                         samsung,spi-src-clk = <0>;
1543                         pinctrl-names = "default";
1544                         pinctrl-0 = <&spi4_bus>;
1545                         num-cs = <1>;
1546                         status = "disabled";
1547                 };
1548
1549                 adc: adc@14d10000 {
1550                         compatible = "samsung,exynos7-adc";
1551                         reg = <0x14d10000 0x100>;
1552                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1553                         clock-names = "adc";
1554                         clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1555                         #io-channel-cells = <1>;
1556                         status = "disabled";
1557                 };
1558
1559                 i2s1: i2s@14d60000 {
1560                         compatible = "samsung,exynos7-i2s";
1561                         reg = <0x14d60000 0x100>;
1562                         dmas = <&pdma0 31>, <&pdma0 30>;
1563                         dma-names = "tx", "rx";
1564                         interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
1565                         clocks = <&cmu_peric CLK_PCLK_I2S1>,
1566                                  <&cmu_peric CLK_PCLK_I2S1>,
1567                                  <&cmu_peric CLK_SCLK_I2S1>;
1568                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1569                         #clock-cells = <1>;
1570                         #sound-dai-cells = <1>;
1571                         status = "disabled";
1572                 };
1573
1574                 pwm: pwm@14dd0000 {
1575                         compatible = "samsung,exynos4210-pwm";
1576                         reg = <0x14dd0000 0x100>;
1577                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1578                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1579                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1580                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1581                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1582                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1583                         clocks = <&cmu_peric CLK_PCLK_PWM>;
1584                         clock-names = "timers";
1585                         #pwm-cells = <3>;
1586                         status = "disabled";
1587                 };
1588
1589                 hsi2c_0: i2c@14e40000 {
1590                         compatible = "samsung,exynos7-hsi2c";
1591                         reg = <0x14e40000 0x1000>;
1592                         interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1593                         #address-cells = <1>;
1594                         #size-cells = <0>;
1595                         pinctrl-names = "default";
1596                         pinctrl-0 = <&hs_i2c0_bus>;
1597                         clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1598                         clock-names = "hsi2c";
1599                         status = "disabled";
1600                 };
1601
1602                 hsi2c_1: i2c@14e50000 {
1603                         compatible = "samsung,exynos7-hsi2c";
1604                         reg = <0x14e50000 0x1000>;
1605                         interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1606                         #address-cells = <1>;
1607                         #size-cells = <0>;
1608                         pinctrl-names = "default";
1609                         pinctrl-0 = <&hs_i2c1_bus>;
1610                         clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1611                         clock-names = "hsi2c";
1612                         status = "disabled";
1613                 };
1614
1615                 hsi2c_2: i2c@14e60000 {
1616                         compatible = "samsung,exynos7-hsi2c";
1617                         reg = <0x14e60000 0x1000>;
1618                         interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1619                         #address-cells = <1>;
1620                         #size-cells = <0>;
1621                         pinctrl-names = "default";
1622                         pinctrl-0 = <&hs_i2c2_bus>;
1623                         clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1624                         clock-names = "hsi2c";
1625                         status = "disabled";
1626                 };
1627
1628                 hsi2c_3: i2c@14e70000 {
1629                         compatible = "samsung,exynos7-hsi2c";
1630                         reg = <0x14e70000 0x1000>;
1631                         interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1632                         #address-cells = <1>;
1633                         #size-cells = <0>;
1634                         pinctrl-names = "default";
1635                         pinctrl-0 = <&hs_i2c3_bus>;
1636                         clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1637                         clock-names = "hsi2c";
1638                         status = "disabled";
1639                 };
1640
1641                 hsi2c_4: i2c@14ec0000 {
1642                         compatible = "samsung,exynos7-hsi2c";
1643                         reg = <0x14ec0000 0x1000>;
1644                         interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1645                         #address-cells = <1>;
1646                         #size-cells = <0>;
1647                         pinctrl-names = "default";
1648                         pinctrl-0 = <&hs_i2c4_bus>;
1649                         clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1650                         clock-names = "hsi2c";
1651                         status = "disabled";
1652                 };
1653
1654                 hsi2c_5: i2c@14ed0000 {
1655                         compatible = "samsung,exynos7-hsi2c";
1656                         reg = <0x14ed0000 0x1000>;
1657                         interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1658                         #address-cells = <1>;
1659                         #size-cells = <0>;
1660                         pinctrl-names = "default";
1661                         pinctrl-0 = <&hs_i2c5_bus>;
1662                         clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1663                         clock-names = "hsi2c";
1664                         status = "disabled";
1665                 };
1666
1667                 hsi2c_6: i2c@14ee0000 {
1668                         compatible = "samsung,exynos7-hsi2c";
1669                         reg = <0x14ee0000 0x1000>;
1670                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1671                         #address-cells = <1>;
1672                         #size-cells = <0>;
1673                         pinctrl-names = "default";
1674                         pinctrl-0 = <&hs_i2c6_bus>;
1675                         clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1676                         clock-names = "hsi2c";
1677                         status = "disabled";
1678                 };
1679
1680                 hsi2c_7: i2c@14ef0000 {
1681                         compatible = "samsung,exynos7-hsi2c";
1682                         reg = <0x14ef0000 0x1000>;
1683                         interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1684                         #address-cells = <1>;
1685                         #size-cells = <0>;
1686                         pinctrl-names = "default";
1687                         pinctrl-0 = <&hs_i2c7_bus>;
1688                         clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1689                         clock-names = "hsi2c";
1690                         status = "disabled";
1691                 };
1692
1693                 hsi2c_8: i2c@14d90000 {
1694                         compatible = "samsung,exynos7-hsi2c";
1695                         reg = <0x14d90000 0x1000>;
1696                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1697                         #address-cells = <1>;
1698                         #size-cells = <0>;
1699                         pinctrl-names = "default";
1700                         pinctrl-0 = <&hs_i2c8_bus>;
1701                         clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1702                         clock-names = "hsi2c";
1703                         status = "disabled";
1704                 };
1705
1706                 hsi2c_9: i2c@14da0000 {
1707                         compatible = "samsung,exynos7-hsi2c";
1708                         reg = <0x14da0000 0x1000>;
1709                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1710                         #address-cells = <1>;
1711                         #size-cells = <0>;
1712                         pinctrl-names = "default";
1713                         pinctrl-0 = <&hs_i2c9_bus>;
1714                         clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1715                         clock-names = "hsi2c";
1716                         status = "disabled";
1717                 };
1718
1719                 hsi2c_10: i2c@14de0000 {
1720                         compatible = "samsung,exynos7-hsi2c";
1721                         reg = <0x14de0000 0x1000>;
1722                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1723                         #address-cells = <1>;
1724                         #size-cells = <0>;
1725                         pinctrl-names = "default";
1726                         pinctrl-0 = <&hs_i2c10_bus>;
1727                         clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1728                         clock-names = "hsi2c";
1729                         status = "disabled";
1730                 };
1731
1732                 hsi2c_11: i2c@14df0000 {
1733                         compatible = "samsung,exynos7-hsi2c";
1734                         reg = <0x14df0000 0x1000>;
1735                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1736                         #address-cells = <1>;
1737                         #size-cells = <0>;
1738                         pinctrl-names = "default";
1739                         pinctrl-0 = <&hs_i2c11_bus>;
1740                         clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1741                         clock-names = "hsi2c";
1742                         status = "disabled";
1743                 };
1744
1745                 usbdrd30: usbdrd {
1746                         compatible = "samsung,exynos5433-dwusb3";
1747                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1748                                 <&cmu_fsys CLK_SCLK_USBDRD30>,
1749                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1750                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1751                         clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1752                         #address-cells = <1>;
1753                         #size-cells = <1>;
1754                         ranges;
1755                         status = "disabled";
1756
1757                         usbdrd_dwc3: usb@15400000 {
1758                                 compatible = "snps,dwc3";
1759                                 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1760                                         <&cmu_fsys CLK_ACLK_USBDRD30>,
1761                                         <&cmu_fsys CLK_SCLK_USBDRD30>;
1762                                 clock-names = "ref", "bus_early", "suspend";
1763                                 reg = <0x15400000 0x10000>;
1764                                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1765                                 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1766                                 phy-names = "usb2-phy", "usb3-phy";
1767                         };
1768                 };
1769
1770                 usbdrd30_phy: phy@15500000 {
1771                         compatible = "samsung,exynos5433-usbdrd-phy";
1772                         reg = <0x15500000 0x100>;
1773                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1774                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1775                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1776                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
1777                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1778                                         "itp";
1779                         #phy-cells = <1>;
1780                         samsung,pmu-syscon = <&pmu_system_controller>;
1781                         status = "disabled";
1782                 };
1783
1784                 usbhost30_phy: phy@15580000 {
1785                         compatible = "samsung,exynos5433-usbdrd-phy";
1786                         reg = <0x15580000 0x100>;
1787                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1788                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1789                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1790                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
1791                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1792                                         "itp";
1793                         #phy-cells = <1>;
1794                         samsung,pmu-syscon = <&pmu_system_controller>;
1795                         status = "disabled";
1796                 };
1797
1798                 usbhost30: usbhost {
1799                         compatible = "samsung,exynos5433-dwusb3";
1800                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1801                                 <&cmu_fsys CLK_SCLK_USBHOST30>,
1802                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1803                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1804                         clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1805                         #address-cells = <1>;
1806                         #size-cells = <1>;
1807                         ranges;
1808                         status = "disabled";
1809
1810                         usbhost_dwc3: usb@15a00000 {
1811                                 compatible = "snps,dwc3";
1812                                 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1813                                         <&cmu_fsys CLK_ACLK_USBHOST30>,
1814                                         <&cmu_fsys CLK_SCLK_USBHOST30>;
1815                                 clock-names = "ref", "bus_early", "suspend";
1816                                 reg = <0x15a00000 0x10000>;
1817                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1818                                 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1819                                 phy-names = "usb2-phy", "usb3-phy";
1820                         };
1821                 };
1822
1823                 mshc_0: mmc@15540000 {
1824                         compatible = "samsung,exynos7-dw-mshc-smu";
1825                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1826                         #address-cells = <1>;
1827                         #size-cells = <0>;
1828                         reg = <0x15540000 0x2000>;
1829                         clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1830                                 <&cmu_fsys CLK_SCLK_MMC0>;
1831                         clock-names = "biu", "ciu";
1832                         fifo-depth = <0x40>;
1833                         status = "disabled";
1834                 };
1835
1836                 mshc_1: mmc@15550000 {
1837                         compatible = "samsung,exynos7-dw-mshc-smu";
1838                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1839                         #address-cells = <1>;
1840                         #size-cells = <0>;
1841                         reg = <0x15550000 0x2000>;
1842                         clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1843                                 <&cmu_fsys CLK_SCLK_MMC1>;
1844                         clock-names = "biu", "ciu";
1845                         fifo-depth = <0x40>;
1846                         status = "disabled";
1847                 };
1848
1849                 mshc_2: mmc@15560000 {
1850                         compatible = "samsung,exynos7-dw-mshc-smu";
1851                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1852                         #address-cells = <1>;
1853                         #size-cells = <0>;
1854                         reg = <0x15560000 0x2000>;
1855                         clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1856                                 <&cmu_fsys CLK_SCLK_MMC2>;
1857                         clock-names = "biu", "ciu";
1858                         fifo-depth = <0x40>;
1859                         status = "disabled";
1860                 };
1861
1862                 pdma0: dma-controller@15610000 {
1863                         compatible = "arm,pl330", "arm,primecell";
1864                         reg = <0x15610000 0x1000>;
1865                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1866                         clocks = <&cmu_fsys CLK_PDMA0>;
1867                         clock-names = "apb_pclk";
1868                         #dma-cells = <1>;
1869                 };
1870
1871                 pdma1: dma-controller@15600000 {
1872                         compatible = "arm,pl330", "arm,primecell";
1873                         reg = <0x15600000 0x1000>;
1874                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1875                         clocks = <&cmu_fsys CLK_PDMA1>;
1876                         clock-names = "apb_pclk";
1877                         #dma-cells = <1>;
1878                 };
1879
1880                 audio-subsystem@11400000 {
1881                         compatible = "samsung,exynos5433-lpass";
1882                         reg = <0x11400000 0x100>, <0x11500000 0x08>;
1883                         clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1884                         clock-names = "sfr0_ctrl";
1885                         power-domains = <&pd_aud>;
1886                         #address-cells = <1>;
1887                         #size-cells = <1>;
1888                         ranges;
1889
1890                         adma: dma-controller@11420000 {
1891                                 compatible = "arm,pl330", "arm,primecell";
1892                                 reg = <0x11420000 0x1000>;
1893                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1894                                 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1895                                 clock-names = "apb_pclk";
1896                                 #dma-cells = <1>;
1897                                 power-domains = <&pd_aud>;
1898                         };
1899
1900                         i2s0: i2s@11440000 {
1901                                 compatible = "samsung,exynos7-i2s";
1902                                 reg = <0x11440000 0x100>;
1903                                 dmas = <&adma 0>, <&adma 2>;
1904                                 dma-names = "tx", "rx";
1905                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1906                                 #address-cells = <1>;
1907                                 #size-cells = <0>;
1908                                 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1909                                         <&cmu_aud CLK_SCLK_AUD_I2S>,
1910                                         <&cmu_aud CLK_SCLK_I2S_BCLK>;
1911                                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1912                                 #clock-cells = <1>;
1913                                 pinctrl-names = "default";
1914                                 pinctrl-0 = <&i2s0_bus>;
1915                                 power-domains = <&pd_aud>;
1916                                 #sound-dai-cells = <1>;
1917                                 status = "disabled";
1918                         };
1919
1920                         serial_3: serial@11460000 {
1921                                 compatible = "samsung,exynos5433-uart";
1922                                 reg = <0x11460000 0x100>;
1923                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1924                                 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1925                                         <&cmu_aud CLK_SCLK_AUD_UART>;
1926                                 clock-names = "uart", "clk_uart_baud0";
1927                                 pinctrl-names = "default";
1928                                 pinctrl-0 = <&uart_aud_bus>;
1929                                 power-domains = <&pd_aud>;
1930                                 status = "disabled";
1931                         };
1932                 };
1933
1934                 pcie_phy: pcie-phy@15680000 {
1935                         compatible = "samsung,exynos5433-pcie-phy";
1936                         reg = <0x15680000 0x1000>;
1937                         samsung,pmu-syscon = <&pmu_system_controller>;
1938                         samsung,fsys-sysreg = <&syscon_fsys>;
1939                         #phy-cells = <0>;
1940                         status = "disabled";
1941                 };
1942
1943                 pcie: pcie@15700000 {
1944                         compatible = "samsung,exynos5433-pcie";
1945                         reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
1946                               <0x0c000000 0x1000>;
1947                         reg-names = "dbi", "elbi", "config";
1948                         #address-cells = <3>;
1949                         #size-cells = <2>;
1950                         #interrupt-cells = <1>;
1951                         device_type = "pci";
1952                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1953                         clocks = <&cmu_fsys CLK_PCIE>,
1954                                  <&cmu_fsys CLK_PCLK_PCIE_PHY>;
1955                         clock-names = "pcie", "pcie_bus";
1956                         num-lanes = <1>;
1957                         num-viewport = <3>;
1958                         bus-range = <0x00 0xff>;
1959                         phys = <&pcie_phy>;
1960                         ranges = <0x81000000 0 0          0x0c001000 0 0x00010000>,
1961                                  <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
1962                         status = "disabled";
1963                 };
1964         };
1965
1966         timer: timer {
1967                 compatible = "arm,armv8-timer";
1968                 interrupts = <GIC_PPI 13
1969                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1970                         <GIC_PPI 14
1971                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1972                         <GIC_PPI 11
1973                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1974                         <GIC_PPI 10
1975                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1976         };
1977 };
1978
1979 #include "exynos5433-bus.dtsi"
1980 #include "exynos5433-pinctrl.dtsi"
1981 #include "exynos5433-tmu.dtsi"