2 * Samsung's Exynos5433 SoC device tree source
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * Samsung's Exynos5433 SoC device nodes are listed in this file.
7 * Exynos5433 based board files can include this file and provide
8 * values for board specific bindings.
10 * Note: This file does not include device nodes for all the controllers in
11 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
12 * additional nodes can be added to this file.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <dt-bindings/clock/exynos5433.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 compatible = "samsung,exynos5433";
27 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
38 clock-frequency = <1300000000>;
39 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
40 clock-names = "apolloclk";
41 operating-points-v2 = <&cluster_a53_opp_table>;
47 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
50 clock-frequency = <1300000000>;
51 operating-points-v2 = <&cluster_a53_opp_table>;
57 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
60 clock-frequency = <1300000000>;
61 operating-points-v2 = <&cluster_a53_opp_table>;
67 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
70 clock-frequency = <1300000000>;
71 operating-points-v2 = <&cluster_a53_opp_table>;
77 compatible = "arm,cortex-a57", "arm,armv8";
78 enable-method = "psci";
80 clock-frequency = <1900000000>;
81 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
82 clock-names = "atlasclk";
83 operating-points-v2 = <&cluster_a57_opp_table>;
89 compatible = "arm,cortex-a57", "arm,armv8";
90 enable-method = "psci";
92 clock-frequency = <1900000000>;
93 operating-points-v2 = <&cluster_a57_opp_table>;
99 compatible = "arm,cortex-a57", "arm,armv8";
100 enable-method = "psci";
102 clock-frequency = <1900000000>;
103 operating-points-v2 = <&cluster_a57_opp_table>;
104 #cooling-cells = <2>;
109 compatible = "arm,cortex-a57", "arm,armv8";
110 enable-method = "psci";
112 clock-frequency = <1900000000>;
113 operating-points-v2 = <&cluster_a57_opp_table>;
114 #cooling-cells = <2>;
118 cluster_a53_opp_table: opp_table0 {
119 compatible = "operating-points-v2";
123 opp-hz = /bits/ 64 <400000000>;
124 opp-microvolt = <900000>;
127 opp-hz = /bits/ 64 <500000000>;
128 opp-microvolt = <925000>;
131 opp-hz = /bits/ 64 <600000000>;
132 opp-microvolt = <950000>;
135 opp-hz = /bits/ 64 <700000000>;
136 opp-microvolt = <975000>;
139 opp-hz = /bits/ 64 <800000000>;
140 opp-microvolt = <1000000>;
143 opp-hz = /bits/ 64 <900000000>;
144 opp-microvolt = <1050000>;
147 opp-hz = /bits/ 64 <1000000000>;
148 opp-microvolt = <1075000>;
151 opp-hz = /bits/ 64 <1100000000>;
152 opp-microvolt = <1112500>;
155 opp-hz = /bits/ 64 <1200000000>;
156 opp-microvolt = <1112500>;
159 opp-hz = /bits/ 64 <1300000000>;
160 opp-microvolt = <1150000>;
164 cluster_a57_opp_table: opp_table1 {
165 compatible = "operating-points-v2";
169 opp-hz = /bits/ 64 <500000000>;
170 opp-microvolt = <900000>;
173 opp-hz = /bits/ 64 <600000000>;
174 opp-microvolt = <900000>;
177 opp-hz = /bits/ 64 <700000000>;
178 opp-microvolt = <912500>;
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <912500>;
185 opp-hz = /bits/ 64 <900000000>;
186 opp-microvolt = <937500>;
189 opp-hz = /bits/ 64 <1000000000>;
190 opp-microvolt = <975000>;
193 opp-hz = /bits/ 64 <1100000000>;
194 opp-microvolt = <1012500>;
197 opp-hz = /bits/ 64 <1200000000>;
198 opp-microvolt = <1037500>;
201 opp-hz = /bits/ 64 <1300000000>;
202 opp-microvolt = <1062500>;
205 opp-hz = /bits/ 64 <1400000000>;
206 opp-microvolt = <1087500>;
209 opp-hz = /bits/ 64 <1500000000>;
210 opp-microvolt = <1125000>;
213 opp-hz = /bits/ 64 <1600000000>;
214 opp-microvolt = <1137500>;
217 opp-hz = /bits/ 64 <1700000000>;
218 opp-microvolt = <1175000>;
221 opp-hz = /bits/ 64 <1800000000>;
222 opp-microvolt = <1212500>;
225 opp-hz = /bits/ 64 <1900000000>;
226 opp-microvolt = <1262500>;
231 compatible = "arm,psci";
233 cpu_off = <0x84000002>;
234 cpu_on = <0xC4000003>;
237 reboot: syscon-reboot {
238 compatible = "syscon-reboot";
239 regmap = <&pmu_system_controller>;
240 offset = <0x400>; /* SWRESET */
245 compatible = "simple-bus";
246 #address-cells = <1>;
248 ranges = <0x0 0x0 0x0 0x18000000>;
251 compatible = "samsung,exynos4210-chipid";
252 reg = <0x10000000 0x100>;
256 compatible = "fixed-clock";
257 clock-output-names = "oscclk";
261 cmu_top: clock-controller@10030000 {
262 compatible = "samsung,exynos5433-cmu-top";
263 reg = <0x10030000 0x1000>;
266 clock-names = "oscclk",
271 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
272 <&cmu_mif CLK_SCLK_MFC_PLL>,
273 <&cmu_mif CLK_SCLK_BUS_PLL>;
276 cmu_cpif: clock-controller@10fc0000 {
277 compatible = "samsung,exynos5433-cmu-cpif";
278 reg = <0x10fc0000 0x1000>;
281 clock-names = "oscclk";
285 cmu_mif: clock-controller@105b0000 {
286 compatible = "samsung,exynos5433-cmu-mif";
287 reg = <0x105b0000 0x2000>;
290 clock-names = "oscclk",
293 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
296 cmu_peric: clock-controller@14c80000 {
297 compatible = "samsung,exynos5433-cmu-peric";
298 reg = <0x14c80000 0x1000>;
302 cmu_peris: clock-controller@10040000 {
303 compatible = "samsung,exynos5433-cmu-peris";
304 reg = <0x10040000 0x1000>;
308 cmu_fsys: clock-controller@156e0000 {
309 compatible = "samsung,exynos5433-cmu-fsys";
310 reg = <0x156e0000 0x1000>;
313 clock-names = "oscclk",
316 "sclk_pcie_100_fsys",
317 "sclk_ufsunipro_fsys",
321 "sclk_usbhost30_fsys",
322 "sclk_usbdrd30_fsys";
324 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
325 <&cmu_top CLK_ACLK_FSYS_200>,
326 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
327 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
328 <&cmu_top CLK_SCLK_MMC2_FSYS>,
329 <&cmu_top CLK_SCLK_MMC1_FSYS>,
330 <&cmu_top CLK_SCLK_MMC0_FSYS>,
331 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
332 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
335 cmu_g2d: clock-controller@12460000 {
336 compatible = "samsung,exynos5433-cmu-g2d";
337 reg = <0x12460000 0x1000>;
340 clock-names = "oscclk",
344 <&cmu_top CLK_ACLK_G2D_266>,
345 <&cmu_top CLK_ACLK_G2D_400>;
348 cmu_disp: clock-controller@13b90000 {
349 compatible = "samsung,exynos5433-cmu-disp";
350 reg = <0x13b90000 0x1000>;
353 clock-names = "oscclk",
357 "sclk_decon_tv_eclk_disp",
358 "sclk_decon_vclk_disp",
359 "sclk_decon_eclk_disp",
360 "sclk_decon_tv_vclk_disp",
363 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
364 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
365 <&cmu_mif CLK_SCLK_DSD_DISP>,
366 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
367 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
368 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
369 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
370 <&cmu_mif CLK_ACLK_DISP_333>;
373 cmu_aud: clock-controller@114c0000 {
374 compatible = "samsung,exynos5433-cmu-aud";
375 reg = <0x114c0000 0x1000>;
377 clock-names = "oscclk", "fout_aud_pll";
378 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
381 cmu_bus0: clock-controller@13600000 {
382 compatible = "samsung,exynos5433-cmu-bus0";
383 reg = <0x13600000 0x1000>;
386 clock-names = "aclk_bus0_400";
387 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
390 cmu_bus1: clock-controller@14800000 {
391 compatible = "samsung,exynos5433-cmu-bus1";
392 reg = <0x14800000 0x1000>;
395 clock-names = "aclk_bus1_400";
396 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
399 cmu_bus2: clock-controller@13400000 {
400 compatible = "samsung,exynos5433-cmu-bus2";
401 reg = <0x13400000 0x1000>;
404 clock-names = "oscclk", "aclk_bus2_400";
405 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
408 cmu_g3d: clock-controller@14aa0000 {
409 compatible = "samsung,exynos5433-cmu-g3d";
410 reg = <0x14aa0000 0x2000>;
413 clock-names = "oscclk", "aclk_g3d_400";
414 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
417 cmu_gscl: clock-controller@13cf0000 {
418 compatible = "samsung,exynos5433-cmu-gscl";
419 reg = <0x13cf0000 0x1000>;
422 clock-names = "oscclk",
426 <&cmu_top CLK_ACLK_GSCL_111>,
427 <&cmu_top CLK_ACLK_GSCL_333>;
430 cmu_apollo: clock-controller@11900000 {
431 compatible = "samsung,exynos5433-cmu-apollo";
432 reg = <0x11900000 0x2000>;
435 clock-names = "oscclk", "sclk_bus_pll_apollo";
436 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
439 cmu_atlas: clock-controller@11800000 {
440 compatible = "samsung,exynos5433-cmu-atlas";
441 reg = <0x11800000 0x2000>;
444 clock-names = "oscclk", "sclk_bus_pll_atlas";
445 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
448 cmu_mscl: clock-controller@105d0000 {
449 compatible = "samsung,exynos5433-cmu-mscl";
450 reg = <0x150d0000 0x1000>;
453 clock-names = "oscclk",
457 <&cmu_top CLK_SCLK_JPEG_MSCL>,
458 <&cmu_top CLK_ACLK_MSCL_400>;
461 cmu_mfc: clock-controller@15280000 {
462 compatible = "samsung,exynos5433-cmu-mfc";
463 reg = <0x15280000 0x1000>;
466 clock-names = "oscclk", "aclk_mfc_400";
467 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
470 cmu_hevc: clock-controller@14f80000 {
471 compatible = "samsung,exynos5433-cmu-hevc";
472 reg = <0x14f80000 0x1000>;
475 clock-names = "oscclk", "aclk_hevc_400";
476 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
479 cmu_isp: clock-controller@146d0000 {
480 compatible = "samsung,exynos5433-cmu-isp";
481 reg = <0x146d0000 0x1000>;
484 clock-names = "oscclk",
488 <&cmu_top CLK_ACLK_ISP_DIS_400>,
489 <&cmu_top CLK_ACLK_ISP_400>;
492 cmu_cam0: clock-controller@120d0000 {
493 compatible = "samsung,exynos5433-cmu-cam0";
494 reg = <0x120d0000 0x1000>;
497 clock-names = "oscclk",
502 <&cmu_top CLK_ACLK_CAM0_333>,
503 <&cmu_top CLK_ACLK_CAM0_400>,
504 <&cmu_top CLK_ACLK_CAM0_552>;
507 cmu_cam1: clock-controller@145d0000 {
508 compatible = "samsung,exynos5433-cmu-cam1";
509 reg = <0x145d0000 0x1000>;
512 clock-names = "oscclk",
513 "sclk_isp_uart_cam1",
514 "sclk_isp_spi1_cam1",
515 "sclk_isp_spi0_cam1",
520 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
521 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
522 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
523 <&cmu_top CLK_ACLK_CAM1_333>,
524 <&cmu_top CLK_ACLK_CAM1_400>,
525 <&cmu_top CLK_ACLK_CAM1_552>;
528 tmu_atlas0: tmu@10060000 {
529 compatible = "samsung,exynos5433-tmu";
530 reg = <0x10060000 0x200>;
531 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
533 <&cmu_peris CLK_SCLK_TMU0>;
534 clock-names = "tmu_apbif", "tmu_sclk";
535 #include "exynos5433-tmu-sensor-conf.dtsi"
539 tmu_atlas1: tmu@10068000 {
540 compatible = "samsung,exynos5433-tmu";
541 reg = <0x10068000 0x200>;
542 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
544 <&cmu_peris CLK_SCLK_TMU0>;
545 clock-names = "tmu_apbif", "tmu_sclk";
546 #include "exynos5433-tmu-sensor-conf.dtsi"
550 tmu_g3d: tmu@10070000 {
551 compatible = "samsung,exynos5433-tmu";
552 reg = <0x10070000 0x200>;
553 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
555 <&cmu_peris CLK_SCLK_TMU1>;
556 clock-names = "tmu_apbif", "tmu_sclk";
557 #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
561 tmu_apollo: tmu@10078000 {
562 compatible = "samsung,exynos5433-tmu";
563 reg = <0x10078000 0x200>;
564 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
566 <&cmu_peris CLK_SCLK_TMU1>;
567 clock-names = "tmu_apbif", "tmu_sclk";
568 #include "exynos5433-tmu-sensor-conf.dtsi"
572 tmu_isp: tmu@1007c000 {
573 compatible = "samsung,exynos5433-tmu";
574 reg = <0x1007c000 0x200>;
575 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
577 <&cmu_peris CLK_SCLK_TMU1>;
578 clock-names = "tmu_apbif", "tmu_sclk";
579 #include "exynos5433-tmu-sensor-conf.dtsi"
584 compatible = "samsung,exynos4210-mct";
585 reg = <0x101c0000 0x800>;
586 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
599 clock-names = "fin_pll", "mct";
602 ppmu_d0_cpu: ppmu@10480000 {
603 compatible = "samsung,exynos-ppmu-v2";
604 reg = <0x10480000 0x2000>;
608 ppmu_d0_general: ppmu@10490000 {
609 compatible = "samsung,exynos-ppmu-v2";
610 reg = <0x10490000 0x2000>;
614 ppmu_d1_cpu: ppmu@104b0000 {
615 compatible = "samsung,exynos-ppmu-v2";
616 reg = <0x104b0000 0x2000>;
620 ppmu_d1_general: ppmu@104c0000 {
621 compatible = "samsung,exynos-ppmu-v2";
622 reg = <0x104c0000 0x2000>;
626 pinctrl_alive: pinctrl@10580000 {
627 compatible = "samsung,exynos5433-pinctrl";
628 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
630 wakeup-interrupt-controller {
631 compatible = "samsung,exynos7-wakeup-eint";
632 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
636 pinctrl_aud: pinctrl@114b0000 {
637 compatible = "samsung,exynos5433-pinctrl";
638 reg = <0x114b0000 0x1000>;
639 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
642 pinctrl_cpif: pinctrl@10fe0000 {
643 compatible = "samsung,exynos5433-pinctrl";
644 reg = <0x10fe0000 0x1000>;
645 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
648 pinctrl_ese: pinctrl@14ca0000 {
649 compatible = "samsung,exynos5433-pinctrl";
650 reg = <0x14ca0000 0x1000>;
651 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
654 pinctrl_finger: pinctrl@14cb0000 {
655 compatible = "samsung,exynos5433-pinctrl";
656 reg = <0x14cb0000 0x1000>;
657 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
660 pinctrl_fsys: pinctrl@15690000 {
661 compatible = "samsung,exynos5433-pinctrl";
662 reg = <0x15690000 0x1000>;
663 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
666 pinctrl_imem: pinctrl@11090000 {
667 compatible = "samsung,exynos5433-pinctrl";
668 reg = <0x11090000 0x1000>;
669 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
672 pinctrl_nfc: pinctrl@14cd0000 {
673 compatible = "samsung,exynos5433-pinctrl";
674 reg = <0x14cd0000 0x1000>;
675 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
678 pinctrl_peric: pinctrl@14cc0000 {
679 compatible = "samsung,exynos5433-pinctrl";
680 reg = <0x14cc0000 0x1100>;
681 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
684 pinctrl_touch: pinctrl@14ce0000 {
685 compatible = "samsung,exynos5433-pinctrl";
686 reg = <0x14ce0000 0x1100>;
687 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
690 pmu_system_controller: system-controller@105c0000 {
691 compatible = "samsung,exynos5433-pmu", "syscon";
692 reg = <0x105c0000 0x5008>;
694 clock-names = "clkout16";
698 gic: interrupt-controller@11001000 {
699 compatible = "arm,gic-400";
700 #interrupt-cells = <3>;
701 interrupt-controller;
702 reg = <0x11001000 0x1000>,
706 interrupts = <GIC_PPI 9 0xf04>;
709 mipi_phy: video-phy {
710 compatible = "samsung,exynos5433-mipi-video-phy";
712 samsung,pmu-syscon = <&pmu_system_controller>;
713 samsung,cam0-sysreg = <&syscon_cam0>;
714 samsung,cam1-sysreg = <&syscon_cam1>;
715 samsung,disp-sysreg = <&syscon_disp>;
718 decon: decon@13800000 {
719 compatible = "samsung,exynos5433-decon";
720 reg = <0x13800000 0x2104>;
721 clocks = <&cmu_disp CLK_PCLK_DECON>,
722 <&cmu_disp CLK_ACLK_DECON>,
723 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
724 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
725 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
726 <&cmu_disp CLK_SCLK_DECON_VCLK>,
727 <&cmu_disp CLK_SCLK_DECON_ECLK>;
728 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
729 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
730 "sclk_decon_vclk", "sclk_decon_eclk";
731 interrupt-names = "fifo", "vsync", "lcd_sys";
732 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
735 samsung,disp-sysreg = <&syscon_disp>;
737 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
738 iommu-names = "m0", "m1";
741 #address-cells = <1>;
746 decon_to_mic: endpoint {
754 decon_tv: decon@13880000 {
755 compatible = "samsung,exynos5433-decon-tv";
756 reg = <0x13880000 0x20b8>;
757 clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
758 <&cmu_disp CLK_ACLK_DECON_TV>,
759 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
760 <&cmu_disp CLK_ACLK_XIU_TV0X>,
761 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
762 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
763 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
764 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
765 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
766 "sclk_decon_vclk", "sclk_decon_eclk";
767 samsung,disp-sysreg = <&syscon_disp>;
768 interrupt-names = "fifo", "vsync", "lcd_sys";
769 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
773 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
774 iommu-names = "m0", "m1";
778 compatible = "samsung,exynos5433-mipi-dsi";
779 reg = <0x13900000 0xC0>;
780 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
781 phys = <&mipi_phy 1>;
783 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
784 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
785 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
786 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
787 <&cmu_disp CLK_SCLK_DSIM0>;
788 clock-names = "bus_clk",
789 "phyclk_mipidphy0_bitclkdiv8",
790 "phyclk_mipidphy0_rxclkesc0",
791 "sclk_rgb_vclk_to_dsim0",
794 #address-cells = <1>;
798 #address-cells = <1>;
803 dsi_to_mic: endpoint {
804 remote-endpoint = <&mic_to_dsi>;
811 compatible = "samsung,exynos5433-mic";
812 reg = <0x13930000 0x48>;
813 clocks = <&cmu_disp CLK_PCLK_MIC0>,
814 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
815 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
816 samsung,disp-syscon = <&syscon_disp>;
820 #address-cells = <1>;
825 mic_to_decon: endpoint {
833 mic_to_dsi: endpoint {
834 remote-endpoint = <&dsi_to_mic>;
840 hdmi: hdmi@13970000 {
841 compatible = "samsung,exynos5433-hdmi";
842 reg = <0x13970000 0x70000>;
843 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&cmu_disp CLK_PCLK_HDMI>,
845 <&cmu_disp CLK_PCLK_HDMIPHY>,
846 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
847 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
848 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
849 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
850 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
851 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
852 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
853 clock-names = "hdmi_pclk", "hdmi_i_pclk",
854 "i_tmds_clk", "i_pixel_clk",
855 "tmds_clko", "tmds_clko_user",
856 "pixel_clko", "pixel_clko_user",
857 "oscclk", "i_spdif_clk";
860 samsung,syscon-phandle = <&pmu_system_controller>;
861 samsung,sysreg-phandle = <&syscon_disp>;
865 hdmiphy: hdmiphy@13af0000 {
866 reg = <0x13af0000 0x80>;
869 syscon_disp: syscon@13b80000 {
870 compatible = "syscon";
871 reg = <0x13b80000 0x1010>;
874 syscon_cam0: syscon@120f0000 {
875 compatible = "syscon";
876 reg = <0x120f0000 0x1020>;
879 syscon_cam1: syscon@145f0000 {
880 compatible = "syscon";
881 reg = <0x145f0000 0x1038>;
884 gsc_0: video-scaler@13C00000 {
885 compatible = "samsung,exynos5433-gsc";
886 reg = <0x13c00000 0x1000>;
887 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
888 clock-names = "pclk", "aclk", "aclk_xiu",
890 clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
891 <&cmu_gscl CLK_ACLK_GSCL0>,
892 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
893 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
894 iommus = <&sysmmu_gscl0>;
897 gsc_1: video-scaler@13C10000 {
898 compatible = "samsung,exynos5433-gsc";
899 reg = <0x13c10000 0x1000>;
900 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
901 clock-names = "pclk", "aclk", "aclk_xiu",
903 clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
904 <&cmu_gscl CLK_ACLK_GSCL1>,
905 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
906 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
907 iommus = <&sysmmu_gscl1>;
910 gsc_2: video-scaler@13C20000 {
911 compatible = "samsung,exynos5433-gsc";
912 reg = <0x13c20000 0x1000>;
913 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
914 clock-names = "pclk", "aclk", "aclk_xiu",
916 clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
917 <&cmu_gscl CLK_ACLK_GSCL2>,
918 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
919 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
920 iommus = <&sysmmu_gscl2>;
923 jpeg: codec@15020000 {
924 compatible = "samsung,exynos5433-jpeg";
925 reg = <0x15020000 0x10000>;
926 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
927 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
928 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
929 <&cmu_mscl CLK_ACLK_JPEG>,
930 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
931 <&cmu_mscl CLK_SCLK_JPEG>;
932 iommus = <&sysmmu_jpeg>;
935 mfc: codec@152E0000 {
936 compatible = "samsung,exynos5433-mfc";
937 reg = <0x152E0000 0x10000>;
938 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
939 clock-names = "pclk", "aclk", "aclk_xiu";
940 clocks = <&cmu_mfc CLK_PCLK_MFC>,
941 <&cmu_mfc CLK_ACLK_MFC>,
942 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
943 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
944 iommu-names = "left", "right";
947 sysmmu_decon0x: sysmmu@13a00000 {
948 compatible = "samsung,exynos-sysmmu";
949 reg = <0x13a00000 0x1000>;
950 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
951 clock-names = "pclk", "aclk";
952 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
953 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
957 sysmmu_decon1x: sysmmu@13a10000 {
958 compatible = "samsung,exynos-sysmmu";
959 reg = <0x13a10000 0x1000>;
960 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
961 clock-names = "pclk", "aclk";
962 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
963 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
967 sysmmu_tv0x: sysmmu@13a20000 {
968 compatible = "samsung,exynos-sysmmu";
969 reg = <0x13a20000 0x1000>;
970 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
971 clock-names = "pclk", "aclk";
972 clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
973 <&cmu_disp CLK_ACLK_SMMU_TV0X>;
977 sysmmu_tv1x: sysmmu@13a30000 {
978 compatible = "samsung,exynos-sysmmu";
979 reg = <0x13a30000 0x1000>;
980 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
981 clock-names = "pclk", "aclk";
982 clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
983 <&cmu_disp CLK_ACLK_SMMU_TV1X>;
987 sysmmu_gscl0: sysmmu@13c80000 {
988 compatible = "samsung,exynos-sysmmu";
989 reg = <0x13C80000 0x1000>;
990 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
991 clock-names = "aclk", "pclk";
992 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
993 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
997 sysmmu_gscl1: sysmmu@13c90000 {
998 compatible = "samsung,exynos-sysmmu";
999 reg = <0x13C90000 0x1000>;
1000 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1001 clock-names = "aclk", "pclk";
1002 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1003 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1007 sysmmu_gscl2: sysmmu@13ca0000 {
1008 compatible = "samsung,exynos-sysmmu";
1009 reg = <0x13CA0000 0x1000>;
1010 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1011 clock-names = "aclk", "pclk";
1012 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1013 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1017 sysmmu_jpeg: sysmmu@15060000 {
1018 compatible = "samsung,exynos-sysmmu";
1019 reg = <0x15060000 0x1000>;
1020 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1021 clock-names = "pclk", "aclk";
1022 clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
1023 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
1027 sysmmu_mfc_0: sysmmu@15200000 {
1028 compatible = "samsung,exynos-sysmmu";
1029 reg = <0x15200000 0x1000>;
1030 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1031 clock-names = "pclk", "aclk";
1032 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
1033 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
1037 sysmmu_mfc_1: sysmmu@15210000 {
1038 compatible = "samsung,exynos-sysmmu";
1039 reg = <0x15210000 0x1000>;
1040 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1041 clock-names = "pclk", "aclk";
1042 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
1043 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
1047 serial_0: serial@14c10000 {
1048 compatible = "samsung,exynos5433-uart";
1049 reg = <0x14c10000 0x100>;
1050 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&cmu_peric CLK_PCLK_UART0>,
1052 <&cmu_peric CLK_SCLK_UART0>;
1053 clock-names = "uart", "clk_uart_baud0";
1054 pinctrl-names = "default";
1055 pinctrl-0 = <&uart0_bus>;
1056 status = "disabled";
1059 serial_1: serial@14c20000 {
1060 compatible = "samsung,exynos5433-uart";
1061 reg = <0x14c20000 0x100>;
1062 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&cmu_peric CLK_PCLK_UART1>,
1064 <&cmu_peric CLK_SCLK_UART1>;
1065 clock-names = "uart", "clk_uart_baud0";
1066 pinctrl-names = "default";
1067 pinctrl-0 = <&uart1_bus>;
1068 status = "disabled";
1071 serial_2: serial@14c30000 {
1072 compatible = "samsung,exynos5433-uart";
1073 reg = <0x14c30000 0x100>;
1074 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&cmu_peric CLK_PCLK_UART2>,
1076 <&cmu_peric CLK_SCLK_UART2>;
1077 clock-names = "uart", "clk_uart_baud0";
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&uart2_bus>;
1080 status = "disabled";
1083 spi_0: spi@14d20000 {
1084 compatible = "samsung,exynos5433-spi";
1085 reg = <0x14d20000 0x100>;
1086 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1087 dmas = <&pdma0 9>, <&pdma0 8>;
1088 dma-names = "tx", "rx";
1089 #address-cells = <1>;
1091 clocks = <&cmu_peric CLK_PCLK_SPI0>,
1092 <&cmu_peric CLK_SCLK_SPI0>,
1093 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1094 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1095 samsung,spi-src-clk = <0>;
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&spi0_bus>;
1099 status = "disabled";
1102 spi_1: spi@14d30000 {
1103 compatible = "samsung,exynos5433-spi";
1104 reg = <0x14d30000 0x100>;
1105 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1106 dmas = <&pdma0 11>, <&pdma0 10>;
1107 dma-names = "tx", "rx";
1108 #address-cells = <1>;
1110 clocks = <&cmu_peric CLK_PCLK_SPI1>,
1111 <&cmu_peric CLK_SCLK_SPI1>,
1112 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1113 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1114 samsung,spi-src-clk = <0>;
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&spi1_bus>;
1118 status = "disabled";
1121 spi_2: spi@14d40000 {
1122 compatible = "samsung,exynos5433-spi";
1123 reg = <0x14d40000 0x100>;
1124 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1125 dmas = <&pdma0 13>, <&pdma0 12>;
1126 dma-names = "tx", "rx";
1127 #address-cells = <1>;
1129 clocks = <&cmu_peric CLK_PCLK_SPI2>,
1130 <&cmu_peric CLK_SCLK_SPI2>,
1131 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1132 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1133 samsung,spi-src-clk = <0>;
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&spi2_bus>;
1137 status = "disabled";
1140 spi_3: spi@14d50000 {
1141 compatible = "samsung,exynos5433-spi";
1142 reg = <0x14d50000 0x100>;
1143 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1144 dmas = <&pdma0 23>, <&pdma0 22>;
1145 dma-names = "tx", "rx";
1146 #address-cells = <1>;
1148 clocks = <&cmu_peric CLK_PCLK_SPI3>,
1149 <&cmu_peric CLK_SCLK_SPI3>,
1150 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1151 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1152 samsung,spi-src-clk = <0>;
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&spi3_bus>;
1156 status = "disabled";
1159 spi_4: spi@14d00000 {
1160 compatible = "samsung,exynos5433-spi";
1161 reg = <0x14d00000 0x100>;
1162 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1163 dmas = <&pdma0 25>, <&pdma0 24>;
1164 dma-names = "tx", "rx";
1165 #address-cells = <1>;
1167 clocks = <&cmu_peric CLK_PCLK_SPI4>,
1168 <&cmu_peric CLK_SCLK_SPI4>,
1169 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1170 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1171 samsung,spi-src-clk = <0>;
1172 pinctrl-names = "default";
1173 pinctrl-0 = <&spi4_bus>;
1175 status = "disabled";
1179 compatible = "samsung,exynos7-adc";
1180 reg = <0x14d10000 0x100>;
1181 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1182 clock-names = "adc";
1183 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1184 #io-channel-cells = <1>;
1186 status = "disabled";
1190 compatible = "samsung,exynos4210-pwm";
1191 reg = <0x14dd0000 0x100>;
1192 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1197 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1198 clocks = <&cmu_peric CLK_PCLK_PWM>;
1199 clock-names = "timers";
1201 status = "disabled";
1204 hsi2c_0: hsi2c@14e40000 {
1205 compatible = "samsung,exynos7-hsi2c";
1206 reg = <0x14e40000 0x1000>;
1207 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1208 #address-cells = <1>;
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&hs_i2c0_bus>;
1212 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1213 clock-names = "hsi2c";
1214 status = "disabled";
1217 hsi2c_1: hsi2c@14e50000 {
1218 compatible = "samsung,exynos7-hsi2c";
1219 reg = <0x14e50000 0x1000>;
1220 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1221 #address-cells = <1>;
1223 pinctrl-names = "default";
1224 pinctrl-0 = <&hs_i2c1_bus>;
1225 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1226 clock-names = "hsi2c";
1227 status = "disabled";
1230 hsi2c_2: hsi2c@14e60000 {
1231 compatible = "samsung,exynos7-hsi2c";
1232 reg = <0x14e60000 0x1000>;
1233 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1234 #address-cells = <1>;
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&hs_i2c2_bus>;
1238 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1239 clock-names = "hsi2c";
1240 status = "disabled";
1243 hsi2c_3: hsi2c@14e70000 {
1244 compatible = "samsung,exynos7-hsi2c";
1245 reg = <0x14e70000 0x1000>;
1246 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1247 #address-cells = <1>;
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&hs_i2c3_bus>;
1251 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1252 clock-names = "hsi2c";
1253 status = "disabled";
1256 hsi2c_4: hsi2c@14ec0000 {
1257 compatible = "samsung,exynos7-hsi2c";
1258 reg = <0x14ec0000 0x1000>;
1259 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1260 #address-cells = <1>;
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&hs_i2c4_bus>;
1264 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1265 clock-names = "hsi2c";
1266 status = "disabled";
1269 hsi2c_5: hsi2c@14ed0000 {
1270 compatible = "samsung,exynos7-hsi2c";
1271 reg = <0x14ed0000 0x1000>;
1272 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1273 #address-cells = <1>;
1275 pinctrl-names = "default";
1276 pinctrl-0 = <&hs_i2c5_bus>;
1277 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1278 clock-names = "hsi2c";
1279 status = "disabled";
1282 hsi2c_6: hsi2c@14ee0000 {
1283 compatible = "samsung,exynos7-hsi2c";
1284 reg = <0x14ee0000 0x1000>;
1285 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1286 #address-cells = <1>;
1288 pinctrl-names = "default";
1289 pinctrl-0 = <&hs_i2c6_bus>;
1290 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1291 clock-names = "hsi2c";
1292 status = "disabled";
1295 hsi2c_7: hsi2c@14ef0000 {
1296 compatible = "samsung,exynos7-hsi2c";
1297 reg = <0x14ef0000 0x1000>;
1298 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1299 #address-cells = <1>;
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&hs_i2c7_bus>;
1303 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1304 clock-names = "hsi2c";
1305 status = "disabled";
1308 hsi2c_8: hsi2c@14d90000 {
1309 compatible = "samsung,exynos7-hsi2c";
1310 reg = <0x14d90000 0x1000>;
1311 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1312 #address-cells = <1>;
1314 pinctrl-names = "default";
1315 pinctrl-0 = <&hs_i2c8_bus>;
1316 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1317 clock-names = "hsi2c";
1318 status = "disabled";
1321 hsi2c_9: hsi2c@14da0000 {
1322 compatible = "samsung,exynos7-hsi2c";
1323 reg = <0x14da0000 0x1000>;
1324 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1325 #address-cells = <1>;
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&hs_i2c9_bus>;
1329 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1330 clock-names = "hsi2c";
1331 status = "disabled";
1334 hsi2c_10: hsi2c@14de0000 {
1335 compatible = "samsung,exynos7-hsi2c";
1336 reg = <0x14de0000 0x1000>;
1337 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1338 #address-cells = <1>;
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&hs_i2c10_bus>;
1342 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1343 clock-names = "hsi2c";
1344 status = "disabled";
1347 hsi2c_11: hsi2c@14df0000 {
1348 compatible = "samsung,exynos7-hsi2c";
1349 reg = <0x14df0000 0x1000>;
1350 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1351 #address-cells = <1>;
1353 pinctrl-names = "default";
1354 pinctrl-0 = <&hs_i2c11_bus>;
1355 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1356 clock-names = "hsi2c";
1357 status = "disabled";
1361 compatible = "samsung,exynos5250-dwusb3";
1362 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1363 <&cmu_fsys CLK_SCLK_USBDRD30>;
1364 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1365 #address-cells = <1>;
1368 status = "disabled";
1370 usbdrd_dwc3: dwc3@15400000 {
1371 compatible = "snps,dwc3";
1372 reg = <0x15400000 0x10000>;
1373 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1374 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1375 phy-names = "usb2-phy", "usb3-phy";
1379 usbdrd30_phy: phy@15500000 {
1380 compatible = "samsung,exynos5433-usbdrd-phy";
1381 reg = <0x15500000 0x100>;
1382 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1383 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1384 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1385 <&cmu_fsys CLK_SCLK_USBDRD30>;
1386 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1389 samsung,pmu-syscon = <&pmu_system_controller>;
1390 status = "disabled";
1393 usbhost30_phy: phy@15580000 {
1394 compatible = "samsung,exynos5433-usbdrd-phy";
1395 reg = <0x15580000 0x100>;
1396 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1397 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1398 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1399 <&cmu_fsys CLK_SCLK_USBHOST30>;
1400 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1403 samsung,pmu-syscon = <&pmu_system_controller>;
1404 status = "disabled";
1407 usbhost30: usbhost {
1408 compatible = "samsung,exynos5250-dwusb3";
1409 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1410 <&cmu_fsys CLK_SCLK_USBHOST30>;
1411 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1412 #address-cells = <1>;
1415 status = "disabled";
1417 usbhost_dwc3: dwc3@15a00000 {
1418 compatible = "snps,dwc3";
1419 reg = <0x15a00000 0x10000>;
1420 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1421 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1422 phy-names = "usb2-phy", "usb3-phy";
1426 mshc_0: mshc@15540000 {
1427 compatible = "samsung,exynos7-dw-mshc-smu";
1428 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1429 #address-cells = <1>;
1431 reg = <0x15540000 0x2000>;
1432 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1433 <&cmu_fsys CLK_SCLK_MMC0>;
1434 clock-names = "biu", "ciu";
1435 fifo-depth = <0x40>;
1436 status = "disabled";
1439 mshc_1: mshc@15550000 {
1440 compatible = "samsung,exynos7-dw-mshc-smu";
1441 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1442 #address-cells = <1>;
1444 reg = <0x15550000 0x2000>;
1445 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1446 <&cmu_fsys CLK_SCLK_MMC1>;
1447 clock-names = "biu", "ciu";
1448 fifo-depth = <0x40>;
1449 status = "disabled";
1452 mshc_2: mshc@15560000 {
1453 compatible = "samsung,exynos7-dw-mshc-smu";
1454 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cells = <1>;
1457 reg = <0x15560000 0x2000>;
1458 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1459 <&cmu_fsys CLK_SCLK_MMC2>;
1460 clock-names = "biu", "ciu";
1461 fifo-depth = <0x40>;
1462 status = "disabled";
1466 compatible = "simple-bus";
1467 #address-cells = <1>;
1471 pdma0: pdma@15610000 {
1472 compatible = "arm,pl330", "arm,primecell";
1473 reg = <0x15610000 0x1000>;
1474 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1475 clocks = <&cmu_fsys CLK_PDMA0>;
1476 clock-names = "apb_pclk";
1478 #dma-channels = <8>;
1479 #dma-requests = <32>;
1482 pdma1: pdma@15600000 {
1483 compatible = "arm,pl330", "arm,primecell";
1484 reg = <0x15600000 0x1000>;
1485 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1486 clocks = <&cmu_fsys CLK_PDMA1>;
1487 clock-names = "apb_pclk";
1489 #dma-channels = <8>;
1490 #dma-requests = <32>;
1494 audio-subsystem@11400000 {
1495 compatible = "samsung,exynos5433-lpass";
1496 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1497 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1498 clock-names = "sfr0_ctrl";
1499 samsung,pmu-syscon = <&pmu_system_controller>;
1500 #address-cells = <1>;
1504 adma: adma@11420000 {
1505 compatible = "arm,pl330", "arm,primecell";
1506 reg = <0x11420000 0x1000>;
1507 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1509 clock-names = "apb_pclk";
1511 #dma-channels = <8>;
1512 #dma-requests = <32>;
1515 i2s0: i2s0@11440000 {
1516 compatible = "samsung,exynos7-i2s";
1517 reg = <0x11440000 0x100>;
1518 dmas = <&adma 0 &adma 2>;
1519 dma-names = "tx", "rx";
1520 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1521 #address-cells = <1>;
1523 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1524 <&cmu_aud CLK_SCLK_AUD_I2S>,
1525 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1526 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1527 pinctrl-names = "default";
1528 pinctrl-0 = <&i2s0_bus>;
1529 status = "disabled";
1532 serial_3: serial@11460000 {
1533 compatible = "samsung,exynos5433-uart";
1534 reg = <0x11460000 0x100>;
1535 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1536 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1537 <&cmu_aud CLK_SCLK_AUD_UART>;
1538 clock-names = "uart", "clk_uart_baud0";
1539 pinctrl-names = "default";
1540 pinctrl-0 = <&uart_aud_bus>;
1541 status = "disabled";
1547 compatible = "arm,armv8-timer";
1548 interrupts = <GIC_PPI 13
1549 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1551 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1553 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1555 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1559 #include "exynos5433-bus.dtsi"
1560 #include "exynos5433-pinctrl.dtsi"
1561 #include "exynos5433-tmu.dtsi"