4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
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13 * notice, this list of conditions and the following disclaimer in
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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 compatible = "brcm,stingray";
37 interrupt-parent = <&gic>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
55 compatible = "arm,cortex-a72";
57 enable-method = "psci";
58 next-level-cache = <&CLUSTER0_L2>;
63 compatible = "arm,cortex-a72";
65 enable-method = "psci";
66 next-level-cache = <&CLUSTER1_L2>;
71 compatible = "arm,cortex-a72";
73 enable-method = "psci";
74 next-level-cache = <&CLUSTER1_L2>;
79 compatible = "arm,cortex-a72";
81 enable-method = "psci";
82 next-level-cache = <&CLUSTER2_L2>;
87 compatible = "arm,cortex-a72";
89 enable-method = "psci";
90 next-level-cache = <&CLUSTER2_L2>;
95 compatible = "arm,cortex-a72";
97 enable-method = "psci";
98 next-level-cache = <&CLUSTER3_L2>;
103 compatible = "arm,cortex-a72";
105 enable-method = "psci";
106 next-level-cache = <&CLUSTER3_L2>;
109 CLUSTER0_L2: l2-cache@0 {
110 compatible = "cache";
115 CLUSTER1_L2: l2-cache@100 {
116 compatible = "cache";
121 CLUSTER2_L2: l2-cache@200 {
122 compatible = "cache";
127 CLUSTER3_L2: l2-cache@300 {
128 compatible = "cache";
134 memory: memory@80000000 {
135 device_type = "memory";
136 reg = <0x00000000 0x80000000 0 0x40000000>;
140 compatible = "arm,psci-0.2";
145 compatible = "arm,armv8-pmuv3";
146 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
150 compatible = "arm,armv8-timer";
151 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
152 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
153 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
154 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
157 mhb: syscon@60401000 {
158 compatible = "brcm,sr-mhb", "syscon";
159 reg = <0 0x60401000 0 0x38c>;
163 compatible = "simple-bus";
164 #address-cells = <1>;
166 ranges = <0x0 0x0 0x61000000 0x05000000>;
169 compatible = "arm,ccn-502";
170 reg = <0x00000000 0x900000>;
171 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
174 gic: interrupt-controller@2c00000 {
175 compatible = "arm,gic-v3";
176 #interrupt-cells = <3>;
177 #address-cells = <1>;
180 interrupt-controller;
181 reg = <0x02c00000 0x010000>, /* GICD */
182 <0x02e00000 0x600000>; /* GICR */
183 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
185 gic_its: msi-controller@63c20000 {
186 compatible = "arm,gic-v3-its";
189 reg = <0x02c20000 0x10000>;
193 smmu: iommu@3000000 {
194 compatible = "arm,mmu-500";
195 reg = <0x03000000 0x80000>;
196 #global-interrupts = <1>;
197 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
267 compatible = "simple-bus";
268 #address-cells = <1>;
270 ranges = <0x0 0x0 0x66400000 0x100000>;
272 #include "stingray-clock.dtsi"
275 compatible = "brcm,ocotp-v2";
276 reg = <0x0001c400 0x68>;
277 brcm,ocotp-size = <2048>;
282 compatible = "brcm,sr-cdru", "syscon";
283 reg = <0x0001d000 0x400>;
286 gpio_crmu: gpio@24800 {
287 compatible = "brcm,iproc-gpio";
288 reg = <0x00024800 0x4c>;
295 #include "stingray-fs4.dtsi"
296 #include "stingray-pcie.dtsi"
297 #include "stingray-usb.dtsi"
300 compatible = "simple-bus";
301 #address-cells = <1>;
303 ranges = <0x0 0x0 0x68900000 0x17700000>;
305 #include "stingray-pinctrl.dtsi"
307 mdio_mux_iproc: mdio-mux@20000 {
308 compatible = "brcm,mdio-mux-iproc";
309 reg = <0x00020000 0x250>;
310 #address-cells = <1>;
313 mdio@0 { /* PCIe serdes */
315 #address-cells = <1>;
321 #address-cells = <1>;
325 mdio@10 { /* RGMII */
327 #address-cells = <1>;
333 compatible = "brcm,iproc-pwm";
334 reg = <0x00010000 0x1000>;
335 clocks = <&crmu_ref25m>;
340 timer0: timer@30000 {
341 compatible = "arm,sp804", "arm,primecell";
342 reg = <0x00030000 0x1000>;
343 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&hsls_25m_div2_clk>,
345 <&hsls_25m_div2_clk>,
347 clock-names = "timer1", "timer2", "apb_pclk";
351 timer1: timer@40000 {
352 compatible = "arm,sp804", "arm,primecell";
353 reg = <0x00040000 0x1000>;
354 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&hsls_25m_div2_clk>,
356 <&hsls_25m_div2_clk>,
358 clock-names = "timer1", "timer2", "apb_pclk";
361 timer2: timer@50000 {
362 compatible = "arm,sp804", "arm,primecell";
363 reg = <0x00050000 0x1000>;
364 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&hsls_25m_div2_clk>,
366 <&hsls_25m_div2_clk>,
368 clock-names = "timer1", "timer2", "apb_pclk";
372 timer3: timer@60000 {
373 compatible = "arm,sp804", "arm,primecell";
374 reg = <0x00060000 0x1000>;
375 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&hsls_25m_div2_clk>,
377 <&hsls_25m_div2_clk>,
379 clock-names = "timer1", "timer2", "apb_pclk";
383 timer4: timer@70000 {
384 compatible = "arm,sp804", "arm,primecell";
385 reg = <0x00070000 0x1000>;
386 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&hsls_25m_div2_clk>,
388 <&hsls_25m_div2_clk>,
390 clock-names = "timer1", "timer2", "apb_pclk";
394 timer5: timer@80000 {
395 compatible = "arm,sp804", "arm,primecell";
396 reg = <0x00080000 0x1000>;
397 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&hsls_25m_div2_clk>,
399 <&hsls_25m_div2_clk>,
401 clock-names = "timer1", "timer2", "apb_pclk";
405 timer6: timer@90000 {
406 compatible = "arm,sp804", "arm,primecell";
407 reg = <0x00090000 0x1000>;
408 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&hsls_25m_div2_clk>,
410 <&hsls_25m_div2_clk>,
412 clock-names = "timer1", "timer2", "apb_pclk";
416 timer7: timer@a0000 {
417 compatible = "arm,sp804", "arm,primecell";
418 reg = <0x000a0000 0x1000>;
419 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&hsls_25m_div2_clk>,
421 <&hsls_25m_div2_clk>,
423 clock-names = "timer1", "timer2", "apb_pclk";
428 compatible = "brcm,iproc-i2c";
429 reg = <0x000b0000 0x100>;
430 #address-cells = <1>;
432 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
433 clock-frequency = <100000>;
437 wdt0: watchdog@c0000 {
438 compatible = "arm,sp805", "arm,primecell";
439 reg = <0x000c0000 0x1000>;
440 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
442 clock-names = "wdog_clk", "apb_pclk";
446 gpio_hsls: gpio@d0000 {
447 compatible = "brcm,iproc-gpio";
448 reg = <0x000d0000 0x864>;
452 interrupt-controller;
453 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
454 gpio-ranges = <&pinmux 0 0 16>,
472 compatible = "brcm,iproc-i2c";
473 reg = <0x000e0000 0x100>;
474 #address-cells = <1>;
476 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
477 clock-frequency = <100000>;
481 uart0: serial@100000 {
482 compatible = "snps,dw-apb-uart";
483 reg = <0x00100000 0x1000>;
485 clock-frequency = <25000000>;
486 interrupt-parent = <&gic>;
487 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
491 uart1: serial@110000 {
492 compatible = "snps,dw-apb-uart";
493 reg = <0x00110000 0x1000>;
495 clock-frequency = <25000000>;
496 interrupt-parent = <&gic>;
497 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
501 uart2: serial@120000 {
502 compatible = "snps,dw-apb-uart";
503 reg = <0x00120000 0x1000>;
505 clock-frequency = <25000000>;
506 interrupt-parent = <&gic>;
507 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
511 uart3: serial@130000 {
512 compatible = "snps,dw-apb-uart";
513 reg = <0x00130000 0x1000>;
515 clock-frequency = <25000000>;
516 interrupt-parent = <&gic>;
517 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
522 compatible = "arm,pl022", "arm,primecell";
523 reg = <0x00180000 0x1000>;
524 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
526 clock-names = "sspclk", "apb_pclk";
528 #address-cells = <1>;
534 compatible = "arm,pl022", "arm,primecell";
535 reg = <0x00190000 0x1000>;
536 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
538 clock-names = "sspclk", "apb_pclk";
540 #address-cells = <1>;
545 hwrng: hwrng@220000 {
546 compatible = "brcm,iproc-rng200";
547 reg = <0x00220000 0x28>;
550 dma0: dma-controller@310000 {
551 compatible = "arm,pl330", "arm,primecell";
552 reg = <0x00310000 0x1000>;
553 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&hsls_div2_clk>;
564 clock-names = "apb_pclk";
565 iommus = <&smmu 0x6000 0x0000>;
568 enet: ethernet@340000 {
569 compatible = "brcm,amac";
570 reg = <0x00340000 0x1000>;
571 reg-names = "amac_base";
573 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
578 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
579 reg = <0x00360000 0x600>,
582 reg-names = "nand", "iproc-idm", "iproc-ext";
583 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
584 #address-cells = <1>;
590 sdio0: sdhci@3f1000 {
591 compatible = "brcm,sdhci-iproc";
592 reg = <0x003f1000 0x100>;
593 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&sdio0_clk>;
596 iommus = <&smmu 0x6002 0x0000>;
600 sdio1: sdhci@3f2000 {
601 compatible = "brcm,sdhci-iproc";
602 reg = <0x003f2000 0x100>;
603 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&sdio1_clk>;
606 iommus = <&smmu 0x6003 0x0000>;
612 compatible = "simple-bus";
613 #address-cells = <1>;
615 ranges = <0x0 0x0 0x8f100000 0x100>;
618 compatible = "brcm,sr-thermal";
620 brcm,tmon-mask = <0x3f>;
621 #thermal-sensor-cells = <1>;
626 ihost0_thermal: ihost0-thermal {
627 polling-delay-passive = <0>;
628 polling-delay = <1000>;
629 thermal-sensors = <&tmon 0>;
632 temperature = <105000>;
638 ihost1_thermal: ihost1-thermal {
639 polling-delay-passive = <0>;
640 polling-delay = <1000>;
641 thermal-sensors = <&tmon 1>;
644 temperature = <105000>;
650 ihost2_thermal: ihost2-thermal {
651 polling-delay-passive = <0>;
652 polling-delay = <1000>;
653 thermal-sensors = <&tmon 2>;
656 temperature = <105000>;
662 ihost3_thermal: ihost3-thermal {
663 polling-delay-passive = <0>;
664 polling-delay = <1000>;
665 thermal-sensors = <&tmon 3>;
668 temperature = <105000>;
674 crmu_thermal: crmu-thermal {
675 polling-delay-passive = <0>;
676 polling-delay = <1000>;
677 thermal-sensors = <&tmon 4>;
680 temperature = <105000>;
686 nitro_thermal: nitro-thermal {
687 polling-delay-passive = <0>;
688 polling-delay = <1000>;
689 thermal-sensors = <&tmon 5>;
692 temperature = <105000>;
701 compatible = "simple-bus";
702 #address-cells = <1>;
704 ranges = <0x0 0x0 0x0 0x7fffffff>;
706 nic_i2c0: i2c@60826100 {
707 compatible = "brcm,iproc-nic-i2c";
708 #address-cells = <1>;
710 reg = <0x60826100 0x100>,
712 brcm,ape-hsls-addr-mask = <0x03400000>;
713 clock-frequency = <100000>;