4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Broadcom nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 compatible = "brcm,stingray";
37 interrupt-parent = <&gic>;
47 compatible = "arm,cortex-a72", "arm,armv8";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
55 compatible = "arm,cortex-a72", "arm,armv8";
57 enable-method = "psci";
58 next-level-cache = <&CLUSTER0_L2>;
63 compatible = "arm,cortex-a72", "arm,armv8";
65 enable-method = "psci";
66 next-level-cache = <&CLUSTER1_L2>;
71 compatible = "arm,cortex-a72", "arm,armv8";
73 enable-method = "psci";
74 next-level-cache = <&CLUSTER1_L2>;
79 compatible = "arm,cortex-a72", "arm,armv8";
81 enable-method = "psci";
82 next-level-cache = <&CLUSTER2_L2>;
87 compatible = "arm,cortex-a72", "arm,armv8";
89 enable-method = "psci";
90 next-level-cache = <&CLUSTER2_L2>;
95 compatible = "arm,cortex-a72", "arm,armv8";
97 enable-method = "psci";
98 next-level-cache = <&CLUSTER3_L2>;
103 compatible = "arm,cortex-a72", "arm,armv8";
105 enable-method = "psci";
106 next-level-cache = <&CLUSTER3_L2>;
109 CLUSTER0_L2: l2-cache@000 {
110 compatible = "cache";
113 CLUSTER1_L2: l2-cache@100 {
114 compatible = "cache";
117 CLUSTER2_L2: l2-cache@200 {
118 compatible = "cache";
121 CLUSTER3_L2: l2-cache@300 {
122 compatible = "cache";
126 memory: memory@80000000 {
127 device_type = "memory";
128 reg = <0x00000000 0x80000000 0 0x40000000>;
132 compatible = "arm,psci-0.2";
137 compatible = "arm,armv8-pmuv3";
138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
142 compatible = "arm,armv8-timer";
143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
150 compatible = "simple-bus";
151 #address-cells = <1>;
153 ranges = <0x0 0x0 0x61000000 0x05000000>;
156 compatible = "arm,ccn-502";
157 reg = <0x00000000 0x900000>;
158 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
161 gic: interrupt-controller@02c00000 {
162 compatible = "arm,gic-v3";
163 #interrupt-cells = <3>;
164 #address-cells = <1>;
167 interrupt-controller;
168 reg = <0x02c00000 0x010000>, /* GICD */
169 <0x02e00000 0x600000>; /* GICR */
170 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
172 gic_its: gic-its@63c20000 {
173 compatible = "arm,gic-v3-its";
176 reg = <0x02c20000 0x10000>;
181 compatible = "arm,mmu-500";
182 reg = <0x03000000 0x80000>;
183 #global-interrupts = <1>;
184 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
254 compatible = "simple-bus";
255 #address-cells = <1>;
257 ranges = <0x0 0x0 0x66400000 0x100000>;
259 #include "stingray-clock.dtsi"
261 gpio_crmu: gpio@00024800 {
262 compatible = "brcm,iproc-gpio";
263 reg = <0x00024800 0x4c>;
270 #include "stingray-fs4.dtsi"
271 #include "stingray-sata.dtsi"
274 compatible = "simple-bus";
275 #address-cells = <1>;
277 ranges = <0x0 0x0 0x68900000 0x17700000>;
279 #include "stingray-pinctrl.dtsi"
281 mdio_mux_iproc: mdio-mux@0002023c {
282 compatible = "brcm,mdio-mux-iproc";
283 reg = <0x0002023c 0x14>;
284 #address-cells = <1>;
287 mdio@0 { /* PCIe serdes */
289 #address-cells = <1>;
295 #address-cells = <1>;
301 #address-cells = <1>;
305 mdio@10 { /* RGMII */
307 #address-cells = <1>;
313 compatible = "brcm,iproc-pwm";
314 reg = <0x00010000 0x1000>;
315 clocks = <&crmu_ref25m>;
320 timer0: timer@00030000 {
321 compatible = "arm,sp804", "arm,primecell";
322 reg = <0x00030000 0x1000>;
323 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&hsls_25m_div2_clk>,
325 <&hsls_25m_div2_clk>,
327 clock-names = "timer1", "timer2", "apb_pclk";
331 timer1: timer@00040000 {
332 compatible = "arm,sp804", "arm,primecell";
333 reg = <0x00040000 0x1000>;
334 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&hsls_25m_div2_clk>,
336 <&hsls_25m_div2_clk>,
338 clock-names = "timer1", "timer2", "apb_pclk";
341 timer2: timer@00050000 {
342 compatible = "arm,sp804", "arm,primecell";
343 reg = <0x00050000 0x1000>;
344 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&hsls_25m_div2_clk>,
346 <&hsls_25m_div2_clk>,
348 clock-names = "timer1", "timer2", "apb_pclk";
352 timer3: timer@00060000 {
353 compatible = "arm,sp804", "arm,primecell";
354 reg = <0x00060000 0x1000>;
355 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&hsls_25m_div2_clk>,
357 <&hsls_25m_div2_clk>,
359 clock-names = "timer1", "timer2", "apb_pclk";
363 timer4: timer@00070000 {
364 compatible = "arm,sp804", "arm,primecell";
365 reg = <0x00070000 0x1000>;
366 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&hsls_25m_div2_clk>,
368 <&hsls_25m_div2_clk>,
370 clock-names = "timer1", "timer2", "apb_pclk";
374 timer5: timer@00080000 {
375 compatible = "arm,sp804", "arm,primecell";
376 reg = <0x00080000 0x1000>;
377 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&hsls_25m_div2_clk>,
379 <&hsls_25m_div2_clk>,
381 clock-names = "timer1", "timer2", "apb_pclk";
385 timer6: timer@00090000 {
386 compatible = "arm,sp804", "arm,primecell";
387 reg = <0x00090000 0x1000>;
388 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&hsls_25m_div2_clk>,
390 <&hsls_25m_div2_clk>,
392 clock-names = "timer1", "timer2", "apb_pclk";
396 timer7: timer@000a0000 {
397 compatible = "arm,sp804", "arm,primecell";
398 reg = <0x000a0000 0x1000>;
399 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&hsls_25m_div2_clk>,
401 <&hsls_25m_div2_clk>,
403 clock-names = "timer1", "timer2", "apb_pclk";
408 compatible = "brcm,iproc-i2c";
409 reg = <0x000b0000 0x100>;
410 #address-cells = <1>;
412 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
413 clock-frequency = <100000>;
417 wdt0: watchdog@000c0000 {
418 compatible = "arm,sp805", "arm,primecell";
419 reg = <0x000c0000 0x1000>;
420 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
422 clock-names = "wdogclk", "apb_pclk";
425 gpio_hsls: gpio@000d0000 {
426 compatible = "brcm,iproc-gpio";
427 reg = <0x000d0000 0x864>;
431 interrupt-controller;
432 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
433 gpio-ranges = <&pinmux 0 0 16>,
451 compatible = "brcm,iproc-i2c";
452 reg = <0x000e0000 0x100>;
453 #address-cells = <1>;
455 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
456 clock-frequency = <100000>;
460 uart0: uart@00100000 {
461 device_type = "serial";
462 compatible = "snps,dw-apb-uart";
463 reg = <0x00100000 0x1000>;
465 clock-frequency = <25000000>;
466 interrupt-parent = <&gic>;
467 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
471 uart1: uart@00110000 {
472 device_type = "serial";
473 compatible = "snps,dw-apb-uart";
474 reg = <0x00110000 0x1000>;
476 clock-frequency = <25000000>;
477 interrupt-parent = <&gic>;
478 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
482 uart2: uart@00120000 {
483 device_type = "serial";
484 compatible = "snps,dw-apb-uart";
485 reg = <0x00120000 0x1000>;
487 clock-frequency = <25000000>;
488 interrupt-parent = <&gic>;
489 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
493 uart3: uart@00130000 {
494 device_type = "serial";
495 compatible = "snps,dw-apb-uart";
496 reg = <0x00130000 0x1000>;
498 clock-frequency = <25000000>;
499 interrupt-parent = <&gic>;
500 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
505 compatible = "arm,pl022", "arm,primecell";
506 reg = <0x00180000 0x1000>;
507 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
509 clock-names = "spiclk", "apb_pclk";
511 #address-cells = <1>;
517 compatible = "arm,pl022", "arm,primecell";
518 reg = <0x00190000 0x1000>;
519 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
521 clock-names = "spiclk", "apb_pclk";
523 #address-cells = <1>;
528 hwrng: hwrng@00220000 {
529 compatible = "brcm,iproc-rng200";
530 reg = <0x00220000 0x28>;
534 compatible = "arm,pl330", "arm,primecell";
535 reg = <0x00310000 0x1000>;
536 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
547 #dma-requests = <32>;
548 clocks = <&hsls_div2_clk>;
549 clock-names = "apb_pclk";
550 iommus = <&smmu 0x6000 0x0000>;
553 enet: ethernet@00340000{
554 compatible = "brcm,amac";
555 reg = <0x00340000 0x1000>;
556 reg-names = "amac_base";
558 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
562 nand: nand@00360000 {
563 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
564 reg = <0x00360000 0x600>,
567 reg-names = "nand", "iproc-idm", "iproc-ext";
568 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
569 #address-cells = <1>;
575 sdio0: sdhci@003f1000 {
576 compatible = "brcm,sdhci-iproc";
577 reg = <0x003f1000 0x100>;
578 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&sdio0_clk>;
581 iommus = <&smmu 0x6002 0x0000>;
585 sdio1: sdhci@003f2000 {
586 compatible = "brcm,sdhci-iproc";
587 reg = <0x003f2000 0x100>;
588 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&sdio1_clk>;
591 iommus = <&smmu 0x6003 0x0000>;