4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 /memreserve/ 0x81000000 0x00200000;
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 /memreserve/ 0x84b00000 0x00000008;
40 compatible = "brcm,ns2";
41 interrupt-parent = <&gic>;
51 compatible = "arm,cortex-a57", "arm,armv8";
53 enable-method = "spin-table";
54 cpu-release-addr = <0 0x84b00000>;
59 compatible = "arm,cortex-a57", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0 0x84b00000>;
67 compatible = "arm,cortex-a57", "arm,armv8";
69 enable-method = "spin-table";
70 cpu-release-addr = <0 0x84b00000>;
75 compatible = "arm,cortex-a57", "arm,armv8";
77 enable-method = "spin-table";
78 cpu-release-addr = <0 0x84b00000>;
83 compatible = "arm,armv8-timer";
84 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
85 IRQ_TYPE_EDGE_RISING)>,
86 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
87 IRQ_TYPE_EDGE_RISING)>,
88 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
89 IRQ_TYPE_EDGE_RISING)>,
90 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
91 IRQ_TYPE_EDGE_RISING)>;
95 compatible = "simple-bus";
98 ranges = <0 0 0 0xffffffff>;
100 gic: interrupt-controller@65210000 {
101 compatible = "arm,gic-400";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 reg = <0x65210000 0x1000>,
110 uart3: serial@66130000 {
111 compatible = "snps,dw-apb-uart";
112 reg = <0x66130000 0x100>;
113 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
116 clock-frequency = <23961600>;