1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Broadcom Ltd.
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 compatible = "brcm,bcm6856", "brcm,bcmbca";
14 interrupt-parent = <&gic>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
29 compatible = "brcm,brahma-b53";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
44 compatible = "arm,armv8-timer";
45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 compatible = "arm,cortex-a53-pmu";
53 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
55 interrupt-affinity = <&B53_0>, <&B53_1>;
59 periph_clk:periph-clk {
60 compatible = "fixed-clock";
62 clock-frequency = <200000000>;
65 hsspi_pll: hsspi-pll {
66 compatible = "fixed-clock";
68 clock-frequency = <400000000>;
73 compatible = "arm,psci-0.2";
78 compatible = "simple-bus";
81 ranges = <0x0 0x0 0x81000000 0x8000>;
83 gic: interrupt-controller@1000 {
84 compatible = "arm,gic-400";
85 #interrupt-cells = <3>;
87 reg = <0x1000 0x1000>, /* GICD */
88 <0x2000 0x2000>, /* GICC */
89 <0x4000 0x2000>, /* GICH */
90 <0x6000 0x2000>; /* GICV */
91 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
92 IRQ_TYPE_LEVEL_HIGH)>;
97 compatible = "simple-bus";
100 ranges = <0x0 0x0 0xff800000 0x800000>;
103 compatible = "brcm,bcm6345-uart";
105 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&periph_clk>;
107 clock-names = "refclk";
112 #address-cells = <1>;
114 compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
115 reg = <0x1000 0x600>;
116 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&hsspi_pll &hsspi_pll>;
118 clock-names = "hsspi", "pll";