arch/arm64/boot/dts/broadcom/bcm2837.dtsi

   1 #include "bcm283x.dtsi"
   2
   3 / {
   4         compatible = "brcm,bcm2837";
   5
   6         soc {
   7                 ranges = <0x7e000000 0x3f000000 0x1000000>,
   8                          <0x40000000 0x40000000 0x00001000>;
   9                 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
  10
  11                 local_intc: local_intc {
  12                         compatible = "brcm,bcm2836-l1-intc";
  13                         reg = <0x40000000 0x100>;
  14                         interrupt-controller;
  15                         #interrupt-cells = <1>;
  16                         interrupt-parent = <&local_intc>;
  17                 };
  18         };
  19
  20         timer {
  21                 compatible = "arm,armv7-timer";
  22                 interrupt-parent = <&local_intc>;
  23                 interrupts = <0>, // PHYS_SECURE_PPI
  24                              <1>, // PHYS_NONSECURE_PPI
  25                              <3>, // VIRT_PPI
  26                              <2>; // HYP_PPI
  27                 always-on;
  28         };
  29
  30         cpus: cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 /* Source for d/i-cache-line-size and d/i-cache-sets
  35                  * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
  36                  * /about-the-l1-memory-system?lang=en
  37                  *
  38                  * Source for d/i-cache-size
  39                  * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
  40                  */
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53";
  44                         reg = <0>;
  45                         enable-method = "spin-table";
  46                         cpu-release-addr = <0x0 0x000000d8>;
  47                         d-cache-size = <0x8000>;
  48                         d-cache-line-size = <64>;
  49                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  50                         i-cache-size = <0x8000>;
  51                         i-cache-line-size = <64>;
  52                         i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
  53                         next-level-cache = <&l2>;
  54                 };
  55
  56                 cpu1: cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a53";
  59                         reg = <1>;
  60                         enable-method = "spin-table";
  61                         cpu-release-addr = <0x0 0x000000e0>;
  62                         d-cache-size = <0x8000>;
  63                         d-cache-line-size = <64>;
  64                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  65                         i-cache-size = <0x8000>;
  66                         i-cache-line-size = <64>;
  67                         i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
  68                         next-level-cache = <&l2>;
  69                 };
  70
  71                 cpu2: cpu@2 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <2>;
  75                         enable-method = "spin-table";
  76                         cpu-release-addr = <0x0 0x000000e8>;
  77                         d-cache-size = <0x8000>;
  78                         d-cache-line-size = <64>;
  79                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  80                         i-cache-size = <0x8000>;
  81                         i-cache-line-size = <64>;
  82                         i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
  83                         next-level-cache = <&l2>;
  84                 };
  85
  86                 cpu3: cpu@3 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53";
  89                         reg = <3>;
  90                         enable-method = "spin-table";
  91                         cpu-release-addr = <0x0 0x000000f0>;
  92                         d-cache-size = <0x8000>;
  93                         d-cache-line-size = <64>;
  94                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  95                         i-cache-size = <0x8000>;
  96                         i-cache-line-size = <64>;
  97                         i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
  98                         next-level-cache = <&l2>;
  99                 };
 100
 101                 /* Source for cache-line-size + cache-sets
 102                  * https://developer.arm.com/documentation/ddi0500
 103                  * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
 104                  * Source for cache-size
 105                  * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
 106                  */
 107                 l2: l2-cache0 {
 108                         compatible = "cache";
 109                         cache-size = <0x80000>;
 110                         cache-line-size = <64>;
 111                         cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
 112                         cache-level = <2>;
 113                 };
 114         };
 115 };
 116
 117 /* Make the BCM2835-style global interrupt controller be a child of the
 118  * CPU-local interrupt controller.
 119  */
 120 &intc {
 121         compatible = "brcm,bcm2836-armctrl-ic";
 122         reg = <0x7e00b200 0x200>;
 123         interrupt-parent = <&local_intc>;
 124         interrupts = <8>;
 125 };