arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd. Versatile Express
   4  *
   5  * LogicTile Express 20MG
   6  * V2F-1XV7
   7  *
   8  * Cortex-A53 (2 cores) Soft Macrocell Model
   9  *
  10  * HBI-0247C
  11  */
  12
  13 /dts-v1/;
  14
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include "arm/arm/vexpress-v2m-rs1.dtsi"
  17
  18 / {
  19         model = "V2F-1XV7 Cortex-A53x2 SMM";
  20         arm,hbi = <0x247>;
  21         arm,vexpress,site = <0xf>;
  22         compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
  23         interrupt-parent = <&gic>;
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         chosen {
  28                 stdout-path = "serial0:38400n8";
  29         };
  30
  31         aliases {
  32                 serial0 = &v2m_serial0;
  33                 serial1 = &v2m_serial1;
  34                 serial2 = &v2m_serial2;
  35                 serial3 = &v2m_serial3;
  36                 i2c0 = &v2m_i2c_dvi;
  37                 i2c1 = &v2m_i2c_pcie;
  38         };
  39
  40         cpus {
  41                 #address-cells = <2>;
  42                 #size-cells = <0>;
  43
  44                 cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53";
  47                         reg = <0 0>;
  48                         next-level-cache = <&L2_0>;
  49                 };
  50
  51                 cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0 1>;
  55                         next-level-cache = <&L2_0>;
  56                 };
  57
  58                 L2_0: l2-cache0 {
  59                         compatible = "cache";
  60                         cache-level = <2>;
  61                         cache-unified;
  62                 };
  63         };
  64
  65         memory@80000000 {
  66                 device_type = "memory";
  67                 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
  68         };
  69
  70         reserved-memory {
  71                 #address-cells = <2>;
  72                 #size-cells = <2>;
  73                 ranges;
  74
  75                 /* Chipselect 2 is physically at 0x18000000 */
  76                 vram: vram@18000000 {
  77                         /* 8 MB of designated video RAM */
  78                         compatible = "shared-dma-pool";
  79                         reg = <0 0x18000000 0 0x00800000>;
  80                         no-map;
  81                 };
  82         };
  83
  84         gic: interrupt-controller@2c001000 {
  85                 compatible = "arm,gic-400";
  86                 #interrupt-cells = <3>;
  87                 #address-cells = <0>;
  88                 interrupt-controller;
  89                 reg = <0 0x2c001000 0 0x1000>,
  90                       <0 0x2c002000 0 0x2000>,
  91                       <0 0x2c004000 0 0x2000>,
  92                       <0 0x2c006000 0 0x2000>;
  93                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  94         };
  95
  96         timer {
  97                 compatible = "arm,armv8-timer";
  98                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  99                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 100                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 101                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 102         };
 103
 104         pmu {
 105                 compatible = "arm,armv8-pmuv3";
 106                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 108         };
 109
 110         dcc {
 111                 compatible = "arm,vexpress,config-bus";
 112                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 113
 114                 smbclk: smclk {
 115                         /* SMC clock */
 116                         compatible = "arm,vexpress-osc";
 117                         arm,vexpress-sysreg,func = <1 4>;
 118                         freq-range = <40000000 40000000>;
 119                         #clock-cells = <0>;
 120                         clock-output-names = "smclk";
 121                 };
 122
 123                 volt-vio {
 124                         /* VIO to expansion board above */
 125                         compatible = "arm,vexpress-volt";
 126                         arm,vexpress-sysreg,func = <2 0>;
 127                         regulator-name = "VIO_UP";
 128                         regulator-min-microvolt = <800000>;
 129                         regulator-max-microvolt = <1800000>;
 130                         regulator-always-on;
 131                 };
 132
 133                 volt-12v {
 134                         /* 12V from power connector J6 */
 135                         compatible = "arm,vexpress-volt";
 136                         arm,vexpress-sysreg,func = <2 1>;
 137                         regulator-name = "12";
 138                         regulator-always-on;
 139                 };
 140
 141                 temp-fpga {
 142                         /* FPGA temperature */
 143                         compatible = "arm,vexpress-temp";
 144                         arm,vexpress-sysreg,func = <4 0>;
 145                         label = "FPGA";
 146                 };
 147         };
 148
 149         smb: bus@8000000 {
 150                 ranges = <0x8000000 0 0x8000000 0x18000000>;
 151         };
 152 };