1 // SPDX-License-Identifier: GPL-2.0
5 * Versatile Express (VE) system model
6 * Motherboard component
13 arm,v2m-memory-map = "rs1";
14 compatible = "arm,vexpress,v2m-p1", "simple-bus";
15 #address-cells = <2>; /* SMB chipselect number and offset */
17 #interrupt-cells = <1>;
21 compatible = "arm,vexpress-flash", "cfi-flash";
22 reg = <0 0x00000000 0x04000000>,
23 <4 0x00000000 0x04000000>;
27 v2m_video_ram: vram@2,00000000 {
28 compatible = "arm,vexpress-vram";
29 reg = <2 0x00000000 0x00800000>;
33 compatible = "smsc,lan91c111";
34 reg = <2 0x02000000 0x10000>;
38 v2m_clk24mhz: clk24mhz {
39 compatible = "fixed-clock";
41 clock-frequency = <24000000>;
42 clock-output-names = "v2m:clk24mhz";
45 v2m_refclk1mhz: refclk1mhz {
46 compatible = "fixed-clock";
48 clock-frequency = <1000000>;
49 clock-output-names = "v2m:refclk1mhz";
52 v2m_refclk32khz: refclk32khz {
53 compatible = "fixed-clock";
55 clock-frequency = <32768>;
56 clock-output-names = "v2m:refclk32khz";
60 compatible = "simple-bus";
63 ranges = <0 3 0 0x200000>;
65 v2m_sysreg: sysreg@10000 {
66 compatible = "arm,vexpress-sysreg";
67 reg = <0x010000 0x1000>;
72 v2m_sysctl: sysctl@20000 {
73 compatible = "arm,sp810", "arm,primecell";
74 reg = <0x020000 0x1000>;
75 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
76 clock-names = "refclk", "timclk", "apb_pclk";
78 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
79 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
80 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
84 compatible = "arm,pl041", "arm,primecell";
85 reg = <0x040000 0x1000>;
87 clocks = <&v2m_clk24mhz>;
88 clock-names = "apb_pclk";
92 compatible = "arm,pl180", "arm,primecell";
93 reg = <0x050000 0x1000>;
95 cd-gpios = <&v2m_sysreg 0 0>;
96 wp-gpios = <&v2m_sysreg 1 0>;
97 max-frequency = <12000000>;
98 vmmc-supply = <&v2m_fixed_3v3>;
99 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
100 clock-names = "mclk", "apb_pclk";
104 compatible = "arm,pl050", "arm,primecell";
105 reg = <0x060000 0x1000>;
107 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
108 clock-names = "KMIREFCLK", "apb_pclk";
112 compatible = "arm,pl050", "arm,primecell";
113 reg = <0x070000 0x1000>;
115 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
116 clock-names = "KMIREFCLK", "apb_pclk";
119 v2m_serial0: uart@90000 {
120 compatible = "arm,pl011", "arm,primecell";
121 reg = <0x090000 0x1000>;
123 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
124 clock-names = "uartclk", "apb_pclk";
127 v2m_serial1: uart@a0000 {
128 compatible = "arm,pl011", "arm,primecell";
129 reg = <0x0a0000 0x1000>;
131 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
132 clock-names = "uartclk", "apb_pclk";
135 v2m_serial2: uart@b0000 {
136 compatible = "arm,pl011", "arm,primecell";
137 reg = <0x0b0000 0x1000>;
139 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
140 clock-names = "uartclk", "apb_pclk";
143 v2m_serial3: uart@c0000 {
144 compatible = "arm,pl011", "arm,primecell";
145 reg = <0x0c0000 0x1000>;
147 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
148 clock-names = "uartclk", "apb_pclk";
152 compatible = "arm,sp805", "arm,primecell";
153 reg = <0x0f0000 0x1000>;
155 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
156 clock-names = "wdogclk", "apb_pclk";
159 v2m_timer01: timer@110000 {
160 compatible = "arm,sp804", "arm,primecell";
161 reg = <0x110000 0x1000>;
163 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
164 clock-names = "timclken1", "timclken2", "apb_pclk";
167 v2m_timer23: timer@120000 {
168 compatible = "arm,sp804", "arm,primecell";
169 reg = <0x120000 0x1000>;
171 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
172 clock-names = "timclken1", "timclken2", "apb_pclk";
176 compatible = "arm,pl031", "arm,primecell";
177 reg = <0x170000 0x1000>;
179 clocks = <&v2m_clk24mhz>;
180 clock-names = "apb_pclk";
184 compatible = "arm,pl111", "arm,primecell";
185 reg = <0x1f0000 0x1000>;
186 interrupt-names = "combined";
188 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
189 clock-names = "clcdclk", "apb_pclk";
190 arm,pl11x,framebuffer = <0x18000000 0x00180000>;
191 memory-region = <&v2m_video_ram>;
192 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
195 v2m_clcd_pads: endpoint {
196 remote-endpoint = <&v2m_clcd_panel>;
197 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
202 compatible = "panel-dpi";
205 v2m_clcd_panel: endpoint {
206 remote-endpoint = <&v2m_clcd_pads>;
211 clock-frequency = <63500127>;
224 virtio-block@130000 {
225 compatible = "virtio,mmio";
226 reg = <0x130000 0x200>;
231 v2m_fixed_3v3: v2m-3v3 {
232 compatible = "regulator-fixed";
233 regulator-name = "3V3";
234 regulator-min-microvolt = <3300000>;
235 regulator-max-microvolt = <3300000>;
240 compatible = "arm,vexpress,config-bus";
241 arm,vexpress,config-bridge = <&v2m_sysreg>;
243 v2m_oscclk1: oscclk1 {
245 compatible = "arm,vexpress-osc";
246 arm,vexpress-sysreg,func = <1 1>;
247 freq-range = <23750000 63500000>;
249 clock-output-names = "v2m:oscclk1";
253 compatible = "arm,vexpress-reset";
254 arm,vexpress-sysreg,func = <5 0>;
258 compatible = "arm,vexpress-muxfpga";
259 arm,vexpress-sysreg,func = <7 0>;
263 compatible = "arm,vexpress-shutdown";
264 arm,vexpress-sysreg,func = <8 0>;
268 compatible = "arm,vexpress-reboot";
269 arm,vexpress-sysreg,func = <9 0>;
273 compatible = "arm,vexpress-dvimode";
274 arm,vexpress-sysreg,func = <11 0>;