arch/arm64/boot/dts/arm/juno-r2.dts

   1 /*
   2  * ARM Ltd. Juno Platform
   3  *
   4  * Copyright (c) 2015 ARM Ltd.
   5  *
   6  * This file is licensed under a dual GPLv2 or BSD license.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/arm/coresight-cti-dt.h>
  13 #include "juno-base.dtsi"
  14 #include "juno-cs-r1r2.dtsi"
  15
  16 / {
  17         model = "ARM Juno development board (r2)";
  18         compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 serial0 = &soc_uart0;
  25         };
  26
  27         chosen {
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         psci {
  32                 compatible = "arm,psci-0.2";
  33                 method = "smc";
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 cpu-map {
  41                         cluster0 {
  42                                 core0 {
  43                                         cpu = <&A72_0>;
  44                                 };
  45                                 core1 {
  46                                         cpu = <&A72_1>;
  47                                 };
  48                         };
  49
  50                         cluster1 {
  51                                 core0 {
  52                                         cpu = <&A53_0>;
  53                                 };
  54                                 core1 {
  55                                         cpu = <&A53_1>;
  56                                 };
  57                                 core2 {
  58                                         cpu = <&A53_2>;
  59                                 };
  60                                 core3 {
  61                                         cpu = <&A53_3>;
  62                                 };
  63                         };
  64                 };
  65
  66                 idle-states {
  67                         entry-method = "psci";
  68
  69                         CPU_SLEEP_0: cpu-sleep-0 {
  70                                 compatible = "arm,idle-state";
  71                                 arm,psci-suspend-param = <0x0010000>;
  72                                 local-timer-stop;
  73                                 entry-latency-us = <300>;
  74                                 exit-latency-us = <1200>;
  75                                 min-residency-us = <2000>;
  76                         };
  77
  78                         CLUSTER_SLEEP_0: cluster-sleep-0 {
  79                                 compatible = "arm,idle-state";
  80                                 arm,psci-suspend-param = <0x1010000>;
  81                                 local-timer-stop;
  82                                 entry-latency-us = <400>;
  83                                 exit-latency-us = <1200>;
  84                                 min-residency-us = <2500>;
  85                         };
  86                 };
  87
  88                 A72_0: cpu@0 {
  89                         compatible = "arm,cortex-a72";
  90                         reg = <0x0 0x0>;
  91                         device_type = "cpu";
  92                         enable-method = "psci";
  93                         i-cache-size = <0xc000>;
  94                         i-cache-line-size = <64>;
  95                         i-cache-sets = <256>;
  96                         d-cache-size = <0x8000>;
  97                         d-cache-line-size = <64>;
  98                         d-cache-sets = <256>;
  99                         next-level-cache = <&A72_L2>;
 100                         clocks = <&scpi_dvfs 0>;
 101                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 102                         capacity-dmips-mhz = <1024>;
 103                         dynamic-power-coefficient = <450>;
 104                 };
 105
 106                 A72_1: cpu@1 {
 107                         compatible = "arm,cortex-a72";
 108                         reg = <0x0 0x1>;
 109                         device_type = "cpu";
 110                         enable-method = "psci";
 111                         i-cache-size = <0xc000>;
 112                         i-cache-line-size = <64>;
 113                         i-cache-sets = <256>;
 114                         d-cache-size = <0x8000>;
 115                         d-cache-line-size = <64>;
 116                         d-cache-sets = <256>;
 117                         next-level-cache = <&A72_L2>;
 118                         clocks = <&scpi_dvfs 0>;
 119                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 120                         capacity-dmips-mhz = <1024>;
 121                         dynamic-power-coefficient = <450>;
 122                 };
 123
 124                 A53_0: cpu@100 {
 125                         compatible = "arm,cortex-a53";
 126                         reg = <0x0 0x100>;
 127                         device_type = "cpu";
 128                         enable-method = "psci";
 129                         i-cache-size = <0x8000>;
 130                         i-cache-line-size = <64>;
 131                         i-cache-sets = <256>;
 132                         d-cache-size = <0x8000>;
 133                         d-cache-line-size = <64>;
 134                         d-cache-sets = <128>;
 135                         next-level-cache = <&A53_L2>;
 136                         clocks = <&scpi_dvfs 1>;
 137                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 138                         capacity-dmips-mhz = <485>;
 139                         dynamic-power-coefficient = <140>;
 140                 };
 141
 142                 A53_1: cpu@101 {
 143                         compatible = "arm,cortex-a53";
 144                         reg = <0x0 0x101>;
 145                         device_type = "cpu";
 146                         enable-method = "psci";
 147                         i-cache-size = <0x8000>;
 148                         i-cache-line-size = <64>;
 149                         i-cache-sets = <256>;
 150                         d-cache-size = <0x8000>;
 151                         d-cache-line-size = <64>;
 152                         d-cache-sets = <128>;
 153                         next-level-cache = <&A53_L2>;
 154                         clocks = <&scpi_dvfs 1>;
 155                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 156                         capacity-dmips-mhz = <485>;
 157                         dynamic-power-coefficient = <140>;
 158                 };
 159
 160                 A53_2: cpu@102 {
 161                         compatible = "arm,cortex-a53";
 162                         reg = <0x0 0x102>;
 163                         device_type = "cpu";
 164                         enable-method = "psci";
 165                         i-cache-size = <0x8000>;
 166                         i-cache-line-size = <64>;
 167                         i-cache-sets = <256>;
 168                         d-cache-size = <0x8000>;
 169                         d-cache-line-size = <64>;
 170                         d-cache-sets = <128>;
 171                         next-level-cache = <&A53_L2>;
 172                         clocks = <&scpi_dvfs 1>;
 173                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 174                         capacity-dmips-mhz = <485>;
 175                         dynamic-power-coefficient = <140>;
 176                 };
 177
 178                 A53_3: cpu@103 {
 179                         compatible = "arm,cortex-a53";
 180                         reg = <0x0 0x103>;
 181                         device_type = "cpu";
 182                         enable-method = "psci";
 183                         i-cache-size = <0x8000>;
 184                         i-cache-line-size = <64>;
 185                         i-cache-sets = <256>;
 186                         d-cache-size = <0x8000>;
 187                         d-cache-line-size = <64>;
 188                         d-cache-sets = <128>;
 189                         next-level-cache = <&A53_L2>;
 190                         clocks = <&scpi_dvfs 1>;
 191                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 192                         capacity-dmips-mhz = <485>;
 193                         dynamic-power-coefficient = <140>;
 194                 };
 195
 196                 A72_L2: l2-cache0 {
 197                         compatible = "cache";
 198                         cache-unified;
 199                         cache-size = <0x200000>;
 200                         cache-line-size = <64>;
 201                         cache-sets = <2048>;
 202                         cache-level = <2>;
 203                 };
 204
 205                 A53_L2: l2-cache1 {
 206                         compatible = "cache";
 207                         cache-unified;
 208                         cache-size = <0x100000>;
 209                         cache-line-size = <64>;
 210                         cache-sets = <1024>;
 211                         cache-level = <2>;
 212                 };
 213         };
 214
 215         pmu-a72 {
 216                 compatible = "arm,cortex-a72-pmu";
 217                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
 219                 interrupt-affinity = <&A72_0>,
 220                                      <&A72_1>;
 221         };
 222
 223         pmu-a53 {
 224                 compatible = "arm,cortex-a53-pmu";
 225                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 229                 interrupt-affinity = <&A53_0>,
 230                                      <&A53_1>,
 231                                      <&A53_2>,
 232                                      <&A53_3>;
 233         };
 234 };
 235
 236 &memtimer {
 237         status = "okay";
 238 };
 239
 240 &pcie_ctlr {
 241         status = "okay";
 242 };
 243
 244 &smmu_pcie {
 245         status = "okay";
 246 };
 247
 248 &etm0 {
 249         cpu = <&A72_0>;
 250 };
 251
 252 &etm1 {
 253         cpu = <&A72_1>;
 254 };
 255
 256 &etm2 {
 257         cpu = <&A53_0>;
 258 };
 259
 260 &etm3 {
 261         cpu = <&A53_1>;
 262 };
 263
 264 &etm4 {
 265         cpu = <&A53_2>;
 266 };
 267
 268 &etm5 {
 269         cpu = <&A53_3>;
 270 };
 271
 272 &big_cluster_thermal_zone {
 273         status = "okay";
 274 };
 275
 276 &little_cluster_thermal_zone {
 277         status = "okay";
 278 };
 279
 280 &gpu0_thermal_zone {
 281         status = "okay";
 282 };
 283
 284 &gpu1_thermal_zone {
 285         status = "okay";
 286 };
 287
 288 &etf0_out_port {
 289         remote-endpoint = <&csys2_funnel_in_port0>;
 290 };
 291
 292 &replicator_in_port0 {
 293         remote-endpoint = <&csys2_funnel_out_port>;
 294 };
 295
 296 &csys1_funnel_in_port0 {
 297         remote-endpoint = <&stm_out_port>;
 298 };
 299
 300 &stm_out_port {
 301         remote-endpoint = <&csys1_funnel_in_port0>;
 302 };
 303
 304 &cpu_debug0 {
 305         cpu = <&A72_0>;
 306 };
 307
 308 &cpu_debug1 {
 309         cpu = <&A72_1>;
 310 };
 311
 312 &cpu_debug2 {
 313         cpu = <&A53_0>;
 314 };
 315
 316 &cpu_debug3 {
 317         cpu = <&A53_1>;
 318 };
 319
 320 &cpu_debug4 {
 321         cpu = <&A53_2>;
 322 };
 323
 324 &cpu_debug5 {
 325         cpu = <&A53_3>;
 326 };
 327
 328 &cti0 {
 329         cpu = <&A72_0>;
 330 };
 331
 332 &cti1 {
 333         cpu = <&A72_1>;
 334 };
 335
 336 &cti2 {
 337         cpu = <&A53_0>;
 338 };
 339
 340 &cti3 {
 341         cpu = <&A53_1>;
 342 };
 343
 344 &cti4 {
 345         cpu = <&A53_2>;
 346 };
 347
 348 &cti5 {
 349         cpu = <&A53_3>;
 350 };