2 * ARM Juno Platform motherboard peripherals
4 * Copyright (c) 2013-2014 ARM Ltd
6 * This file is licensed under a dual GPLv2 or BSD license.
11 mb_clk24mhz: clk24mhz {
12 compatible = "fixed-clock";
14 clock-frequency = <24000000>;
15 clock-output-names = "juno_mb:clk24mhz";
18 mb_clk25mhz: clk25mhz {
19 compatible = "fixed-clock";
21 clock-frequency = <25000000>;
22 clock-output-names = "juno_mb:clk25mhz";
25 v2m_refclk1mhz: refclk1mhz {
26 compatible = "fixed-clock";
28 clock-frequency = <1000000>;
29 clock-output-names = "juno_mb:refclk1mhz";
32 v2m_refclk32khz: refclk32khz {
33 compatible = "fixed-clock";
35 clock-frequency = <32768>;
36 clock-output-names = "juno_mb:refclk32khz";
39 mb_fixed_3v3: mcc-sb-3v3 {
40 compatible = "regulator-fixed";
41 regulator-name = "MCC_SB_3V3";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
48 compatible = "gpio-keys";
51 debounce-interval = <50>;
55 gpios = <&iofpga_gpio0 0 0x4>;
58 debounce-interval = <50>;
62 gpios = <&iofpga_gpio0 1 0x4>;
65 debounce-interval = <50>;
69 gpios = <&iofpga_gpio0 2 0x4>;
72 debounce-interval = <50>;
76 gpios = <&iofpga_gpio0 3 0x4>;
79 debounce-interval = <50>;
83 gpios = <&iofpga_gpio0 4 0x4>;
86 debounce-interval = <50>;
90 gpios = <&iofpga_gpio0 5 0x4>;
95 compatible = "simple-bus";
98 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
100 motherboard-bus@8000000 {
101 compatible = "arm,vexpress,v2p-p1", "simple-bus";
102 #address-cells = <2>; /* SMB chipselect number and offset */
104 ranges = <0 0 0 0x08000000 0x04000000>,
105 <1 0 0 0x14000000 0x04000000>,
106 <2 0 0 0x18000000 0x04000000>,
107 <3 0 0 0x1c000000 0x04000000>,
108 <4 0 0 0x0c000000 0x04000000>,
109 <5 0 0 0x10000000 0x04000000>;
111 arm,vexpress,site = <0>;
114 /* 2 * 32MiB NOR Flash memory mounted on CS0 */
115 compatible = "arm,vexpress-flash", "cfi-flash";
116 reg = <0 0x00000000 0x04000000>;
119 * Unfortunately, accessing the flash disturbs
120 * the CPU idle states (suspend) and CPU
121 * hotplug of the platform. For this reason,
122 * flash hardware access is disabled by default.
126 compatible = "arm,arm-firmware-suite";
131 compatible = "smsc,lan9118", "smsc,lan9115";
132 reg = <2 0x00000000 0x10000>;
136 smsc,irq-active-high;
138 clocks = <&mb_clk25mhz>;
139 vdd33a-supply = <&mb_fixed_3v3>;
140 vddvario-supply = <&mb_fixed_3v3>;
143 iofpga-bus@300000000 {
144 compatible = "simple-bus";
145 #address-cells = <1>;
147 ranges = <0 3 0 0x200000>;
149 v2m_sysctl: sysctl@20000 {
150 compatible = "arm,sp810", "arm,primecell";
151 reg = <0x020000 0x1000>;
152 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
153 clock-names = "refclk", "timclk", "apb_pclk";
155 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
156 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
157 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
161 compatible = "syscon", "simple-mfd";
162 reg = <0x010000 0x1000>;
163 ranges = <0x0 0x10000 0x1000>;
164 #address-cells = <1>;
168 compatible = "register-bit-led";
172 label = "vexpress:0";
173 linux,default-trigger = "heartbeat";
174 default-state = "on";
177 compatible = "register-bit-led";
181 label = "vexpress:1";
182 linux,default-trigger = "mmc0";
183 default-state = "off";
186 compatible = "register-bit-led";
190 label = "vexpress:2";
191 linux,default-trigger = "cpu0";
192 default-state = "off";
195 compatible = "register-bit-led";
199 label = "vexpress:3";
200 linux,default-trigger = "cpu1";
201 default-state = "off";
204 compatible = "register-bit-led";
208 label = "vexpress:4";
209 linux,default-trigger = "cpu2";
210 default-state = "off";
213 compatible = "register-bit-led";
217 label = "vexpress:5";
218 linux,default-trigger = "cpu3";
219 default-state = "off";
222 compatible = "register-bit-led";
226 label = "vexpress:6";
227 default-state = "off";
230 compatible = "register-bit-led";
234 label = "vexpress:7";
235 default-state = "off";
240 compatible = "arm,pl180", "arm,primecell";
241 reg = <0x050000 0x1000>;
243 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
244 wp-gpios = <&v2m_mmc_gpios 1 0>; */
245 max-frequency = <12000000>;
246 vmmc-supply = <&mb_fixed_3v3>;
247 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
248 clock-names = "mclk", "apb_pclk";
252 compatible = "arm,pl050", "arm,primecell";
253 reg = <0x060000 0x1000>;
255 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
256 clock-names = "KMIREFCLK", "apb_pclk";
260 compatible = "arm,pl050", "arm,primecell";
261 reg = <0x070000 0x1000>;
263 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
264 clock-names = "KMIREFCLK", "apb_pclk";
268 compatible = "arm,sp805", "arm,primecell";
269 reg = <0x0f0000 0x10000>;
271 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
272 clock-names = "wdog_clk", "apb_pclk";
275 v2m_timer01: timer@110000 {
276 compatible = "arm,sp804", "arm,primecell";
277 reg = <0x110000 0x10000>;
279 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
280 clock-names = "timclken1", "timclken2", "apb_pclk";
283 v2m_timer23: timer@120000 {
284 compatible = "arm,sp804", "arm,primecell";
285 reg = <0x120000 0x10000>;
287 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
288 clock-names = "timclken1", "timclken2", "apb_pclk";
292 compatible = "arm,pl031", "arm,primecell";
293 reg = <0x170000 0x10000>;
295 clocks = <&soc_smc50mhz>;
296 clock-names = "apb_pclk";
299 iofpga_gpio0: gpio@1d0000 {
300 compatible = "arm,pl061", "arm,primecell";
301 reg = <0x1d0000 0x1000>;
303 clocks = <&soc_smc50mhz>;
304 clock-names = "apb_pclk";
307 interrupt-controller;
308 #interrupt-cells = <2>;