1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
7 * Devices shared by all Juno boards
10 memtimer: timer@2a810000 {
11 compatible = "arm,armv7-timer-mem";
12 reg = <0x0 0x2a810000 0x0 0x10000>;
13 clock-frequency = <50000000>;
20 interrupts = <0 60 4>;
21 reg = <0x0 0x2a830000 0x0 0x10000>;
25 mailbox: mhu@2b1f0000 {
26 compatible = "arm,mhu", "arm,primecell";
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
30 interrupt-names = "mhu_lpri_rx",
33 clocks = <&soc_refclk100mhz>;
34 clock-names = "apb_pclk";
37 smmu_pcie: iommu@2b500000 {
38 compatible = "arm,mmu-401", "arm,smmu-v1";
39 reg = <0x0 0x2b500000 0x0 0x10000>;
40 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
43 #global-interrupts = <1>;
48 smmu_etr: iommu@2b600000 {
49 compatible = "arm,mmu-401", "arm,smmu-v1";
50 reg = <0x0 0x2b600000 0x0 0x10000>;
51 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
54 #global-interrupts = <1>;
56 power-domains = <&scpi_devpd 0>;
59 gic: interrupt-controller@2c010000 {
60 compatible = "arm,gic-400", "arm,cortex-a15-gic";
61 reg = <0x0 0x2c010000 0 0x1000>,
62 <0x0 0x2c02f000 0 0x2000>,
63 <0x0 0x2c04f000 0 0x2000>,
64 <0x0 0x2c06f000 0 0x2000>;
66 #interrupt-cells = <3>;
69 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
70 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
73 compatible = "arm,gic-v2m-frame";
75 reg = <0 0 0 0x10000>;
79 compatible = "arm,gic-v2m-frame";
81 reg = <0 0x10000 0 0x10000>;
85 compatible = "arm,gic-v2m-frame";
87 reg = <0 0x20000 0 0x10000>;
91 compatible = "arm,gic-v2m-frame";
93 reg = <0 0x30000 0 0x10000>;
98 compatible = "arm,armv8-timer";
99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
106 * Juno TRMs specify the size for these coresight components as 64K.
107 * The actual size is just 4K though 64K is reserved. Access to the
108 * unmapped reserved region results in a DECERR response.
110 etf@20010000 { /* etf0 */
111 compatible = "arm,coresight-tmc", "arm,primecell";
112 reg = <0 0x20010000 0 0x1000>;
114 clocks = <&soc_smc50mhz>;
115 clock-names = "apb_pclk";
116 power-domains = <&scpi_devpd 0>;
118 #address-cells = <1>;
124 etf0_in_port: endpoint {
126 remote-endpoint = <&main_funnel_out_port>;
133 etf0_out_port: endpoint {
140 compatible = "arm,coresight-tpiu", "arm,primecell";
141 reg = <0 0x20030000 0 0x1000>;
143 clocks = <&soc_smc50mhz>;
144 clock-names = "apb_pclk";
145 power-domains = <&scpi_devpd 0>;
147 tpiu_in_port: endpoint {
149 remote-endpoint = <&replicator_out_port0>;
154 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
155 main_funnel: funnel@20040000 {
156 compatible = "arm,coresight-funnel", "arm,primecell";
157 reg = <0 0x20040000 0 0x1000>;
159 clocks = <&soc_smc50mhz>;
160 clock-names = "apb_pclk";
161 power-domains = <&scpi_devpd 0>;
163 #address-cells = <1>;
169 main_funnel_out_port: endpoint {
170 remote-endpoint = <&etf0_in_port>;
177 main_funnel_in_port0: endpoint {
179 remote-endpoint = <&cluster0_funnel_out_port>;
185 main_funnel_in_port1: endpoint {
187 remote-endpoint = <&cluster1_funnel_out_port>;
194 compatible = "arm,coresight-tmc", "arm,primecell";
195 reg = <0 0x20070000 0 0x1000>;
196 iommus = <&smmu_etr 0>;
198 clocks = <&soc_smc50mhz>;
199 clock-names = "apb_pclk";
200 power-domains = <&scpi_devpd 0>;
202 etr_in_port: endpoint {
204 remote-endpoint = <&replicator_out_port1>;
210 compatible = "arm,coresight-stm", "arm,primecell";
211 reg = <0 0x20100000 0 0x1000>,
212 <0 0x28000000 0 0x1000000>;
213 reg-names = "stm-base", "stm-stimulus-base";
215 clocks = <&soc_smc50mhz>;
216 clock-names = "apb_pclk";
217 power-domains = <&scpi_devpd 0>;
219 stm_out_port: endpoint {
224 cpu_debug0: cpu-debug@22010000 {
225 compatible = "arm,coresight-cpu-debug", "arm,primecell";
226 reg = <0x0 0x22010000 0x0 0x1000>;
228 clocks = <&soc_smc50mhz>;
229 clock-names = "apb_pclk";
230 power-domains = <&scpi_devpd 0>;
234 compatible = "arm,coresight-etm4x", "arm,primecell";
235 reg = <0 0x22040000 0 0x1000>;
237 clocks = <&soc_smc50mhz>;
238 clock-names = "apb_pclk";
239 power-domains = <&scpi_devpd 0>;
241 cluster0_etm0_out_port: endpoint {
242 remote-endpoint = <&cluster0_funnel_in_port0>;
247 funnel@220c0000 { /* cluster0 funnel */
248 compatible = "arm,coresight-funnel", "arm,primecell";
249 reg = <0 0x220c0000 0 0x1000>;
251 clocks = <&soc_smc50mhz>;
252 clock-names = "apb_pclk";
253 power-domains = <&scpi_devpd 0>;
255 #address-cells = <1>;
260 cluster0_funnel_out_port: endpoint {
261 remote-endpoint = <&main_funnel_in_port0>;
267 cluster0_funnel_in_port0: endpoint {
269 remote-endpoint = <&cluster0_etm0_out_port>;
275 cluster0_funnel_in_port1: endpoint {
277 remote-endpoint = <&cluster0_etm1_out_port>;
283 cpu_debug1: cpu-debug@22110000 {
284 compatible = "arm,coresight-cpu-debug", "arm,primecell";
285 reg = <0x0 0x22110000 0x0 0x1000>;
287 clocks = <&soc_smc50mhz>;
288 clock-names = "apb_pclk";
289 power-domains = <&scpi_devpd 0>;
293 compatible = "arm,coresight-etm4x", "arm,primecell";
294 reg = <0 0x22140000 0 0x1000>;
296 clocks = <&soc_smc50mhz>;
297 clock-names = "apb_pclk";
298 power-domains = <&scpi_devpd 0>;
300 cluster0_etm1_out_port: endpoint {
301 remote-endpoint = <&cluster0_funnel_in_port1>;
306 cpu_debug2: cpu-debug@23010000 {
307 compatible = "arm,coresight-cpu-debug", "arm,primecell";
308 reg = <0x0 0x23010000 0x0 0x1000>;
310 clocks = <&soc_smc50mhz>;
311 clock-names = "apb_pclk";
312 power-domains = <&scpi_devpd 0>;
316 compatible = "arm,coresight-etm4x", "arm,primecell";
317 reg = <0 0x23040000 0 0x1000>;
319 clocks = <&soc_smc50mhz>;
320 clock-names = "apb_pclk";
321 power-domains = <&scpi_devpd 0>;
323 cluster1_etm0_out_port: endpoint {
324 remote-endpoint = <&cluster1_funnel_in_port0>;
329 funnel@230c0000 { /* cluster1 funnel */
330 compatible = "arm,coresight-funnel", "arm,primecell";
331 reg = <0 0x230c0000 0 0x1000>;
333 clocks = <&soc_smc50mhz>;
334 clock-names = "apb_pclk";
335 power-domains = <&scpi_devpd 0>;
337 #address-cells = <1>;
342 cluster1_funnel_out_port: endpoint {
343 remote-endpoint = <&main_funnel_in_port1>;
349 cluster1_funnel_in_port0: endpoint {
351 remote-endpoint = <&cluster1_etm0_out_port>;
357 cluster1_funnel_in_port1: endpoint {
359 remote-endpoint = <&cluster1_etm1_out_port>;
364 cluster1_funnel_in_port2: endpoint {
366 remote-endpoint = <&cluster1_etm2_out_port>;
371 cluster1_funnel_in_port3: endpoint {
373 remote-endpoint = <&cluster1_etm3_out_port>;
379 cpu_debug3: cpu-debug@23110000 {
380 compatible = "arm,coresight-cpu-debug", "arm,primecell";
381 reg = <0x0 0x23110000 0x0 0x1000>;
383 clocks = <&soc_smc50mhz>;
384 clock-names = "apb_pclk";
385 power-domains = <&scpi_devpd 0>;
389 compatible = "arm,coresight-etm4x", "arm,primecell";
390 reg = <0 0x23140000 0 0x1000>;
392 clocks = <&soc_smc50mhz>;
393 clock-names = "apb_pclk";
394 power-domains = <&scpi_devpd 0>;
396 cluster1_etm1_out_port: endpoint {
397 remote-endpoint = <&cluster1_funnel_in_port1>;
402 cpu_debug4: cpu-debug@23210000 {
403 compatible = "arm,coresight-cpu-debug", "arm,primecell";
404 reg = <0x0 0x23210000 0x0 0x1000>;
406 clocks = <&soc_smc50mhz>;
407 clock-names = "apb_pclk";
408 power-domains = <&scpi_devpd 0>;
412 compatible = "arm,coresight-etm4x", "arm,primecell";
413 reg = <0 0x23240000 0 0x1000>;
415 clocks = <&soc_smc50mhz>;
416 clock-names = "apb_pclk";
417 power-domains = <&scpi_devpd 0>;
419 cluster1_etm2_out_port: endpoint {
420 remote-endpoint = <&cluster1_funnel_in_port2>;
425 cpu_debug5: cpu-debug@23310000 {
426 compatible = "arm,coresight-cpu-debug", "arm,primecell";
427 reg = <0x0 0x23310000 0x0 0x1000>;
429 clocks = <&soc_smc50mhz>;
430 clock-names = "apb_pclk";
431 power-domains = <&scpi_devpd 0>;
435 compatible = "arm,coresight-etm4x", "arm,primecell";
436 reg = <0 0x23340000 0 0x1000>;
438 clocks = <&soc_smc50mhz>;
439 clock-names = "apb_pclk";
440 power-domains = <&scpi_devpd 0>;
442 cluster1_etm3_out_port: endpoint {
443 remote-endpoint = <&cluster1_funnel_in_port3>;
448 replicator@20120000 {
449 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
450 reg = <0 0x20120000 0 0x1000>;
452 clocks = <&soc_smc50mhz>;
453 clock-names = "apb_pclk";
454 power-domains = <&scpi_devpd 0>;
457 #address-cells = <1>;
460 /* replicator output ports */
463 replicator_out_port0: endpoint {
464 remote-endpoint = <&tpiu_in_port>;
470 replicator_out_port1: endpoint {
471 remote-endpoint = <&etr_in_port>;
475 /* replicator input port */
478 replicator_in_port0: endpoint {
485 sram: sram@2e000000 {
486 compatible = "arm,juno-sram-ns", "mmio-sram";
487 reg = <0x0 0x2e000000 0x0 0x8000>;
489 #address-cells = <1>;
491 ranges = <0 0x0 0x2e000000 0x8000>;
493 cpu_scp_lpri: scp-shmem@0 {
494 compatible = "arm,juno-scp-shmem";
498 cpu_scp_hpri: scp-shmem@200 {
499 compatible = "arm,juno-scp-shmem";
504 pcie_ctlr: pcie@40000000 {
505 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
507 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
509 linux,pci-domain = <0>;
510 #address-cells = <3>;
513 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
514 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
515 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
516 #interrupt-cells = <1>;
517 interrupt-map-mask = <0 0 0 7>;
518 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
519 <0 0 0 2 &gic 0 0 0 137 4>,
520 <0 0 0 3 &gic 0 0 0 138 4>,
521 <0 0 0 4 &gic 0 0 0 139 4>;
522 msi-parent = <&v2m_0>;
524 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
525 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
529 compatible = "arm,scpi";
530 mboxes = <&mailbox 1>;
531 shmem = <&cpu_scp_hpri>;
534 compatible = "arm,scpi-clocks";
536 scpi_dvfs: clocks-0 {
537 compatible = "arm,scpi-dvfs-clocks";
539 clock-indices = <0>, <1>, <2>;
540 clock-output-names = "atlclk", "aplclk","gpuclk";
543 compatible = "arm,scpi-variable-clocks";
546 clock-output-names = "pxlclk";
550 scpi_devpd: power-controller {
551 compatible = "arm,scpi-power-domains";
553 #power-domain-cells = <1>;
556 scpi_sensors0: sensors {
557 compatible = "arm,scpi-sensors";
558 #thermal-sensor-cells = <1>;
564 polling-delay = <1000>;
565 polling-delay-passive = <100>;
566 thermal-sensors = <&scpi_sensors0 0>;
570 polling-delay = <1000>;
571 polling-delay-passive = <100>;
572 thermal-sensors = <&scpi_sensors0 3>;
575 big_cluster_thermal_zone: big-cluster {
576 polling-delay = <1000>;
577 polling-delay-passive = <100>;
578 thermal-sensors = <&scpi_sensors0 21>;
582 little_cluster_thermal_zone: little-cluster {
583 polling-delay = <1000>;
584 polling-delay-passive = <100>;
585 thermal-sensors = <&scpi_sensors0 22>;
589 gpu0_thermal_zone: gpu0 {
590 polling-delay = <1000>;
591 polling-delay-passive = <100>;
592 thermal-sensors = <&scpi_sensors0 23>;
596 gpu1_thermal_zone: gpu1 {
597 polling-delay = <1000>;
598 polling-delay-passive = <100>;
599 thermal-sensors = <&scpi_sensors0 24>;
604 smmu_dma: iommu@7fb00000 {
605 compatible = "arm,mmu-401", "arm,smmu-v1";
606 reg = <0x0 0x7fb00000 0x0 0x10000>;
607 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
610 #global-interrupts = <1>;
615 smmu_hdlcd1: iommu@7fb10000 {
616 compatible = "arm,mmu-401", "arm,smmu-v1";
617 reg = <0x0 0x7fb10000 0x0 0x10000>;
618 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
621 #global-interrupts = <1>;
624 smmu_hdlcd0: iommu@7fb20000 {
625 compatible = "arm,mmu-401", "arm,smmu-v1";
626 reg = <0x0 0x7fb20000 0x0 0x10000>;
627 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
630 #global-interrupts = <1>;
633 smmu_usb: iommu@7fb30000 {
634 compatible = "arm,mmu-401", "arm,smmu-v1";
635 reg = <0x0 0x7fb30000 0x0 0x10000>;
636 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
639 #global-interrupts = <1>;
644 compatible = "arm,pl330", "arm,primecell";
645 reg = <0x0 0x7ff00000 0 0x1000>;
648 #dma-requests = <32>;
649 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
658 iommus = <&smmu_dma 0>,
667 clocks = <&soc_faxiclk>;
668 clock-names = "apb_pclk";
672 compatible = "arm,hdlcd";
673 reg = <0 0x7ff50000 0 0x1000>;
674 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
675 iommus = <&smmu_hdlcd1 0>;
676 clocks = <&scpi_clk 3>;
677 clock-names = "pxlclk";
680 hdlcd1_output: endpoint {
681 remote-endpoint = <&tda998x_1_input>;
687 compatible = "arm,hdlcd";
688 reg = <0 0x7ff60000 0 0x1000>;
689 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
690 iommus = <&smmu_hdlcd0 0>;
691 clocks = <&scpi_clk 3>;
692 clock-names = "pxlclk";
695 hdlcd0_output: endpoint {
696 remote-endpoint = <&tda998x_0_input>;
701 soc_uart0: uart@7ff80000 {
702 compatible = "arm,pl011", "arm,primecell";
703 reg = <0x0 0x7ff80000 0x0 0x1000>;
704 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
706 clock-names = "uartclk", "apb_pclk";
710 compatible = "snps,designware-i2c";
711 reg = <0x0 0x7ffa0000 0x0 0x1000>;
712 #address-cells = <1>;
714 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
715 clock-frequency = <400000>;
716 i2c-sda-hold-time-ns = <500>;
717 clocks = <&soc_smc50mhz>;
719 hdmi-transmitter@70 {
720 compatible = "nxp,tda998x";
723 tda998x_0_input: endpoint {
724 remote-endpoint = <&hdlcd0_output>;
729 hdmi-transmitter@71 {
730 compatible = "nxp,tda998x";
733 tda998x_1_input: endpoint {
734 remote-endpoint = <&hdlcd1_output>;
741 compatible = "generic-ohci";
742 reg = <0x0 0x7ffb0000 0x0 0x10000>;
743 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
744 iommus = <&smmu_usb 0>;
745 clocks = <&soc_usb48mhz>;
749 compatible = "generic-ehci";
750 reg = <0x0 0x7ffc0000 0x0 0x10000>;
751 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
752 iommus = <&smmu_usb 0>;
753 clocks = <&soc_usb48mhz>;
756 memory-controller@7ffd0000 {
757 compatible = "arm,pl354", "arm,primecell";
758 reg = <0 0x7ffd0000 0 0x1000>;
759 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&soc_smc50mhz>;
762 clock-names = "apb_pclk";
766 device_type = "memory";
767 /* last 16MB of the first memory area is reserved for secure world use by firmware */
768 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
769 <0x00000008 0x80000000 0x1 0x80000000>;
773 compatible = "simple-bus";
774 #address-cells = <2>;
776 ranges = <0 0 0 0x08000000 0x04000000>,
777 <1 0 0 0x14000000 0x04000000>,
778 <2 0 0 0x18000000 0x04000000>,
779 <3 0 0 0x1c000000 0x04000000>,
780 <4 0 0 0x0c000000 0x04000000>,
781 <5 0 0 0x10000000 0x04000000>;
783 #interrupt-cells = <1>;
784 interrupt-map-mask = <0 0 15>;
785 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
786 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
787 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
788 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
789 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
790 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
791 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
792 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
793 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
794 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
795 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
796 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
797 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
800 site2: tlx@60000000 {
801 compatible = "simple-bus";
802 #address-cells = <1>;
804 ranges = <0 0 0x60000000 0x10000000>;
805 #interrupt-cells = <1>;
806 interrupt-map-mask = <0 0>;
807 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;