arch/arm64/boot/dts/arm/foundation-v8.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd.
   4  *
   5  * ARMv8 Foundation model DTS
   6  */
   7
   8 /dts-v1/;
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 /memreserve/ 0x80000000 0x00010000;
  13
  14 / {
  15         model = "Foundation-v8A";
  16         compatible = "arm,foundation-aarch64", "arm,vexpress";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         aliases {
  24                 serial0 = &v2m_serial0;
  25                 serial1 = &v2m_serial1;
  26                 serial2 = &v2m_serial2;
  27                 serial3 = &v2m_serial3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <2>;
  32                 #size-cells = <0>;
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,armv8";
  37                         reg = <0x0 0x0>;
  38                         next-level-cache = <&L2_0>;
  39                 };
  40                 cpu1: cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,armv8";
  43                         reg = <0x0 0x1>;
  44                         next-level-cache = <&L2_0>;
  45                 };
  46                 cpu2: cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,armv8";
  49                         reg = <0x0 0x2>;
  50                         next-level-cache = <&L2_0>;
  51                 };
  52                 cpu3: cpu@3 {
  53                         device_type = "cpu";
  54                         compatible = "arm,armv8";
  55                         reg = <0x0 0x3>;
  56                         next-level-cache = <&L2_0>;
  57                 };
  58
  59                 L2_0: l2-cache0 {
  60                         compatible = "cache";
  61                         cache-level = <2>;
  62                         cache-unified;
  63                 };
  64         };
  65
  66         memory@80000000 {
  67                 device_type = "memory";
  68                 reg = <0x00000000 0x80000000 0 0x80000000>,
  69                       <0x00000008 0x80000000 0 0x80000000>;
  70         };
  71
  72         timer {
  73                 compatible = "arm,armv8-timer";
  74                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  78                 clock-frequency = <100000000>;
  79         };
  80
  81         pmu {
  82                 compatible = "arm,armv8-pmuv3";
  83                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  87         };
  88
  89         spe-pmu {
  90                 compatible = "arm,statistical-profiling-extension-v1";
  91                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
  92         };
  93
  94         watchdog@2a440000 {
  95                 compatible = "arm,sbsa-gwdt";
  96                 reg = <0x0 0x2a440000 0 0x1000>,
  97                         <0x0 0x2a450000 0 0x1000>;
  98                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  99                 timeout-sec = <30>;
 100         };
 101
 102         v2m_clk24mhz: clk24mhz {
 103                 compatible = "fixed-clock";
 104                 #clock-cells = <0>;
 105                 clock-frequency = <24000000>;
 106                 clock-output-names = "v2m:clk24mhz";
 107         };
 108
 109         v2m_refclk1mhz: refclk1mhz {
 110                 compatible = "fixed-clock";
 111                 #clock-cells = <0>;
 112                 clock-frequency = <1000000>;
 113                 clock-output-names = "v2m:refclk1mhz";
 114         };
 115
 116         v2m_refclk32khz: refclk32khz {
 117                 compatible = "fixed-clock";
 118                 #clock-cells = <0>;
 119                 clock-frequency = <32768>;
 120                 clock-output-names = "v2m:refclk32khz";
 121         };
 122
 123         bus@8000000 {
 124                 compatible = "arm,vexpress,v2m-p1", "simple-bus";
 125                 #address-cells = <2>; /* SMB chipselect number and offset */
 126                 #size-cells = <1>;
 127
 128                 ranges = <0 0 0 0x08000000 0x04000000>,
 129                          <1 0 0 0x14000000 0x04000000>,
 130                          <2 0 0 0x18000000 0x04000000>,
 131                          <3 0 0 0x1c000000 0x04000000>,
 132                          <4 0 0 0x0c000000 0x04000000>,
 133                          <5 0 0 0x10000000 0x04000000>;
 134
 135                 #interrupt-cells = <1>;
 136                 interrupt-map-mask = <0 0 63>;
 137                 interrupt-map = <0 0  0 &gic 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
 138                                 <0 0  1 &gic 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
 139                                 <0 0  2 &gic 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
 140                                 <0 0  3 &gic 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
 141                                 <0 0  4 &gic 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
 142                                 <0 0  5 &gic 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
 143                                 <0 0  6 &gic 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
 144                                 <0 0  7 &gic 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
 145                                 <0 0  8 &gic 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 146                                 <0 0  9 &gic 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 147                                 <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 148                                 <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 149                                 <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 150                                 <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 151                                 <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 152                                 <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 153                                 <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 154                                 <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 155                                 <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 156                                 <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 157                                 <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 158                                 <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 159                                 <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 160                                 <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 161                                 <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 162                                 <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 163                                 <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 164                                 <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 165                                 <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 166                                 <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 167                                 <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 168                                 <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 169                                 <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 170                                 <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 171                                 <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 172                                 <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 173                                 <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 174                                 <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 175                                 <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 176                                 <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 177                                 <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 178                                 <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 179                                 <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 180
 181                 ethernet@202000000 {
 182                         compatible = "smsc,lan91c111";
 183                         reg = <2 0x02000000 0x10000>;
 184                         interrupts = <15>;
 185                 };
 186
 187                 iofpga-bus@300000000 {
 188                         compatible = "simple-bus";
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191                         ranges = <0 3 0 0x200000>;
 192
 193                         v2m_sysreg: sysreg@10000 {
 194                                 compatible = "arm,vexpress-sysreg";
 195                                 reg = <0x010000 0x1000>;
 196                         };
 197
 198                         v2m_serial0: serial@90000 {
 199                                 compatible = "arm,pl011", "arm,primecell";
 200                                 reg = <0x090000 0x1000>;
 201                                 interrupts = <5>;
 202                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 203                                 clock-names = "uartclk", "apb_pclk";
 204                         };
 205
 206                         v2m_serial1: serial@a0000 {
 207                                 compatible = "arm,pl011", "arm,primecell";
 208                                 reg = <0x0a0000 0x1000>;
 209                                 interrupts = <6>;
 210                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 211                                 clock-names = "uartclk", "apb_pclk";
 212                         };
 213
 214                         v2m_serial2: serial@b0000 {
 215                                 compatible = "arm,pl011", "arm,primecell";
 216                                 reg = <0x0b0000 0x1000>;
 217                                 interrupts = <7>;
 218                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 219                                 clock-names = "uartclk", "apb_pclk";
 220                         };
 221
 222                         v2m_serial3: serial@c0000 {
 223                                 compatible = "arm,pl011", "arm,primecell";
 224                                 reg = <0x0c0000 0x1000>;
 225                                 interrupts = <8>;
 226                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 227                                 clock-names = "uartclk", "apb_pclk";
 228                         };
 229
 230                         virtio@130000 {
 231                                 compatible = "virtio,mmio";
 232                                 reg = <0x130000 0x200>;
 233                                 interrupts = <42>;
 234                         };
 235                 };
 236         };
 237 };