1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (c) 2022, Arm Limited. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited. All rights reserved.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
21 stdout-path = "serial0:115200n8";
30 compatible = "arm,cortex-a35";
32 next-level-cache = <&L2_0>;
37 device_type = "memory";
38 reg = <0x88200000 0x77e00000>;
41 gic: interrupt-controller@1c000000 {
42 compatible = "arm,gic-400";
43 #interrupt-cells = <3>;
46 reg = <0x1c010000 0x1000>,
50 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
58 cache-size = <0x80000>;
59 cache-line-size = <64>;
63 refclk100mhz: refclk100mhz {
64 compatible = "fixed-clock";
66 clock-frequency = <100000000>;
67 clock-output-names = "apb_pclk";
70 smbclk: refclk24mhzx2 {
71 /* Reference 24MHz clock x 2 */
72 compatible = "fixed-clock";
74 clock-frequency = <48000000>;
75 clock-output-names = "smclk";
79 compatible = "arm,armv8-timer";
80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
87 /* UART clock - 50MHz */
88 compatible = "fixed-clock";
90 clock-frequency = <50000000>;
91 clock-output-names = "uartclk";
95 compatible = "arm,psci-1.0", "arm,psci-0.2";
100 compatible = "simple-bus";
101 #address-cells = <1>;
103 interrupt-parent = <&gic>;
107 compatible = "arm,armv7-timer-mem";
108 reg = <0x1a220000 0x1000>;
109 #address-cells = <1>;
111 clock-frequency = <50000000>;
116 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
117 reg = <0x1a230000 0x1000>;
121 uart0: serial@1a510000 {
122 compatible = "arm,pl011", "arm,primecell";
123 reg = <0x1a510000 0x1000>;
124 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&uartclk>, <&refclk100mhz>;
126 clock-names = "uartclk", "apb_pclk";
129 uart1: serial@1a520000 {
130 compatible = "arm,pl011", "arm,primecell";
131 reg = <0x1a520000 0x1000>;
132 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&uartclk>, <&refclk100mhz>;
134 clock-names = "uartclk", "apb_pclk";
137 mhu_hse1: mailbox@1b820000 {
138 compatible = "arm,mhuv2-tx", "arm,primecell";
139 reg = <0x1b820000 0x1000>;
140 clocks = <&refclk100mhz>;
141 clock-names = "apb_pclk";
142 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
144 arm,mhuv2-protocols = <0 0>;
145 secure-status = "okay"; /* secure-world-only */
149 mhu_seh1: mailbox@1b830000 {
150 compatible = "arm,mhuv2-rx", "arm,primecell";
151 reg = <0x1b830000 0x1000>;
152 clocks = <&refclk100mhz>;
153 clock-names = "apb_pclk";
154 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
156 arm,mhuv2-protocols = <0 0>;
157 secure-status = "okay"; /* secure-world-only */