arch/arm64/boot/dts/arm/corstone1000.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 or MIT
   2 /*
   3  * Copyright (c) 2022, Arm Limited. All rights reserved.
   4  * Copyright (c) 2022, Linaro Limited. All rights reserved.
   5  *
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         interrupt-parent = <&gic>;
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18         };
  19
  20         chosen {
  21                 stdout-path = "serial0:115200n8";
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a35";
  31                         reg = <0>;
  32                         next-level-cache = <&L2_0>;
  33                 };
  34         };
  35
  36         memory@88200000 {
  37                 device_type = "memory";
  38                 reg = <0x88200000 0x77e00000>;
  39         };
  40
  41         gic: interrupt-controller@1c000000 {
  42                 compatible = "arm,gic-400";
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 interrupt-controller;
  46                 reg =   <0x1c010000 0x1000>,
  47                         <0x1c02f000 0x2000>,
  48                         <0x1c04f000 0x1000>,
  49                         <0x1c06f000 0x2000>;
  50                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
  51                               IRQ_TYPE_LEVEL_LOW)>;
  52         };
  53
  54         L2_0: l2-cache0 {
  55                 compatible = "cache";
  56                 cache-level = <2>;
  57                 cache-size = <0x80000>;
  58                 cache-line-size = <64>;
  59                 cache-sets = <1024>;
  60         };
  61
  62         refclk100mhz: refclk100mhz {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <100000000>;
  66                 clock-output-names = "apb_pclk";
  67         };
  68
  69         smbclk: refclk24mhzx2 {
  70                 /* Reference 24MHz clock x 2 */
  71                 compatible = "fixed-clock";
  72                 #clock-cells = <0>;
  73                 clock-frequency = <48000000>;
  74                 clock-output-names = "smclk";
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv8-timer";
  79                 interrupts =    <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
  80                                  IRQ_TYPE_LEVEL_LOW)>,
  81                                 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
  82                                  IRQ_TYPE_LEVEL_LOW)>,
  83                                 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
  84                                  IRQ_TYPE_LEVEL_LOW)>,
  85                                 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
  86                                  IRQ_TYPE_LEVEL_LOW)>;
  87         };
  88
  89         uartclk: uartclk {
  90                 /* UART clock - 50MHz */
  91                 compatible = "fixed-clock";
  92                 #clock-cells = <0>;
  93                 clock-frequency = <50000000>;
  94                 clock-output-names = "uartclk";
  95         };
  96
  97         psci {
  98                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  99                 method = "smc";
 100         };
 101
 102         soc {
 103                 compatible = "simple-bus";
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 interrupt-parent = <&gic>;
 107                 ranges;
 108
 109                 timer@1a220000 {
 110                         compatible = "arm,armv7-timer-mem";
 111                         reg = <0x1a220000 0x1000>;
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114                         clock-frequency = <50000000>;
 115                         ranges;
 116
 117                         frame@1a230000 {
 118                                 frame-number = <0>;
 119                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 120                                 reg = <0x1a230000 0x1000>;
 121                         };
 122                 };
 123
 124                 uart0: serial@1a510000 {
 125                         compatible = "arm,pl011", "arm,primecell";
 126                         reg = <0x1a510000 0x1000>;
 127                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 128                         clocks = <&uartclk>, <&refclk100mhz>;
 129                         clock-names = "uartclk", "apb_pclk";
 130                 };
 131
 132                 uart1: serial@1a520000 {
 133                         compatible = "arm,pl011", "arm,primecell";
 134                         reg = <0x1a520000 0x1000>;
 135                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 136                         clocks = <&uartclk>, <&refclk100mhz>;
 137                         clock-names = "uartclk", "apb_pclk";
 138                 };
 139
 140                 mhu_hse1: mailbox@1b820000 {
 141                         compatible = "arm,mhuv2-tx", "arm,primecell";
 142                         reg = <0x1b820000 0x1000>;
 143                         clocks = <&refclk100mhz>;
 144                         clock-names = "apb_pclk";
 145                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 146                         #mbox-cells = <2>;
 147                         arm,mhuv2-protocols = <0 0>;
 148                         secure-status = "okay";     /* secure-world-only */
 149                         status = "disabled";
 150                 };
 151
 152                 mhu_seh1: mailbox@1b830000 {
 153                         compatible = "arm,mhuv2-rx", "arm,primecell";
 154                         reg = <0x1b830000 0x1000>;
 155                         clocks = <&refclk100mhz>;
 156                         clock-names = "apb_pclk";
 157                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 158                         #mbox-cells = <2>;
 159                         arm,mhuv2-protocols = <0 0>;
 160                         secure-status = "okay";     /* secure-world-only */
 161                         status = "disabled";
 162                 };
 163         };
 164 };