1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
5 * Copyright (C) 2013, Applied Micro Circuits Corporation
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
20 compatible = "apm,potenza";
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
28 compatible = "apm,potenza";
30 enable-method = "spin-table";
31 cpu-release-addr = <0x1 0x0000fff8>;
32 next-level-cache = <&xgene_L2_0>;
36 compatible = "apm,potenza";
38 enable-method = "spin-table";
39 cpu-release-addr = <0x1 0x0000fff8>;
40 next-level-cache = <&xgene_L2_1>;
44 compatible = "apm,potenza";
46 enable-method = "spin-table";
47 cpu-release-addr = <0x1 0x0000fff8>;
48 next-level-cache = <&xgene_L2_1>;
52 compatible = "apm,potenza";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
56 next-level-cache = <&xgene_L2_2>;
60 compatible = "apm,potenza";
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
68 compatible = "apm,potenza";
70 enable-method = "spin-table";
71 cpu-release-addr = <0x1 0x0000fff8>;
72 next-level-cache = <&xgene_L2_3>;
76 compatible = "apm,potenza";
78 enable-method = "spin-table";
79 cpu-release-addr = <0x1 0x0000fff8>;
80 next-level-cache = <&xgene_L2_3>;
82 xgene_L2_0: l2-cache-0 {
87 xgene_L2_1: l2-cache-1 {
92 xgene_L2_2: l2-cache-2 {
97 xgene_L2_3: l2-cache-3 {
104 gic: interrupt-controller@78010000 {
105 compatible = "arm,cortex-a15-gic";
106 #interrupt-cells = <3>;
107 interrupt-controller;
108 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
109 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
110 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
111 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
112 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
116 compatible = "arm,armv8-timer";
117 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
118 <1 13 0xff08>, /* Non-secure Phys IRQ */
119 <1 14 0xff08>, /* Virt IRQ */
120 <1 15 0xff08>; /* Hyp IRQ */
121 clock-frequency = <50000000>;
125 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
126 interrupts = <1 12 0xff04>;
130 compatible = "simple-bus";
131 #address-cells = <2>;
134 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
137 #address-cells = <2>;
141 compatible = "fixed-clock";
143 clock-frequency = <100000000>;
144 clock-output-names = "refclk";
147 pcppll: pcppll@17000100 {
148 compatible = "apm,xgene-pcppll-clock";
150 clocks = <&refclk 0>;
151 clock-names = "pcppll";
152 reg = <0x0 0x17000100 0x0 0x1000>;
153 clock-output-names = "pcppll";
157 socpll: socpll@17000120 {
158 compatible = "apm,xgene-socpll-clock";
160 clocks = <&refclk 0>;
161 clock-names = "socpll";
162 reg = <0x0 0x17000120 0x0 0x1000>;
163 clock-output-names = "socpll";
167 socplldiv2: socplldiv2 {
168 compatible = "fixed-factor-clock";
170 clocks = <&socpll 0>;
171 clock-names = "socplldiv2";
174 clock-output-names = "socplldiv2";
177 ahbclk: ahbclk@17000000 {
178 compatible = "apm,xgene-device-clock";
180 clocks = <&socplldiv2 0>;
181 reg = <0x0 0x17000000 0x0 0x2000>;
182 reg-names = "div-reg";
183 divider-offset = <0x164>;
184 divider-width = <0x5>;
185 divider-shift = <0x0>;
186 clock-output-names = "ahbclk";
189 sdioclk: sdioclk@1f2ac000 {
190 compatible = "apm,xgene-device-clock";
192 clocks = <&socplldiv2 0>;
193 reg = <0x0 0x1f2ac000 0x0 0x1000
194 0x0 0x17000000 0x0 0x2000>;
195 reg-names = "csr-reg", "div-reg";
198 enable-offset = <0x8>;
200 divider-offset = <0x178>;
201 divider-width = <0x8>;
202 divider-shift = <0x0>;
203 clock-output-names = "sdioclk";
207 compatible = "apm,xgene-device-clock";
209 clocks = <&socplldiv2 0>;
210 clock-names = "ethclk";
211 reg = <0x0 0x17000000 0x0 0x1000>;
212 reg-names = "div-reg";
213 divider-offset = <0x238>;
214 divider-width = <0x9>;
215 divider-shift = <0x0>;
216 clock-output-names = "ethclk";
220 compatible = "apm,xgene-device-clock";
222 clocks = <ðclk 0>;
223 reg = <0x0 0x1702c000 0x0 0x1000>;
224 reg-names = "csr-reg";
225 clock-output-names = "menetclk";
228 sge0clk: sge0clk@1f21c000 {
229 compatible = "apm,xgene-device-clock";
231 clocks = <&socplldiv2 0>;
232 reg = <0x0 0x1f21c000 0x0 0x1000>;
233 reg-names = "csr-reg";
236 clock-output-names = "sge0clk";
239 xge0clk: xge0clk@1f61c000 {
240 compatible = "apm,xgene-device-clock";
242 clocks = <&socplldiv2 0>;
243 reg = <0x0 0x1f61c000 0x0 0x1000>;
244 reg-names = "csr-reg";
246 clock-output-names = "xge0clk";
249 xge1clk: xge1clk@1f62c000 {
250 compatible = "apm,xgene-device-clock";
253 clocks = <&socplldiv2 0>;
254 reg = <0x0 0x1f62c000 0x0 0x1000>;
255 reg-names = "csr-reg";
257 clock-output-names = "xge1clk";
260 sataphy1clk: sataphy1clk@1f21c000 {
261 compatible = "apm,xgene-device-clock";
263 clocks = <&socplldiv2 0>;
264 reg = <0x0 0x1f21c000 0x0 0x1000>;
265 reg-names = "csr-reg";
266 clock-output-names = "sataphy1clk";
270 enable-offset = <0x0>;
271 enable-mask = <0x06>;
274 sataphy2clk: sataphy1clk@1f22c000 {
275 compatible = "apm,xgene-device-clock";
277 clocks = <&socplldiv2 0>;
278 reg = <0x0 0x1f22c000 0x0 0x1000>;
279 reg-names = "csr-reg";
280 clock-output-names = "sataphy2clk";
284 enable-offset = <0x0>;
285 enable-mask = <0x06>;
288 sataphy3clk: sataphy1clk@1f23c000 {
289 compatible = "apm,xgene-device-clock";
291 clocks = <&socplldiv2 0>;
292 reg = <0x0 0x1f23c000 0x0 0x1000>;
293 reg-names = "csr-reg";
294 clock-output-names = "sataphy3clk";
298 enable-offset = <0x0>;
299 enable-mask = <0x06>;
302 sata01clk: sata01clk@1f21c000 {
303 compatible = "apm,xgene-device-clock";
305 clocks = <&socplldiv2 0>;
306 reg = <0x0 0x1f21c000 0x0 0x1000>;
307 reg-names = "csr-reg";
308 clock-output-names = "sata01clk";
311 enable-offset = <0x0>;
312 enable-mask = <0x39>;
315 sata23clk: sata23clk@1f22c000 {
316 compatible = "apm,xgene-device-clock";
318 clocks = <&socplldiv2 0>;
319 reg = <0x0 0x1f22c000 0x0 0x1000>;
320 reg-names = "csr-reg";
321 clock-output-names = "sata23clk";
324 enable-offset = <0x0>;
325 enable-mask = <0x39>;
328 sata45clk: sata45clk@1f23c000 {
329 compatible = "apm,xgene-device-clock";
331 clocks = <&socplldiv2 0>;
332 reg = <0x0 0x1f23c000 0x0 0x1000>;
333 reg-names = "csr-reg";
334 clock-output-names = "sata45clk";
337 enable-offset = <0x0>;
338 enable-mask = <0x39>;
341 rtcclk: rtcclk@17000000 {
342 compatible = "apm,xgene-device-clock";
344 clocks = <&socplldiv2 0>;
345 reg = <0x0 0x17000000 0x0 0x2000>;
346 reg-names = "csr-reg";
349 enable-offset = <0x10>;
351 clock-output-names = "rtcclk";
354 rngpkaclk: rngpkaclk@17000000 {
355 compatible = "apm,xgene-device-clock";
357 clocks = <&socplldiv2 0>;
358 reg = <0x0 0x17000000 0x0 0x2000>;
359 reg-names = "csr-reg";
362 enable-offset = <0x10>;
363 enable-mask = <0x10>;
364 clock-output-names = "rngpkaclk";
367 pcie0clk: pcie0clk@1f2bc000 {
369 compatible = "apm,xgene-device-clock";
371 clocks = <&socplldiv2 0>;
372 reg = <0x0 0x1f2bc000 0x0 0x1000>;
373 reg-names = "csr-reg";
374 clock-output-names = "pcie0clk";
377 pcie1clk: pcie1clk@1f2cc000 {
379 compatible = "apm,xgene-device-clock";
381 clocks = <&socplldiv2 0>;
382 reg = <0x0 0x1f2cc000 0x0 0x1000>;
383 reg-names = "csr-reg";
384 clock-output-names = "pcie1clk";
387 pcie2clk: pcie2clk@1f2dc000 {
389 compatible = "apm,xgene-device-clock";
391 clocks = <&socplldiv2 0>;
392 reg = <0x0 0x1f2dc000 0x0 0x1000>;
393 reg-names = "csr-reg";
394 clock-output-names = "pcie2clk";
397 pcie3clk: pcie3clk@1f50c000 {
399 compatible = "apm,xgene-device-clock";
401 clocks = <&socplldiv2 0>;
402 reg = <0x0 0x1f50c000 0x0 0x1000>;
403 reg-names = "csr-reg";
404 clock-output-names = "pcie3clk";
407 pcie4clk: pcie4clk@1f51c000 {
409 compatible = "apm,xgene-device-clock";
411 clocks = <&socplldiv2 0>;
412 reg = <0x0 0x1f51c000 0x0 0x1000>;
413 reg-names = "csr-reg";
414 clock-output-names = "pcie4clk";
417 dmaclk: dmaclk@1f27c000 {
418 compatible = "apm,xgene-device-clock";
420 clocks = <&socplldiv2 0>;
421 reg = <0x0 0x1f27c000 0x0 0x1000>;
422 reg-names = "csr-reg";
423 clock-output-names = "dmaclk";
428 compatible = "apm,xgene1-msi";
430 reg = <0x00 0x79000000 0x0 0x900000>;
431 interrupts = < 0x0 0x10 0x4
449 scu: system-clk-controller@17000000 {
450 compatible = "apm,xgene-scu","syscon";
451 reg = <0x0 0x17000000 0x0 0x400>;
454 reboot: reboot@17000014 {
455 compatible = "syscon-reboot";
462 compatible = "apm,xgene-csw", "syscon";
463 reg = <0x0 0x7e200000 0x0 0x1000>;
466 mcba: mcba@7e700000 {
467 compatible = "apm,xgene-mcb", "syscon";
468 reg = <0x0 0x7e700000 0x0 0x1000>;
471 mcbb: mcbb@7e720000 {
472 compatible = "apm,xgene-mcb", "syscon";
473 reg = <0x0 0x7e720000 0x0 0x1000>;
476 efuse: efuse@1054a000 {
477 compatible = "apm,xgene-efuse", "syscon";
478 reg = <0x0 0x1054a000 0x0 0x20>;
482 compatible = "apm,xgene-rb", "syscon";
483 reg = <0x0 0x7e000000 0x0 0x10>;
487 compatible = "apm,xgene-edac";
488 #address-cells = <2>;
492 regmap-mcba = <&mcba>;
493 regmap-mcbb = <&mcbb>;
494 regmap-efuse = <&efuse>;
496 reg = <0x0 0x78800000 0x0 0x100>;
497 interrupts = <0x0 0x20 0x4>,
502 compatible = "apm,xgene-edac-mc";
503 reg = <0x0 0x7e800000 0x0 0x1000>;
504 memory-controller = <0>;
508 compatible = "apm,xgene-edac-mc";
509 reg = <0x0 0x7e840000 0x0 0x1000>;
510 memory-controller = <1>;
514 compatible = "apm,xgene-edac-mc";
515 reg = <0x0 0x7e880000 0x0 0x1000>;
516 memory-controller = <2>;
520 compatible = "apm,xgene-edac-mc";
521 reg = <0x0 0x7e8c0000 0x0 0x1000>;
522 memory-controller = <3>;
526 compatible = "apm,xgene-edac-pmd";
527 reg = <0x0 0x7c000000 0x0 0x200000>;
528 pmd-controller = <0>;
532 compatible = "apm,xgene-edac-pmd";
533 reg = <0x0 0x7c200000 0x0 0x200000>;
534 pmd-controller = <1>;
538 compatible = "apm,xgene-edac-pmd";
539 reg = <0x0 0x7c400000 0x0 0x200000>;
540 pmd-controller = <2>;
544 compatible = "apm,xgene-edac-pmd";
545 reg = <0x0 0x7c600000 0x0 0x200000>;
546 pmd-controller = <3>;
550 compatible = "apm,xgene-edac-l3";
551 reg = <0x0 0x7e600000 0x0 0x1000>;
555 compatible = "apm,xgene-edac-soc-v1";
556 reg = <0x0 0x7e930000 0x0 0x1000>;
561 compatible = "apm,xgene-pmu-v2";
562 #address-cells = <2>;
566 regmap-mcba = <&mcba>;
567 regmap-mcbb = <&mcbb>;
568 reg = <0x0 0x78810000 0x0 0x1000>;
569 interrupts = <0x0 0x22 0x4>;
572 compatible = "apm,xgene-pmu-l3c";
573 reg = <0x0 0x7e610000 0x0 0x1000>;
577 compatible = "apm,xgene-pmu-iob";
578 reg = <0x0 0x7e940000 0x0 0x1000>;
582 compatible = "apm,xgene-pmu-mcb";
583 reg = <0x0 0x7e710000 0x0 0x1000>;
584 enable-bit-index = <0>;
588 compatible = "apm,xgene-pmu-mcb";
589 reg = <0x0 0x7e730000 0x0 0x1000>;
590 enable-bit-index = <1>;
594 compatible = "apm,xgene-pmu-mc";
595 reg = <0x0 0x7e810000 0x0 0x1000>;
596 enable-bit-index = <0>;
600 compatible = "apm,xgene-pmu-mc";
601 reg = <0x0 0x7e850000 0x0 0x1000>;
602 enable-bit-index = <1>;
606 compatible = "apm,xgene-pmu-mc";
607 reg = <0x0 0x7e890000 0x0 0x1000>;
608 enable-bit-index = <2>;
612 compatible = "apm,xgene-pmu-mc";
613 reg = <0x0 0x7e8d0000 0x0 0x1000>;
614 enable-bit-index = <3>;
618 pcie0: pcie@1f2b0000 {
621 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
622 #interrupt-cells = <1>;
624 #address-cells = <3>;
625 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
626 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
627 reg-names = "csr", "cfg";
628 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
629 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
630 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
631 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
632 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
633 bus-range = <0x00 0xff>;
634 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
635 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
636 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
637 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
638 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
640 clocks = <&pcie0clk 0>;
644 pcie1: pcie@1f2c0000 {
647 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
648 #interrupt-cells = <1>;
650 #address-cells = <3>;
651 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
652 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
653 reg-names = "csr", "cfg";
654 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
655 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
656 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
657 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
658 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
659 bus-range = <0x00 0xff>;
660 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
661 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
662 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
663 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
664 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
666 clocks = <&pcie1clk 0>;
670 pcie2: pcie@1f2d0000 {
673 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
674 #interrupt-cells = <1>;
676 #address-cells = <3>;
677 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
678 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
679 reg-names = "csr", "cfg";
680 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
681 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
682 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
683 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
684 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
685 bus-range = <0x00 0xff>;
686 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
687 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
688 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
689 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
690 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
692 clocks = <&pcie2clk 0>;
696 pcie3: pcie@1f500000 {
699 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
700 #interrupt-cells = <1>;
702 #address-cells = <3>;
703 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
704 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
705 reg-names = "csr", "cfg";
706 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
707 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
708 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
709 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
710 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
711 bus-range = <0x00 0xff>;
712 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
713 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
714 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
715 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
716 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
718 clocks = <&pcie3clk 0>;
722 pcie4: pcie@1f510000 {
725 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
726 #interrupt-cells = <1>;
728 #address-cells = <3>;
729 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
730 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
731 reg-names = "csr", "cfg";
732 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
733 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
734 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
735 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
736 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
737 bus-range = <0x00 0xff>;
738 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
739 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
740 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
741 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
742 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
744 clocks = <&pcie4clk 0>;
748 mailbox: mailbox@10540000 {
749 compatible = "apm,xgene-slimpro-mbox";
750 reg = <0x0 0x10540000 0x0 0xa000>;
752 interrupts = <0x0 0x0 0x4>,
763 compatible = "apm,xgene-slimpro-i2c";
764 mboxes = <&mailbox 0>;
768 compatible = "apm,xgene-slimpro-hwmon";
769 mboxes = <&mailbox 7>;
772 serial0: serial@1c020000 {
774 compatible = "ns16550a";
775 reg = <0 0x1c020000 0x0 0x1000>;
777 clock-frequency = <10000000>; /* Updated by bootloader */
778 interrupt-parent = <&gic>;
779 interrupts = <0x0 0x4c 0x4>;
782 serial1: serial@1c021000 {
784 compatible = "ns16550a";
785 reg = <0 0x1c021000 0x0 0x1000>;
787 clock-frequency = <10000000>; /* Updated by bootloader */
788 interrupt-parent = <&gic>;
789 interrupts = <0x0 0x4d 0x4>;
792 serial2: serial@1c022000 {
794 compatible = "ns16550a";
795 reg = <0 0x1c022000 0x0 0x1000>;
797 clock-frequency = <10000000>; /* Updated by bootloader */
798 interrupt-parent = <&gic>;
799 interrupts = <0x0 0x4e 0x4>;
802 serial3: serial@1c023000 {
804 compatible = "ns16550a";
805 reg = <0 0x1c023000 0x0 0x1000>;
807 clock-frequency = <10000000>; /* Updated by bootloader */
808 interrupt-parent = <&gic>;
809 interrupts = <0x0 0x4f 0x4>;
813 compatible = "arasan,sdhci-4.9a";
814 reg = <0x0 0x1c000000 0x0 0x100>;
815 interrupts = <0x0 0x49 0x4>;
818 clock-names = "clk_xin", "clk_ahb";
819 clocks = <&sdioclk 0>, <&ahbclk 0>;
822 gfcgpio: gpio0@1701c000 {
823 compatible = "apm,xgene-gpio";
824 reg = <0x0 0x1701c000 0x0 0x40>;
829 dwgpio: gpio@1c024000 {
830 compatible = "snps,dw-apb-gpio";
831 reg = <0x0 0x1c024000 0x0 0x1000>;
832 #address-cells = <1>;
835 porta: gpio-controller@0 {
836 compatible = "snps,dw-apb-gpio-port";
839 snps,nr-gpios = <32>;
846 #address-cells = <1>;
848 compatible = "snps,designware-i2c";
849 reg = <0x0 0x10512000 0x0 0x1000>;
850 interrupts = <0 0x44 0x4>;
852 clocks = <&ahbclk 0>;
857 compatible = "apm,xgene-phy";
858 reg = <0x0 0x1f21a000 0x0 0x100>;
860 clocks = <&sataphy1clk 0>;
862 apm,tx-boost-gain = <30 30 30 30 30 30>;
863 apm,tx-eye-tuning = <2 10 10 2 10 10>;
867 compatible = "apm,xgene-phy";
868 reg = <0x0 0x1f22a000 0x0 0x100>;
870 clocks = <&sataphy2clk 0>;
872 apm,tx-boost-gain = <30 30 30 30 30 30>;
873 apm,tx-eye-tuning = <1 10 10 2 10 10>;
877 compatible = "apm,xgene-phy";
878 reg = <0x0 0x1f23a000 0x0 0x100>;
880 clocks = <&sataphy3clk 0>;
882 apm,tx-boost-gain = <31 31 31 31 31 31>;
883 apm,tx-eye-tuning = <2 10 10 2 10 10>;
886 sata1: sata@1a000000 {
887 compatible = "apm,xgene-ahci";
888 reg = <0x0 0x1a000000 0x0 0x1000>,
889 <0x0 0x1f210000 0x0 0x1000>,
890 <0x0 0x1f21d000 0x0 0x1000>,
891 <0x0 0x1f21e000 0x0 0x1000>,
892 <0x0 0x1f217000 0x0 0x1000>;
893 interrupts = <0x0 0x86 0x4>;
896 clocks = <&sata01clk 0>;
898 phy-names = "sata-phy";
901 sata2: sata@1a400000 {
902 compatible = "apm,xgene-ahci";
903 reg = <0x0 0x1a400000 0x0 0x1000>,
904 <0x0 0x1f220000 0x0 0x1000>,
905 <0x0 0x1f22d000 0x0 0x1000>,
906 <0x0 0x1f22e000 0x0 0x1000>,
907 <0x0 0x1f227000 0x0 0x1000>;
908 interrupts = <0x0 0x87 0x4>;
911 clocks = <&sata23clk 0>;
913 phy-names = "sata-phy";
916 sata3: sata@1a800000 {
917 compatible = "apm,xgene-ahci";
918 reg = <0x0 0x1a800000 0x0 0x1000>,
919 <0x0 0x1f230000 0x0 0x1000>,
920 <0x0 0x1f23d000 0x0 0x1000>,
921 <0x0 0x1f23e000 0x0 0x1000>;
922 interrupts = <0x0 0x88 0x4>;
925 clocks = <&sata45clk 0>;
927 phy-names = "sata-phy";
930 /* Node-name might need to be coded as dwusb for backward compatibility */
933 compatible = "snps,dwc3";
934 reg = <0x0 0x19000000 0x0 0x100000>;
935 interrupts = <0x0 0x89 0x4>;
942 compatible = "snps,dwc3";
943 reg = <0x0 0x19800000 0x0 0x100000>;
944 interrupts = <0x0 0x8a 0x4>;
949 sbgpio: gpio@17001000 {
950 compatible = "apm,xgene-gpio-sb";
951 reg = <0x0 0x17001000 0x0 0x400>;
954 interrupts = <0x0 0x28 0x1>,
960 interrupt-parent = <&gic>;
961 #interrupt-cells = <2>;
962 interrupt-controller;
966 compatible = "apm,xgene-rtc";
967 reg = <0x0 0x10510000 0x0 0x400>;
968 interrupts = <0x0 0x46 0x4>;
970 clocks = <&rtcclk 0>;
973 mdio: mdio@17020000 {
974 compatible = "apm,xgene-mdio-rgmii";
975 #address-cells = <1>;
977 reg = <0x0 0x17020000 0x0 0xd100>;
978 clocks = <&menetclk 0>;
981 menet: ethernet@17020000 {
982 compatible = "apm,xgene-enet";
984 reg = <0x0 0x17020000 0x0 0xd100>,
985 <0x0 0x17030000 0x0 0xc300>,
986 <0x0 0x10000000 0x0 0x200>;
987 reg-names = "enet_csr", "ring_csr", "ring_cmd";
988 interrupts = <0x0 0x3c 0x4>;
990 clocks = <&menetclk 0>;
991 /* mac address will be overwritten by the bootloader */
992 local-mac-address = [00 00 00 00 00 00];
993 phy-connection-type = "rgmii";
994 phy-handle = <&menetphy>,<&menet0phy>;
996 compatible = "apm,xgene-mdio";
997 #address-cells = <1>;
999 menetphy: menetphy@3 {
1000 compatible = "ethernet-phy-id001c.c915";
1007 sgenet0: ethernet@1f210000 {
1008 compatible = "apm,xgene1-sgenet";
1009 status = "disabled";
1010 reg = <0x0 0x1f210000 0x0 0xd100>,
1011 <0x0 0x1f200000 0x0 0xc300>,
1012 <0x0 0x1b000000 0x0 0x200>;
1013 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1014 interrupts = <0x0 0xa0 0x4>,
1017 clocks = <&sge0clk 0>;
1018 local-mac-address = [00 00 00 00 00 00];
1019 phy-connection-type = "sgmii";
1020 phy-handle = <&sgenet0phy>;
1023 sgenet1: ethernet@1f210030 {
1024 compatible = "apm,xgene1-sgenet";
1025 status = "disabled";
1026 reg = <0x0 0x1f210030 0x0 0xd100>,
1027 <0x0 0x1f200000 0x0 0xc300>,
1028 <0x0 0x1b000000 0x0 0x8000>;
1029 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1030 interrupts = <0x0 0xac 0x4>,
1034 local-mac-address = [00 00 00 00 00 00];
1035 phy-connection-type = "sgmii";
1036 phy-handle = <&sgenet1phy>;
1039 xgenet: ethernet@1f610000 {
1040 compatible = "apm,xgene1-xgenet";
1041 status = "disabled";
1042 reg = <0x0 0x1f610000 0x0 0xd100>,
1043 <0x0 0x1f600000 0x0 0xc300>,
1044 <0x0 0x18000000 0x0 0x200>;
1045 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1046 interrupts = <0x0 0x60 0x4>,
1056 clocks = <&xge0clk 0>;
1057 /* mac address will be overwritten by the bootloader */
1058 local-mac-address = [00 00 00 00 00 00];
1059 phy-connection-type = "xgmii";
1062 xgenet1: ethernet@1f620000 {
1063 compatible = "apm,xgene1-xgenet";
1064 status = "disabled";
1065 reg = <0x0 0x1f620000 0x0 0xd100>,
1066 <0x0 0x1f600000 0x0 0xc300>,
1067 <0x0 0x18000000 0x0 0x8000>;
1068 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1069 interrupts = <0x0 0x6c 0x4>,
1073 clocks = <&xge1clk 0>;
1074 /* mac address will be overwritten by the bootloader */
1075 local-mac-address = [00 00 00 00 00 00];
1076 phy-connection-type = "xgmii";
1080 compatible = "apm,xgene-rng";
1081 reg = <0x0 0x10520000 0x0 0x100>;
1082 interrupts = <0x0 0x41 0x4>;
1083 clocks = <&rngpkaclk 0>;
1087 compatible = "apm,xgene-storm-dma";
1088 device_type = "dma";
1089 reg = <0x0 0x1f270000 0x0 0x10000>,
1090 <0x0 0x1f200000 0x0 0x10000>,
1091 <0x0 0x1b000000 0x0 0x400000>,
1092 <0x0 0x1054a000 0x0 0x100>;
1093 interrupts = <0x0 0x82 0x4>,
1099 clocks = <&dmaclk 0>;