1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
5 * Copyright (C) 2015, Applied Micro Circuits Corporation
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
20 compatible = "apm,strega";
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
26 clocks = <&pmd0clk 0>;
30 compatible = "apm,strega";
32 enable-method = "spin-table";
33 cpu-release-addr = <0x1 0x0000fff8>;
34 next-level-cache = <&xgene_L2_0>;
36 clocks = <&pmd0clk 0>;
40 compatible = "apm,strega";
42 enable-method = "spin-table";
43 cpu-release-addr = <0x1 0x0000fff8>;
44 next-level-cache = <&xgene_L2_1>;
46 clocks = <&pmd1clk 0>;
50 compatible = "apm,strega";
52 enable-method = "spin-table";
53 cpu-release-addr = <0x1 0x0000fff8>;
54 next-level-cache = <&xgene_L2_1>;
56 clocks = <&pmd1clk 0>;
60 compatible = "apm,strega";
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
66 clocks = <&pmd2clk 0>;
70 compatible = "apm,strega";
72 enable-method = "spin-table";
73 cpu-release-addr = <0x1 0x0000fff8>;
74 next-level-cache = <&xgene_L2_2>;
76 clocks = <&pmd2clk 0>;
80 compatible = "apm,strega";
82 enable-method = "spin-table";
83 cpu-release-addr = <0x1 0x0000fff8>;
84 next-level-cache = <&xgene_L2_3>;
86 clocks = <&pmd3clk 0>;
90 compatible = "apm,strega";
92 enable-method = "spin-table";
93 cpu-release-addr = <0x1 0x0000fff8>;
94 next-level-cache = <&xgene_L2_3>;
96 clocks = <&pmd3clk 0>;
98 xgene_L2_0: l2-cache-0 {
103 xgene_L2_1: l2-cache-1 {
104 compatible = "cache";
108 xgene_L2_2: l2-cache-2 {
109 compatible = "cache";
113 xgene_L2_3: l2-cache-3 {
114 compatible = "cache";
120 gic: interrupt-controller@78090000 {
121 compatible = "arm,cortex-a15-gic";
122 #interrupt-cells = <3>;
123 #address-cells = <2>;
125 interrupt-controller;
126 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
127 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
128 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
129 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
130 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
131 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
133 compatible = "arm,gic-v2m-frame";
135 reg = <0x0 0x0 0x0 0x1000>;
138 compatible = "arm,gic-v2m-frame";
140 reg = <0x0 0x10000 0x0 0x1000>;
143 compatible = "arm,gic-v2m-frame";
145 reg = <0x0 0x20000 0x0 0x1000>;
148 compatible = "arm,gic-v2m-frame";
150 reg = <0x0 0x30000 0x0 0x1000>;
153 compatible = "arm,gic-v2m-frame";
155 reg = <0x0 0x40000 0x0 0x1000>;
158 compatible = "arm,gic-v2m-frame";
160 reg = <0x0 0x50000 0x0 0x1000>;
163 compatible = "arm,gic-v2m-frame";
165 reg = <0x0 0x60000 0x0 0x1000>;
168 compatible = "arm,gic-v2m-frame";
170 reg = <0x0 0x70000 0x0 0x1000>;
173 compatible = "arm,gic-v2m-frame";
175 reg = <0x0 0x80000 0x0 0x1000>;
178 compatible = "arm,gic-v2m-frame";
180 reg = <0x0 0x90000 0x0 0x1000>;
183 compatible = "arm,gic-v2m-frame";
185 reg = <0x0 0xa0000 0x0 0x1000>;
188 compatible = "arm,gic-v2m-frame";
190 reg = <0x0 0xb0000 0x0 0x1000>;
193 compatible = "arm,gic-v2m-frame";
195 reg = <0x0 0xc0000 0x0 0x1000>;
198 compatible = "arm,gic-v2m-frame";
200 reg = <0x0 0xd0000 0x0 0x1000>;
203 compatible = "arm,gic-v2m-frame";
205 reg = <0x0 0xe0000 0x0 0x1000>;
208 compatible = "arm,gic-v2m-frame";
210 reg = <0x0 0xf0000 0x0 0x1000>;
215 compatible = "arm,armv8-pmuv3";
216 interrupts = <1 12 0xff04>;
220 compatible = "arm,armv8-timer";
221 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
222 <1 13 0xff08>, /* Non-secure Phys IRQ */
223 <1 14 0xff08>, /* Virt IRQ */
224 <1 15 0xff08>; /* Hyp IRQ */
225 clock-frequency = <50000000>;
229 compatible = "simple-bus";
230 #address-cells = <2>;
235 #address-cells = <2>;
240 compatible = "fixed-clock";
242 clock-frequency = <100000000>;
243 clock-output-names = "refclk";
246 pmdpll: pmdpll@170000f0 {
247 compatible = "apm,xgene-pcppll-v2-clock";
249 clocks = <&refclk 0>;
250 reg = <0x0 0x170000f0 0x0 0x10>;
251 clock-output-names = "pmdpll";
254 pmd0clk: pmd0clk@7e200200 {
255 compatible = "apm,xgene-pmd-clock";
257 clocks = <&pmdpll 0>;
258 reg = <0x0 0x7e200200 0x0 0x10>;
259 clock-output-names = "pmd0clk";
262 pmd1clk: pmd1clk@7e200210 {
263 compatible = "apm,xgene-pmd-clock";
265 clocks = <&pmdpll 0>;
266 reg = <0x0 0x7e200210 0x0 0x10>;
267 clock-output-names = "pmd1clk";
270 pmd2clk: pmd2clk@7e200220 {
271 compatible = "apm,xgene-pmd-clock";
273 clocks = <&pmdpll 0>;
274 reg = <0x0 0x7e200220 0x0 0x10>;
275 clock-output-names = "pmd2clk";
278 pmd3clk: pmd3clk@7e200230 {
279 compatible = "apm,xgene-pmd-clock";
281 clocks = <&pmdpll 0>;
282 reg = <0x0 0x7e200230 0x0 0x10>;
283 clock-output-names = "pmd3clk";
286 socpll: socpll@17000120 {
287 compatible = "apm,xgene-socpll-v2-clock";
289 clocks = <&refclk 0>;
290 reg = <0x0 0x17000120 0x0 0x1000>;
291 clock-output-names = "socpll";
294 socplldiv2: socplldiv2 {
295 compatible = "fixed-factor-clock";
297 clocks = <&socpll 0>;
300 clock-output-names = "socplldiv2";
303 ahbclk: ahbclk@17000000 {
304 compatible = "apm,xgene-device-clock";
306 clocks = <&socplldiv2 0>;
307 reg = <0x0 0x17000000 0x0 0x2000>;
308 reg-names = "div-reg";
309 divider-offset = <0x164>;
310 divider-width = <0x5>;
311 divider-shift = <0x0>;
312 clock-output-names = "ahbclk";
315 sbapbclk: sbapbclk@1704c000 {
316 compatible = "apm,xgene-device-clock";
318 clocks = <&ahbclk 0>;
319 reg = <0x0 0x1704c000 0x0 0x2000>;
320 reg-names = "div-reg";
321 divider-offset = <0x10>;
322 divider-width = <0x2>;
323 divider-shift = <0x0>;
324 clock-output-names = "sbapbclk";
327 sdioclk: sdioclk@1f2ac000 {
328 compatible = "apm,xgene-device-clock";
330 clocks = <&socplldiv2 0>;
331 reg = <0x0 0x1f2ac000 0x0 0x1000
332 0x0 0x17000000 0x0 0x2000>;
333 reg-names = "csr-reg", "div-reg";
336 enable-offset = <0x8>;
338 divider-offset = <0x178>;
339 divider-width = <0x8>;
340 divider-shift = <0x0>;
341 clock-output-names = "sdioclk";
344 pcie0clk: pcie0clk@1f2bc000 {
345 compatible = "apm,xgene-device-clock";
347 clocks = <&socplldiv2 0>;
348 reg = <0x0 0x1f2bc000 0x0 0x1000>;
349 reg-names = "csr-reg";
350 clock-output-names = "pcie0clk";
353 pcie1clk: pcie1clk@1f2cc000 {
354 compatible = "apm,xgene-device-clock";
356 clocks = <&socplldiv2 0>;
357 reg = <0x0 0x1f2cc000 0x0 0x1000>;
358 reg-names = "csr-reg";
359 clock-output-names = "pcie1clk";
362 xge0clk: xge0clk@1f61c000 {
363 compatible = "apm,xgene-device-clock";
365 clocks = <&socplldiv2 0>;
366 reg = <0x0 0x1f61c000 0x0 0x1000>;
367 reg-names = "csr-reg";
370 clock-output-names = "xge0clk";
373 xge1clk: xge1clk@1f62c000 {
374 compatible = "apm,xgene-device-clock";
376 clocks = <&socplldiv2 0>;
377 reg = <0x0 0x1f62c000 0x0 0x1000>;
378 reg-names = "csr-reg";
381 clock-output-names = "xge1clk";
384 rngpkaclk: rngpkaclk@17000000 {
385 compatible = "apm,xgene-device-clock";
387 clocks = <&socplldiv2 0>;
388 reg = <0x0 0x17000000 0x0 0x2000>;
389 reg-names = "csr-reg";
392 enable-offset = <0x10>;
393 enable-mask = <0x10>;
394 clock-output-names = "rngpkaclk";
397 i2c4clk: i2c4clk@1704c000 {
398 compatible = "apm,xgene-device-clock";
400 clocks = <&sbapbclk 0>;
401 reg = <0x0 0x1704c000 0x0 0x1000>;
402 reg-names = "csr-reg";
405 enable-offset = <0x8>;
406 enable-mask = <0x40>;
407 clock-output-names = "i2c4clk";
411 scu: system-clk-controller@17000000 {
412 compatible = "apm,xgene-scu","syscon";
413 reg = <0x0 0x17000000 0x0 0x400>;
416 reboot: reboot@17000014 {
417 compatible = "syscon-reboot";
424 compatible = "apm,xgene-csw", "syscon";
425 reg = <0x0 0x7e200000 0x0 0x1000>;
428 mcba: mcba@7e700000 {
429 compatible = "apm,xgene-mcb", "syscon";
430 reg = <0x0 0x7e700000 0x0 0x1000>;
433 mcbb: mcbb@7e720000 {
434 compatible = "apm,xgene-mcb", "syscon";
435 reg = <0x0 0x7e720000 0x0 0x1000>;
438 efuse: efuse@1054a000 {
439 compatible = "apm,xgene-efuse", "syscon";
440 reg = <0x0 0x1054a000 0x0 0x20>;
444 compatible = "apm,xgene-edac";
445 #address-cells = <2>;
449 regmap-mcba = <&mcba>;
450 regmap-mcbb = <&mcbb>;
451 regmap-efuse = <&efuse>;
452 reg = <0x0 0x78800000 0x0 0x100>;
453 interrupts = <0x0 0x20 0x4>,
458 compatible = "apm,xgene-edac-mc";
459 reg = <0x0 0x7e800000 0x0 0x1000>;
460 memory-controller = <0>;
464 compatible = "apm,xgene-edac-mc";
465 reg = <0x0 0x7e840000 0x0 0x1000>;
466 memory-controller = <1>;
470 compatible = "apm,xgene-edac-mc";
471 reg = <0x0 0x7e880000 0x0 0x1000>;
472 memory-controller = <2>;
476 compatible = "apm,xgene-edac-mc";
477 reg = <0x0 0x7e8c0000 0x0 0x1000>;
478 memory-controller = <3>;
482 compatible = "apm,xgene-edac-pmd";
483 reg = <0x0 0x7c000000 0x0 0x200000>;
484 pmd-controller = <0>;
488 compatible = "apm,xgene-edac-pmd";
489 reg = <0x0 0x7c200000 0x0 0x200000>;
490 pmd-controller = <1>;
494 compatible = "apm,xgene-edac-pmd";
495 reg = <0x0 0x7c400000 0x0 0x200000>;
496 pmd-controller = <2>;
500 compatible = "apm,xgene-edac-pmd";
501 reg = <0x0 0x7c600000 0x0 0x200000>;
502 pmd-controller = <3>;
506 compatible = "apm,xgene-edac-l3-v2";
507 reg = <0x0 0x7e600000 0x0 0x1000>;
511 compatible = "apm,xgene-edac-soc";
512 reg = <0x0 0x7e930000 0x0 0x1000>;
517 compatible = "apm,xgene-pmu-v2";
518 #address-cells = <2>;
522 regmap-mcba = <&mcba>;
523 regmap-mcbb = <&mcbb>;
524 reg = <0x0 0x78810000 0x0 0x1000>;
525 interrupts = <0x0 0x22 0x4>;
528 compatible = "apm,xgene-pmu-l3c";
529 reg = <0x0 0x7e610000 0x0 0x1000>;
533 compatible = "apm,xgene-pmu-iob";
534 reg = <0x0 0x7e940000 0x0 0x1000>;
538 compatible = "apm,xgene-pmu-mcb";
539 reg = <0x0 0x7e710000 0x0 0x1000>;
540 enable-bit-index = <0>;
544 compatible = "apm,xgene-pmu-mcb";
545 reg = <0x0 0x7e730000 0x0 0x1000>;
546 enable-bit-index = <1>;
550 compatible = "apm,xgene-pmu-mc";
551 reg = <0x0 0x7e810000 0x0 0x1000>;
552 enable-bit-index = <0>;
556 compatible = "apm,xgene-pmu-mc";
557 reg = <0x0 0x7e850000 0x0 0x1000>;
558 enable-bit-index = <1>;
562 compatible = "apm,xgene-pmu-mc";
563 reg = <0x0 0x7e890000 0x0 0x1000>;
564 enable-bit-index = <2>;
568 compatible = "apm,xgene-pmu-mc";
569 reg = <0x0 0x7e8d0000 0x0 0x1000>;
570 enable-bit-index = <3>;
574 mailbox: mailbox@10540000 {
575 compatible = "apm,xgene-slimpro-mbox";
576 reg = <0x0 0x10540000 0x0 0x8000>;
578 interrupts = <0x0 0x0 0x4
589 compatible = "apm,xgene-slimpro-i2c";
590 mboxes = <&mailbox 0>;
594 compatible = "apm,xgene-slimpro-hwmon";
595 mboxes = <&mailbox 7>;
598 serial0: serial@10600000 {
599 compatible = "ns16550";
600 reg = <0 0x10600000 0x0 0x1000>;
602 clock-frequency = <10000000>;
603 interrupt-parent = <&gic>;
604 interrupts = <0x0 0x4c 0x4>;
607 /* Node-name might need to be coded as dwusb for backward compatibility */
610 compatible = "snps,dwc3";
611 reg = <0x0 0x19000000 0x0 0x100000>;
612 interrupts = <0x0 0x5d 0x4>;
617 pcie0: pcie@1f2b0000 {
620 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
621 #interrupt-cells = <1>;
623 #address-cells = <3>;
624 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
625 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
626 reg-names = "csr", "cfg";
627 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
628 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
629 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
630 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
631 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
632 bus-range = <0x00 0xff>;
633 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
634 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
635 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
636 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
637 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
639 clocks = <&pcie0clk 0>;
640 msi-parent = <&v2m0>;
643 pcie1: pcie@1f2c0000 {
646 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
647 #interrupt-cells = <1>;
649 #address-cells = <3>;
650 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
651 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
652 reg-names = "csr", "cfg";
653 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
654 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
655 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
656 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
657 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
658 bus-range = <0x00 0xff>;
659 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
660 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
661 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
662 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
663 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
665 clocks = <&pcie1clk 0>;
666 msi-parent = <&v2m0>;
669 sata1: sata@1a000000 {
670 compatible = "apm,xgene-ahci-v2";
671 reg = <0x0 0x1a000000 0x0 0x1000>,
672 <0x0 0x1f200000 0x0 0x1000>,
673 <0x0 0x1f20d000 0x0 0x1000>,
674 <0x0 0x1f20e000 0x0 0x1000>;
675 interrupts = <0x0 0x5a 0x4>;
679 sata2: sata@1a200000 {
680 compatible = "apm,xgene-ahci-v2";
681 reg = <0x0 0x1a200000 0x0 0x1000>,
682 <0x0 0x1f210000 0x0 0x1000>,
683 <0x0 0x1f21d000 0x0 0x1000>,
684 <0x0 0x1f21e000 0x0 0x1000>;
685 interrupts = <0x0 0x5b 0x4>;
689 sata3: sata@1a400000 {
690 compatible = "apm,xgene-ahci-v2";
691 reg = <0x0 0x1a400000 0x0 0x1000>,
692 <0x0 0x1f220000 0x0 0x1000>,
693 <0x0 0x1f22d000 0x0 0x1000>,
694 <0x0 0x1f22e000 0x0 0x1000>;
695 interrupts = <0x0 0x5c 0x4>;
700 compatible = "arasan,sdhci-4.9a";
701 reg = <0x0 0x1c000000 0x0 0x100>;
702 interrupts = <0x0 0x49 0x4>;
705 clock-names = "clk_xin", "clk_ahb";
706 clocks = <&sdioclk 0>, <&ahbclk 0>;
709 gfcgpio: gpio@1f63c000 {
710 compatible = "apm,xgene-gpio";
711 reg = <0x0 0x1f63c000 0x0 0x40>;
716 dwgpio: gpio@1c024000 {
717 compatible = "snps,dw-apb-gpio";
718 reg = <0x0 0x1c024000 0x0 0x1000>;
719 #address-cells = <1>;
722 porta: gpio-controller@0 {
723 compatible = "snps,dw-apb-gpio-port";
726 snps,nr-gpios = <32>;
731 sbgpio: gpio@17001000 {
732 compatible = "apm,xgene-gpio-sb";
733 reg = <0x0 0x17001000 0x0 0x400>;
736 interrupts = <0x0 0x28 0x1>,
744 interrupt-parent = <&gic>;
745 #interrupt-cells = <2>;
746 interrupt-controller;
752 mdio: mdio@1f610000 {
753 compatible = "apm,xgene-mdio-xfi";
754 #address-cells = <1>;
756 reg = <0x0 0x1f610000 0x0 0xd100>;
757 clocks = <&xge0clk 0>;
760 sgenet0: ethernet@1f610000 {
761 compatible = "apm,xgene2-sgenet";
763 reg = <0x0 0x1f610000 0x0 0xd100>,
764 <0x0 0x1f600000 0x0 0xd100>,
765 <0x0 0x20000000 0x0 0x20000>;
766 interrupts = <0 96 4>,
769 clocks = <&xge0clk 0>;
770 local-mac-address = [00 01 73 00 00 01];
771 phy-connection-type = "sgmii";
772 phy-handle = <&sgenet0phy>;
775 xgenet1: ethernet@1f620000 {
776 compatible = "apm,xgene2-xgenet";
778 reg = <0x0 0x1f620000 0x0 0x10000>,
779 <0x0 0x1f600000 0x0 0xd100>,
780 <0x0 0x20000000 0x0 0x220000>;
781 interrupts = <0 108 4>,
792 clocks = <&xge1clk 0>;
793 local-mac-address = [00 01 73 00 00 02];
794 phy-connection-type = "xgmii";
798 compatible = "apm,xgene-rng";
799 reg = <0x0 0x10520000 0x0 0x100>;
800 interrupts = <0x0 0x41 0x4>;
801 clocks = <&rngpkaclk 0>;
805 #address-cells = <1>;
807 compatible = "snps,designware-i2c";
808 reg = <0x0 0x10511000 0x0 0x1000>;
809 interrupts = <0 0x45 0x4>;
811 clocks = <&sbapbclk 0>;
816 #address-cells = <1>;
818 compatible = "snps,designware-i2c";
819 reg = <0x0 0x10640000 0x0 0x1000>;
820 interrupts = <0 0x3a 0x4>;
821 clocks = <&i2c4clk 0>;