1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
18 compatible = "amlogic,meson-gxl-usb-ctrl";
19 reg = <0x0 0xd0078080 0x0 0x20>;
20 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
25 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
26 clock-names = "usb_ctrl", "ddr";
27 resets = <&reset RESET_USB_OTG>;
31 phys = <&usb2_phy0>, <&usb2_phy1>;
32 phy-names = "usb2-phy0", "usb2-phy1";
35 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
36 reg = <0x0 0xc9100000 0x0 0x40000>;
37 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&clkc CLKID_USB1>;
41 dr_mode = "peripheral";
42 g-rx-fifo-size = <192>;
43 g-np-tx-fifo-size = <128>;
44 g-tx-fifo-size = <128 128 16 16 16>;
48 compatible = "snps,dwc3";
49 reg = <0x0 0xc9000000 0x0 0x100000>;
50 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
52 maximum-speed = "high-speed";
53 snps,dis_u2_susphy_quirk;
57 acodec: audio-controller@c8832000 {
58 compatible = "amlogic,t9015";
59 reg = <0x0 0xc8832000 0x0 0x14>;
60 #sound-dai-cells = <0>;
61 sound-name-prefix = "ACODEC";
62 clocks = <&clkc CLKID_ACODEC>;
64 resets = <&reset RESET_ACODEC>;
68 crypto: crypto@c883e000 {
69 compatible = "amlogic,gxl-crypto";
70 reg = <0x0 0xc883e000 0x0 0x36>;
71 interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
72 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
73 clocks = <&clkc CLKID_BLKMV>;
74 clock-names = "blkmv";
81 compatible = "amlogic,aiu-gxl", "amlogic,aiu";
82 clocks = <&clkc CLKID_AIU_GLUE>,
83 <&clkc CLKID_I2S_OUT>,
84 <&clkc CLKID_AOCLK_GATE>,
85 <&clkc CLKID_CTS_AMCLK>,
86 <&clkc CLKID_MIXER_IFACE>,
88 <&clkc CLKID_IEC958_GATE>,
89 <&clkc CLKID_CTS_MCLK_I958>,
90 <&clkc CLKID_CTS_I958>;
100 resets = <&reset RESET_AIU>;
104 usb2_phy0: phy@78000 {
105 compatible = "amlogic,meson-gxl-usb2-phy";
107 reg = <0x0 0x78000 0x0 0x20>;
108 clocks = <&clkc CLKID_USB>;
110 resets = <&reset RESET_USB_OTG>;
115 usb2_phy1: phy@78020 {
116 compatible = "amlogic,meson-gxl-usb2-phy";
118 reg = <0x0 0x78020 0x0 0x20>;
119 clocks = <&clkc CLKID_USB>;
121 resets = <&reset RESET_USB_OTG>;
128 clocks = <&clkc CLKID_EFUSE>;
132 clocks = <&clkc CLKID_ETH>,
133 <&clkc CLKID_FCLK_DIV2>,
135 <&clkc CLKID_FCLK_DIV2>;
136 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
139 #address-cells = <1>;
141 compatible = "snps,dwmac-mdio";
146 pinctrl_aobus: pinctrl@14 {
147 compatible = "amlogic,meson-gxl-aobus-pinctrl";
148 #address-cells = <2>;
153 reg = <0x0 0x00014 0x0 0x8>,
154 <0x0 0x0002c 0x0 0x4>,
155 <0x0 0x00024 0x0 0x8>;
156 reg-names = "mux", "pull", "gpio";
159 gpio-ranges = <&pinctrl_aobus 0 0 14>;
162 uart_ao_a_pins: uart_ao_a {
164 groups = "uart_tx_ao_a", "uart_rx_ao_a";
165 function = "uart_ao";
170 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
172 groups = "uart_cts_ao_a",
174 function = "uart_ao";
179 uart_ao_b_pins: uart_ao_b {
181 groups = "uart_tx_ao_b", "uart_rx_ao_b";
182 function = "uart_ao_b";
187 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
189 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
190 function = "uart_ao_b";
195 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
197 groups = "uart_cts_ao_b",
199 function = "uart_ao_b";
204 remote_input_ao_pins: remote_input_ao {
206 groups = "remote_input_ao";
207 function = "remote_input_ao";
212 i2c_ao_pins: i2c_ao {
214 groups = "i2c_sck_ao",
221 pwm_ao_a_3_pins: pwm_ao_a_3 {
223 groups = "pwm_ao_a_3";
224 function = "pwm_ao_a";
229 pwm_ao_a_8_pins: pwm_ao_a_8 {
231 groups = "pwm_ao_a_8";
232 function = "pwm_ao_a";
237 pwm_ao_b_pins: pwm_ao_b {
240 function = "pwm_ao_b";
245 pwm_ao_b_6_pins: pwm_ao_b_6 {
247 groups = "pwm_ao_b_6";
248 function = "pwm_ao_b";
253 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
255 groups = "i2s_out_ch23_ao";
256 function = "i2s_out_ao";
261 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
263 groups = "i2s_out_ch45_ao";
264 function = "i2s_out_ao";
269 spdif_out_ao_6_pins: spdif_out_ao_6 {
271 groups = "spdif_out_ao_6";
272 function = "spdif_out_ao";
277 spdif_out_ao_9_pins: spdif_out_ao_9 {
279 groups = "spdif_out_ao_9";
280 function = "spdif_out_ao";
285 ao_cec_pins: ao_cec {
293 ee_cec_pins: ee_cec {
304 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
305 clock-names = "core";
309 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
310 clocks = <&xtal>, <&clkc CLKID_CLK81>;
311 clock-names = "xtal", "mpeg-clk";
315 compatible = "amlogic,meson-gxl-gpio-intc",
316 "amlogic,meson-gpio-intc";
321 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
322 resets = <&reset RESET_HDMITX_CAPB3>,
323 <&reset RESET_HDMI_SYSTEM_RESET>,
324 <&reset RESET_HDMI_TX>;
325 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
326 clocks = <&clkc CLKID_HDMI_PCLK>,
328 <&clkc CLKID_GCLK_VENCI_INT0>;
329 clock-names = "isfr", "iahb", "venci";
333 clkc: clock-controller {
334 compatible = "amlogic,gxl-clkc";
337 clock-names = "xtal";
342 clocks = <&clkc CLKID_RNG0>;
343 clock-names = "core";
347 clocks = <&clkc CLKID_I2C>;
351 clocks = <&clkc CLKID_AO_I2C>;
355 clocks = <&clkc CLKID_I2C>;
359 clocks = <&clkc CLKID_I2C>;
363 pinctrl_periphs: pinctrl@4b0 {
364 compatible = "amlogic,meson-gxl-periphs-pinctrl";
365 #address-cells = <2>;
370 reg = <0x0 0x004b0 0x0 0x28>,
371 <0x0 0x004e8 0x0 0x14>,
372 <0x0 0x00520 0x0 0x14>,
373 <0x0 0x00430 0x0 0x40>;
374 reg-names = "mux", "pull", "pull-enable", "gpio";
377 gpio-ranges = <&pinctrl_periphs 0 0 100>;
382 groups = "emmc_nand_d07",
395 emmc_ds_pins: emmc-ds {
403 emmc_clk_gate_pins: emmc_clk_gate {
406 function = "gpio_periphs";
432 spi_idle_high_pins: spi-idle-high-pins {
439 spi_idle_low_pins: spi-idle-low-pins {
446 spi_ss0_pins: spi-ss0 {
454 sdcard_pins: sdcard {
456 groups = "sdcard_d0",
466 groups = "sdcard_clk";
472 sdcard_clk_gate_pins: sdcard_clk_gate {
475 function = "gpio_periphs";
498 sdio_clk_gate_pins: sdio_clk_gate {
501 function = "gpio_periphs";
506 sdio_irq_pins: sdio_irq {
514 uart_a_pins: uart_a {
516 groups = "uart_tx_a",
523 uart_a_cts_rts_pins: uart_a_cts_rts {
525 groups = "uart_cts_a",
532 uart_b_pins: uart_b {
534 groups = "uart_tx_b",
541 uart_b_cts_rts_pins: uart_b_cts_rts {
543 groups = "uart_cts_b",
550 uart_c_pins: uart_c {
552 groups = "uart_tx_c",
559 uart_c_cts_rts_pins: uart_c_cts_rts {
561 groups = "uart_cts_c",
570 groups = "i2c_sck_a",
579 groups = "i2c_sck_b",
588 groups = "i2c_sck_c",
595 i2c_c_dv18_pins: i2c_c_dv18 {
597 groups = "i2c_sck_c_dv19",
625 eth_link_led_pins: eth_link_led {
627 groups = "eth_link_led";
628 function = "eth_led";
633 eth_act_led_pins: eth_act_led {
635 groups = "eth_act_led";
636 function = "eth_led";
680 pwm_f_clk_pins: pwm_f_clk {
682 groups = "pwm_f_clk";
688 pwm_f_x_pins: pwm_f_x {
696 hdmi_hpd_pins: hdmi_hpd {
699 function = "hdmi_hpd";
704 hdmi_i2c_pins: hdmi_i2c {
706 groups = "hdmi_sda", "hdmi_scl";
707 function = "hdmi_i2c";
712 i2s_am_clk_pins: i2s_am_clk {
714 groups = "i2s_am_clk";
715 function = "i2s_out";
720 i2s_out_ao_clk_pins: i2s_out_ao_clk {
722 groups = "i2s_out_ao_clk";
723 function = "i2s_out";
728 i2s_out_lr_clk_pins: i2s_out_lr_clk {
730 groups = "i2s_out_lr_clk";
731 function = "i2s_out";
736 i2s_out_ch01_pins: i2s_out_ch01 {
738 groups = "i2s_out_ch01";
739 function = "i2s_out";
743 i2sout_ch23_z_pins: i2sout_ch23_z {
745 groups = "i2sout_ch23_z";
746 function = "i2s_out";
751 i2sout_ch45_z_pins: i2sout_ch45_z {
753 groups = "i2sout_ch45_z";
754 function = "i2s_out";
759 i2sout_ch67_z_pins: i2sout_ch67_z {
761 groups = "i2sout_ch67_z";
762 function = "i2s_out";
767 spdif_out_h_pins: spdif_out_ao_h {
769 groups = "spdif_out_h";
770 function = "spdif_out";
776 eth_phy_mux: mdio@558 {
777 reg = <0x0 0x558 0x0 0xc>;
778 compatible = "amlogic,gxl-mdio-mux";
779 #address-cells = <1>;
781 clocks = <&clkc CLKID_FCLK_DIV4>;
783 mdio-parent-bus = <&mdio0>;
785 external_mdio: mdio@0 {
787 #address-cells = <1>;
791 internal_mdio: mdio@1 {
793 #address-cells = <1>;
796 internal_phy: ethernet-phy@8 {
797 compatible = "ethernet-phy-id0181.4400";
798 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
807 resets = <&reset RESET_VIU>,
809 <&reset RESET_VCBUS>,
810 <&reset RESET_BT656>,
811 <&reset RESET_DVIN_RESET>,
813 <&reset RESET_VENCI>,
814 <&reset RESET_VENCP>,
817 <&reset RESET_VENCL>,
818 <&reset RESET_VID_LOCK>;
819 reset-names = "viu", "venc", "vcbus", "bt656",
820 "dvin", "rdma", "venci", "vencp",
821 "vdac", "vdi6", "vencl", "vid_lock";
822 clocks = <&clkc CLKID_VPU>,
824 clock-names = "vpu", "vapb";
826 * VPU clocking is provided by two identical clock paths
827 * VPU_0 and VPU_1 muxed to a single clock by a glitch
828 * free mux to safely change frequency while running.
829 * Same for VAPB but with a final gate after the glitch free mux.
831 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
833 <&clkc CLKID_VPU>, /* Glitch free mux */
834 <&clkc CLKID_VAPB_0_SEL>,
835 <&clkc CLKID_VAPB_0>,
836 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
837 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
838 <0>, /* Do Nothing */
840 <&clkc CLKID_FCLK_DIV4>,
841 <0>, /* Do Nothing */
842 <&clkc CLKID_VAPB_0>;
843 assigned-clock-rates = <0>, /* Do Nothing */
845 <0>, /* Do Nothing */
846 <0>, /* Do Nothing */
848 <0>; /* Do Nothing */
852 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
854 <&clkc CLKID_SAR_ADC>,
855 <&clkc CLKID_SAR_ADC_CLK>,
856 <&clkc CLKID_SAR_ADC_SEL>;
857 clock-names = "clkin", "core", "adc_clk", "adc_sel";
861 clocks = <&clkc CLKID_SD_EMMC_A>,
862 <&clkc CLKID_SD_EMMC_A_CLK0>,
863 <&clkc CLKID_FCLK_DIV2>;
864 clock-names = "core", "clkin0", "clkin1";
865 resets = <&reset RESET_SD_EMMC_A>;
869 clocks = <&clkc CLKID_SD_EMMC_B>,
870 <&clkc CLKID_SD_EMMC_B_CLK0>,
871 <&clkc CLKID_FCLK_DIV2>;
872 clock-names = "core", "clkin0", "clkin1";
873 resets = <&reset RESET_SD_EMMC_B>;
877 clocks = <&clkc CLKID_SD_EMMC_C>,
878 <&clkc CLKID_SD_EMMC_C_CLK0>,
879 <&clkc CLKID_FCLK_DIV2>;
880 clock-names = "core", "clkin0", "clkin1";
881 resets = <&reset RESET_SD_EMMC_C>;
885 clocks = <&clkc CLKID_HDMI_PCLK>,
887 <&clkc CLKID_GCLK_VENCI_INT0>;
891 clocks = <&clkc CLKID_SPICC>;
892 clock-names = "core";
893 resets = <&reset RESET_PERIPHS_SPICC>;
898 clocks = <&clkc CLKID_SPI>;
902 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
903 clock-names = "xtal", "pclk", "baud";
907 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
908 clock-names = "xtal", "pclk", "baud";
912 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
913 clock-names = "xtal", "pclk", "baud";
917 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
918 clock-names = "xtal", "pclk", "baud";
922 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
923 clock-names = "xtal", "pclk", "baud";
927 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
928 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
932 compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
933 clocks = <&clkc CLKID_DOS_PARSER>,
935 <&clkc CLKID_VDEC_1>,
936 <&clkc CLKID_VDEC_HEVC>;
937 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
938 resets = <&reset RESET_PARSER>;
939 reset-names = "esparser";