arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

   1 /*
   2  * Copyright (c) 2016 Endless Computers, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include "meson-gx.dtsi"
  45 #include <dt-bindings/clock/gxbb-clkc.h>
  46 #include <dt-bindings/clock/gxbb-aoclkc.h>
  47 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  48 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  49
  50 / {
  51         compatible = "amlogic,meson-gxl";
  52
  53         reserved-memory {
  54                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  55                 secmon_reserved_alt: secmon@05000000 {
  56                         reg = <0x0 0x05000000 0x0 0x300000>;
  57                         no-map;
  58                 };
  59         };
  60 };
  61
  62 &ethmac {
  63         reg = <0x0 0xc9410000 0x0 0x10000
  64                0x0 0xc8834540 0x0 0x4>;
  65
  66         clocks = <&clkc CLKID_ETH>,
  67                  <&clkc CLKID_FCLK_DIV2>,
  68                  <&clkc CLKID_MPLL2>;
  69         clock-names = "stmmaceth", "clkin0", "clkin1";
  70
  71         mdio0: mdio {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74                 compatible = "snps,dwmac-mdio";
  75         };
  76 };
  77
  78 &aobus {
  79         pinctrl_aobus: pinctrl@14 {
  80                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
  81                 #address-cells = <2>;
  82                 #size-cells = <2>;
  83                 ranges;
  84
  85                 gpio_ao: bank@14 {
  86                         reg = <0x0 0x00014 0x0 0x8>,
  87                               <0x0 0x0002c 0x0 0x4>,
  88                               <0x0 0x00024 0x0 0x8>;
  89                         reg-names = "mux", "pull", "gpio";
  90                         gpio-controller;
  91                         #gpio-cells = <2>;
  92                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
  93                 };
  94
  95                 uart_ao_a_pins: uart_ao_a {
  96                         mux {
  97                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
  98                                 function = "uart_ao";
  99                         };
 100                 };
 101
 102                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 103                         mux {
 104                                 groups = "uart_cts_ao_a",
 105                                        "uart_rts_ao_a";
 106                                 function = "uart_ao";
 107                         };
 108                 };
 109
 110                 uart_ao_b_pins: uart_ao_b {
 111                         mux {
 112                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 113                                 function = "uart_ao_b";
 114                         };
 115                 };
 116
 117                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 118                         mux {
 119                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 120                                 function = "uart_ao_b";
 121                         };
 122                 };
 123
 124                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 125                         mux {
 126                                 groups = "uart_cts_ao_b",
 127                                        "uart_rts_ao_b";
 128                                 function = "uart_ao_b";
 129                         };
 130                 };
 131
 132                 remote_input_ao_pins: remote_input_ao {
 133                         mux {
 134                                 groups = "remote_input_ao";
 135                                 function = "remote_input_ao";
 136                         };
 137                 };
 138
 139                 i2c_ao_pins: i2c_ao {
 140                         mux {
 141                                 groups = "i2c_sck_ao",
 142                                        "i2c_sda_ao";
 143                                 function = "i2c_ao";
 144                         };
 145                 };
 146
 147                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 148                         mux {
 149                                 groups = "pwm_ao_a_3";
 150                                 function = "pwm_ao_a";
 151                         };
 152                 };
 153
 154                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 155                         mux {
 156                                 groups = "pwm_ao_a_8";
 157                                 function = "pwm_ao_a";
 158                         };
 159                 };
 160
 161                 pwm_ao_b_pins: pwm_ao_b {
 162                         mux {
 163                                 groups = "pwm_ao_b";
 164                                 function = "pwm_ao_b";
 165                         };
 166                 };
 167
 168                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 169                         mux {
 170                                 groups = "pwm_ao_b_6";
 171                                 function = "pwm_ao_b";
 172                         };
 173                 };
 174
 175                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 176                         mux {
 177                                 groups = "i2s_out_ch23_ao";
 178                                 function = "i2s_out_ao";
 179                         };
 180                 };
 181
 182                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 183                         mux {
 184                                 groups = "i2s_out_ch45_ao";
 185                                 function = "i2s_out_ao";
 186                         };
 187                 };
 188
 189                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 190                         mux {
 191                                 groups = "spdif_out_ao_6";
 192                                 function = "spdif_out_ao";
 193                         };
 194                 };
 195
 196                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 197                         mux {
 198                                 groups = "spdif_out_ao_9";
 199                                 function = "spdif_out_ao";
 200                         };
 201                 };
 202
 203                 ao_cec_pins: ao_cec {
 204                         mux {
 205                                 groups = "ao_cec";
 206                                 function = "cec_ao";
 207                         };
 208                 };
 209
 210                 ee_cec_pins: ee_cec {
 211                         mux {
 212                                 groups = "ee_cec";
 213                                 function = "cec_ao";
 214                         };
 215                 };
 216         };
 217 };
 218
 219 &cec_AO {
 220         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 221         clock-names = "core";
 222 };
 223
 224 &clkc_AO {
 225         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
 226 };
 227
 228 &hdmi_tx {
 229         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 230         resets = <&reset RESET_HDMITX_CAPB3>,
 231                  <&reset RESET_HDMI_SYSTEM_RESET>,
 232                  <&reset RESET_HDMI_TX>;
 233         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 234         clocks = <&clkc CLKID_HDMI_PCLK>,
 235                  <&clkc CLKID_CLK81>,
 236                  <&clkc CLKID_GCLK_VENCI_INT0>;
 237         clock-names = "isfr", "iahb", "venci";
 238 };
 239
 240 &hiubus {
 241         clkc: clock-controller@0 {
 242                 compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
 243                 #clock-cells = <1>;
 244                 reg = <0x0 0x0 0x0 0x3db>;
 245         };
 246 };
 247
 248 &hwrng {
 249         clocks = <&clkc CLKID_RNG0>;
 250         clock-names = "core";
 251 };
 252
 253 &i2c_A {
 254         clocks = <&clkc CLKID_I2C>;
 255 };
 256
 257 &i2c_AO {
 258         clocks = <&clkc CLKID_AO_I2C>;
 259 };
 260
 261 &i2c_B {
 262         clocks = <&clkc CLKID_I2C>;
 263 };
 264
 265 &i2c_C {
 266         clocks = <&clkc CLKID_I2C>;
 267 };
 268
 269 &periphs {
 270         pinctrl_periphs: pinctrl@4b0 {
 271                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 272                 #address-cells = <2>;
 273                 #size-cells = <2>;
 274                 ranges;
 275
 276                 gpio: bank@4b0 {
 277                         reg = <0x0 0x004b0 0x0 0x28>,
 278                               <0x0 0x004e8 0x0 0x14>,
 279                               <0x0 0x00520 0x0 0x14>,
 280                               <0x0 0x00430 0x0 0x40>;
 281                         reg-names = "mux", "pull", "pull-enable", "gpio";
 282                         gpio-controller;
 283                         #gpio-cells = <2>;
 284                         gpio-ranges = <&pinctrl_periphs 0 10 101>;
 285                 };
 286
 287                 emmc_pins: emmc {
 288                         mux {
 289                                 groups = "emmc_nand_d07",
 290                                        "emmc_cmd",
 291                                        "emmc_clk",
 292                                        "emmc_ds";
 293                                 function = "emmc";
 294                         };
 295                 };
 296
 297                 emmc_clk_gate_pins: emmc_clk_gate {
 298                         mux {
 299                                 groups = "BOOT_8";
 300                                 function = "gpio_periphs";
 301                         };
 302                         cfg-pull-down {
 303                                 pins = "BOOT_8";
 304                                 bias-pull-down;
 305                         };
 306                 };
 307
 308                 nor_pins: nor {
 309                         mux {
 310                                 groups = "nor_d",
 311                                        "nor_q",
 312                                        "nor_c",
 313                                        "nor_cs";
 314                                 function = "nor";
 315                         };
 316                 };
 317
 318                 spi_pins: spi-pins {
 319                         mux {
 320                                 groups = "spi_miso",
 321                                         "spi_mosi",
 322                                         "spi_sclk";
 323                                 function = "spi";
 324                         };
 325                 };
 326
 327                 spi_ss0_pins: spi-ss0 {
 328                         mux {
 329                                 groups = "spi_ss0";
 330                                 function = "spi";
 331                         };
 332                 };
 333
 334                 sdcard_pins: sdcard {
 335                         mux {
 336                                 groups = "sdcard_d0",
 337                                        "sdcard_d1",
 338                                        "sdcard_d2",
 339                                        "sdcard_d3",
 340                                        "sdcard_cmd",
 341                                        "sdcard_clk";
 342                                 function = "sdcard";
 343                         };
 344                 };
 345
 346                 sdcard_clk_gate_pins: sdcard_clk_gate {
 347                         mux {
 348                                 groups = "CARD_2";
 349                                 function = "gpio_periphs";
 350                         };
 351                         cfg-pull-down {
 352                                 pins = "CARD_2";
 353                                 bias-pull-down;
 354                         };
 355                 };
 356
 357                 sdio_pins: sdio {
 358                         mux {
 359                                 groups = "sdio_d0",
 360                                        "sdio_d1",
 361                                        "sdio_d2",
 362                                        "sdio_d3",
 363                                        "sdio_cmd",
 364                                        "sdio_clk";
 365                                 function = "sdio";
 366                         };
 367                 };
 368
 369                 sdio_clk_gate_pins: sdio_clk_gate {
 370                         mux {
 371                                 groups = "GPIOX_4";
 372                                 function = "gpio_periphs";
 373                         };
 374                         cfg-pull-down {
 375                                 pins = "GPIOX_4";
 376                                 bias-pull-down;
 377                         };
 378                 };
 379
 380                 sdio_irq_pins: sdio_irq {
 381                         mux {
 382                                 groups = "sdio_irq";
 383                                 function = "sdio";
 384                         };
 385                 };
 386
 387                 uart_a_pins: uart_a {
 388                         mux {
 389                                 groups = "uart_tx_a",
 390                                        "uart_rx_a";
 391                                 function = "uart_a";
 392                         };
 393                 };
 394
 395                 uart_a_cts_rts_pins: uart_a_cts_rts {
 396                         mux {
 397                                 groups = "uart_cts_a",
 398                                        "uart_rts_a";
 399                                 function = "uart_a";
 400                         };
 401                 };
 402
 403                 uart_b_pins: uart_b {
 404                         mux {
 405                                 groups = "uart_tx_b",
 406                                        "uart_rx_b";
 407                                 function = "uart_b";
 408                         };
 409                 };
 410
 411                 uart_b_cts_rts_pins: uart_b_cts_rts {
 412                         mux {
 413                                 groups = "uart_cts_b",
 414                                        "uart_rts_b";
 415                                 function = "uart_b";
 416                         };
 417                 };
 418
 419                 uart_c_pins: uart_c {
 420                         mux {
 421                                 groups = "uart_tx_c",
 422                                        "uart_rx_c";
 423                                 function = "uart_c";
 424                         };
 425                 };
 426
 427                 uart_c_cts_rts_pins: uart_c_cts_rts {
 428                         mux {
 429                                 groups = "uart_cts_c",
 430                                        "uart_rts_c";
 431                                 function = "uart_c";
 432                         };
 433                 };
 434
 435                 i2c_a_pins: i2c_a {
 436                         mux {
 437                                 groups = "i2c_sck_a",
 438                                      "i2c_sda_a";
 439                                 function = "i2c_a";
 440                         };
 441                 };
 442
 443                 i2c_b_pins: i2c_b {
 444                         mux {
 445                                 groups = "i2c_sck_b",
 446                                       "i2c_sda_b";
 447                                 function = "i2c_b";
 448                         };
 449                 };
 450
 451                 i2c_c_pins: i2c_c {
 452                         mux {
 453                                 groups = "i2c_sck_c",
 454                                       "i2c_sda_c";
 455                                 function = "i2c_c";
 456                         };
 457                 };
 458
 459                 eth_pins: eth_c {
 460                         mux {
 461                                 groups = "eth_mdio",
 462                                        "eth_mdc",
 463                                        "eth_clk_rx_clk",
 464                                        "eth_rx_dv",
 465                                        "eth_rxd0",
 466                                        "eth_rxd1",
 467                                        "eth_rxd2",
 468                                        "eth_rxd3",
 469                                        "eth_rgmii_tx_clk",
 470                                        "eth_tx_en",
 471                                        "eth_txd0",
 472                                        "eth_txd1",
 473                                        "eth_txd2",
 474                                        "eth_txd3";
 475                                 function = "eth";
 476                         };
 477                 };
 478
 479                 eth_link_led_pins: eth_link_led {
 480                         mux {
 481                                 groups = "eth_link_led";
 482                                 function = "eth_led";
 483                         };
 484                 };
 485
 486                 eth_act_led_pins: eth_act_led {
 487                         mux {
 488                                 groups = "eth_act_led";
 489                                 function = "eth_led";
 490                         };
 491                 };
 492
 493                 pwm_a_pins: pwm_a {
 494                         mux {
 495                                 groups = "pwm_a";
 496                                 function = "pwm_a";
 497                         };
 498                 };
 499
 500                 pwm_b_pins: pwm_b {
 501                         mux {
 502                                 groups = "pwm_b";
 503                                 function = "pwm_b";
 504                         };
 505                 };
 506
 507                 pwm_c_pins: pwm_c {
 508                         mux {
 509                                 groups = "pwm_c";
 510                                 function = "pwm_c";
 511                         };
 512                 };
 513
 514                 pwm_d_pins: pwm_d {
 515                         mux {
 516                                 groups = "pwm_d";
 517                                 function = "pwm_d";
 518                         };
 519                 };
 520
 521                 pwm_e_pins: pwm_e {
 522                         mux {
 523                                 groups = "pwm_e";
 524                                 function = "pwm_e";
 525                         };
 526                 };
 527
 528                 pwm_f_clk_pins: pwm_f_clk {
 529                         mux {
 530                                 groups = "pwm_f_clk";
 531                                 function = "pwm_f";
 532                         };
 533                 };
 534
 535                 pwm_f_x_pins: pwm_f_x {
 536                         mux {
 537                                 groups = "pwm_f_x";
 538                                 function = "pwm_f";
 539                         };
 540                 };
 541
 542                 hdmi_hpd_pins: hdmi_hpd {
 543                         mux {
 544                                 groups = "hdmi_hpd";
 545                                 function = "hdmi_hpd";
 546                         };
 547                 };
 548
 549                 hdmi_i2c_pins: hdmi_i2c {
 550                         mux {
 551                                 groups = "hdmi_sda", "hdmi_scl";
 552                                 function = "hdmi_i2c";
 553                         };
 554                 };
 555
 556                 i2s_am_clk_pins: i2s_am_clk {
 557                         mux {
 558                                 groups = "i2s_am_clk";
 559                                 function = "i2s_out";
 560                         };
 561                 };
 562
 563                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 564                         mux {
 565                                 groups = "i2s_out_ao_clk";
 566                                 function = "i2s_out";
 567                         };
 568                 };
 569
 570                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 571                         mux {
 572                                 groups = "i2s_out_lr_clk";
 573                                 function = "i2s_out";
 574                         };
 575                 };
 576
 577                 i2s_out_ch01_pins: i2s_out_ch01 {
 578                         mux {
 579                                 groups = "i2s_out_ch01";
 580                                 function = "i2s_out";
 581                         };
 582                 };
 583                 i2sout_ch23_z_pins: i2sout_ch23_z {
 584                         mux {
 585                                 groups = "i2sout_ch23_z";
 586                                 function = "i2s_out";
 587                         };
 588                 };
 589
 590                 i2sout_ch45_z_pins: i2sout_ch45_z {
 591                         mux {
 592                                 groups = "i2sout_ch45_z";
 593                                 function = "i2s_out";
 594                         };
 595                 };
 596
 597                 i2sout_ch67_z_pins: i2sout_ch67_z {
 598                         mux {
 599                                 groups = "i2sout_ch67_z";
 600                                 function = "i2s_out";
 601                         };
 602                 };
 603
 604                 spdif_out_h_pins: spdif_out_ao_h {
 605                         mux {
 606                                 groups = "spdif_out_h";
 607                                 function = "spdif_out";
 608                         };
 609                 };
 610         };
 611
 612         eth-phy-mux@55c {
 613                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 reg = <0x0 0x55c 0x0 0x4>;
 617                 mux-mask = <0xffffffff>;
 618                 mdio-parent-bus = <&mdio0>;
 619
 620                 internal_mdio: mdio@e40908ff {
 621                         reg = <0xe40908ff>;
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624
 625                         internal_phy: ethernet-phy@8 {
 626                                 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
 627                                 reg = <8>;
 628                                 max-speed = <100>;
 629                         };
 630                 };
 631
 632                 external_mdio: mdio@2009087f {
 633                         reg = <0x2009087f>;
 634                         #address-cells = <1>;
 635                         #size-cells = <0>;
 636                 };
 637         };
 638 };
 639
 640 &saradc {
 641         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 642         clocks = <&xtal>,
 643                  <&clkc CLKID_SAR_ADC>,
 644                  <&clkc CLKID_SANA>,
 645                  <&clkc CLKID_SAR_ADC_CLK>,
 646                  <&clkc CLKID_SAR_ADC_SEL>;
 647         clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
 648 };
 649
 650 &sd_emmc_a {
 651         clocks = <&clkc CLKID_SD_EMMC_A>,
 652                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 653                  <&clkc CLKID_FCLK_DIV2>;
 654         clock-names = "core", "clkin0", "clkin1";
 655 };
 656
 657 &sd_emmc_b {
 658         clocks = <&clkc CLKID_SD_EMMC_B>,
 659                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 660                  <&clkc CLKID_FCLK_DIV2>;
 661        clock-names = "core", "clkin0", "clkin1";
 662 };
 663
 664 &sd_emmc_c {
 665         clocks = <&clkc CLKID_SD_EMMC_C>,
 666                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 667                  <&clkc CLKID_FCLK_DIV2>;
 668         clock-names = "core", "clkin0", "clkin1";
 669 };
 670
 671 &spicc {
 672         clocks = <&clkc CLKID_SPICC>;
 673         clock-names = "core";
 674         resets = <&reset RESET_PERIPHS_SPICC>;
 675         num-cs = <1>;
 676 };
 677
 678 &spifc {
 679         clocks = <&clkc CLKID_SPI>;
 680 };
 681
 682 &uart_A {
 683         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 684         clock-names = "xtal", "core", "baud";
 685 };
 686
 687 &uart_AO {
 688         clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
 689         clock-names = "xtal", "pclk", "baud";
 690 };
 691
 692 &uart_AO_B {
 693         clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
 694         clock-names = "xtal", "pclk", "baud";
 695 };
 696
 697 &uart_B {
 698         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 699         clock-names = "xtal", "core", "baud";
 700 };
 701
 702 &uart_C {
 703         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 704         clock-names = "xtal", "core", "baud";
 705 };
 706
 707 &vpu {
 708         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 709 };