arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Endless Computers, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  */
   6
   7 #include "meson-gx.dtsi"
   8 #include <dt-bindings/clock/gxbb-clkc.h>
   9 #include <dt-bindings/clock/gxbb-aoclkc.h>
  10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  12
  13 / {
  14         compatible = "amlogic,meson-gxl";
  15
  16         soc {
  17                 usb0: usb@c9000000 {
  18                         status = "disabled";
  19                         compatible = "amlogic,meson-gxl-dwc3";
  20                         #address-cells = <2>;
  21                         #size-cells = <2>;
  22                         ranges;
  23
  24                         clocks = <&clkc CLKID_USB>;
  25                         clock-names = "usb_general";
  26                         resets = <&reset RESET_USB_OTG>;
  27                         reset-names = "usb_otg";
  28
  29                         dwc3: dwc3@c9000000 {
  30                                 compatible = "snps,dwc3";
  31                                 reg = <0x0 0xc9000000 0x0 0x100000>;
  32                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  33                                 dr_mode = "host";
  34                                 maximum-speed = "high-speed";
  35                                 snps,dis_u2_susphy_quirk;
  36                                 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
  37                         };
  38                 };
  39         };
  40 };
  41
  42 &apb {
  43         usb2_phy0: phy@78000 {
  44                 compatible = "amlogic,meson-gxl-usb2-phy";
  45                 #phy-cells = <0>;
  46                 reg = <0x0 0x78000 0x0 0x20>;
  47                 clocks = <&clkc CLKID_USB>;
  48                 clock-names = "phy";
  49                 resets = <&reset RESET_USB_OTG>;
  50                 reset-names = "phy";
  51                 status = "okay";
  52         };
  53
  54         usb2_phy1: phy@78020 {
  55                 compatible = "amlogic,meson-gxl-usb2-phy";
  56                 #phy-cells = <0>;
  57                 reg = <0x0 0x78020 0x0 0x20>;
  58                 clocks = <&clkc CLKID_USB>;
  59                 clock-names = "phy";
  60                 resets = <&reset RESET_USB_OTG>;
  61                 reset-names = "phy";
  62                 status = "okay";
  63         };
  64
  65         usb3_phy: phy@78080 {
  66                 compatible = "amlogic,meson-gxl-usb3-phy";
  67                 #phy-cells = <0>;
  68                 reg = <0x0 0x78080 0x0 0x20>;
  69                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  70                 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
  71                 clock-names = "phy", "peripheral";
  72                 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
  73                 reset-names = "phy", "peripheral";
  74                 status = "okay";
  75         };
  76 };
  77
  78 &efuse {
  79         clocks = <&clkc CLKID_EFUSE>;
  80 };
  81
  82 &ethmac {
  83         clocks = <&clkc CLKID_ETH>,
  84                  <&clkc CLKID_FCLK_DIV2>,
  85                  <&clkc CLKID_MPLL2>;
  86         clock-names = "stmmaceth", "clkin0", "clkin1";
  87
  88         mdio0: mdio {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 compatible = "snps,dwmac-mdio";
  92         };
  93 };
  94
  95 &aobus {
  96         pinctrl_aobus: pinctrl@14 {
  97                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
  98                 #address-cells = <2>;
  99                 #size-cells = <2>;
 100                 ranges;
 101
 102                 gpio_ao: bank@14 {
 103                         reg = <0x0 0x00014 0x0 0x8>,
 104                               <0x0 0x0002c 0x0 0x4>,
 105                               <0x0 0x00024 0x0 0x8>;
 106                         reg-names = "mux", "pull", "gpio";
 107                         gpio-controller;
 108                         #gpio-cells = <2>;
 109                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
 110                 };
 111
 112                 uart_ao_a_pins: uart_ao_a {
 113                         mux {
 114                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 115                                 function = "uart_ao";
 116                                 bias-disable;
 117                         };
 118                 };
 119
 120                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 121                         mux {
 122                                 groups = "uart_cts_ao_a",
 123                                        "uart_rts_ao_a";
 124                                 function = "uart_ao";
 125                                 bias-disable;
 126                         };
 127                 };
 128
 129                 uart_ao_b_pins: uart_ao_b {
 130                         mux {
 131                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 132                                 function = "uart_ao_b";
 133                                 bias-disable;
 134                         };
 135                 };
 136
 137                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 138                         mux {
 139                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 140                                 function = "uart_ao_b";
 141                                 bias-disable;
 142                         };
 143                 };
 144
 145                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 146                         mux {
 147                                 groups = "uart_cts_ao_b",
 148                                        "uart_rts_ao_b";
 149                                 function = "uart_ao_b";
 150                                 bias-disable;
 151                         };
 152                 };
 153
 154                 remote_input_ao_pins: remote_input_ao {
 155                         mux {
 156                                 groups = "remote_input_ao";
 157                                 function = "remote_input_ao";
 158                                 bias-disable;
 159                         };
 160                 };
 161
 162                 i2c_ao_pins: i2c_ao {
 163                         mux {
 164                                 groups = "i2c_sck_ao",
 165                                        "i2c_sda_ao";
 166                                 function = "i2c_ao";
 167                                 bias-disable;
 168                         };
 169                 };
 170
 171                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 172                         mux {
 173                                 groups = "pwm_ao_a_3";
 174                                 function = "pwm_ao_a";
 175                                 bias-disable;
 176                         };
 177                 };
 178
 179                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 180                         mux {
 181                                 groups = "pwm_ao_a_8";
 182                                 function = "pwm_ao_a";
 183                                 bias-disable;
 184                         };
 185                 };
 186
 187                 pwm_ao_b_pins: pwm_ao_b {
 188                         mux {
 189                                 groups = "pwm_ao_b";
 190                                 function = "pwm_ao_b";
 191                                 bias-disable;
 192                         };
 193                 };
 194
 195                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 196                         mux {
 197                                 groups = "pwm_ao_b_6";
 198                                 function = "pwm_ao_b";
 199                                 bias-disable;
 200                         };
 201                 };
 202
 203                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 204                         mux {
 205                                 groups = "i2s_out_ch23_ao";
 206                                 function = "i2s_out_ao";
 207                                 bias-disable;
 208                         };
 209                 };
 210
 211                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 212                         mux {
 213                                 groups = "i2s_out_ch45_ao";
 214                                 function = "i2s_out_ao";
 215                                 bias-disable;
 216                         };
 217                 };
 218
 219                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 220                         mux {
 221                                 groups = "spdif_out_ao_6";
 222                                 function = "spdif_out_ao";
 223                                 bias-disable;
 224                         };
 225                 };
 226
 227                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 228                         mux {
 229                                 groups = "spdif_out_ao_9";
 230                                 function = "spdif_out_ao";
 231                                 bias-disable;
 232                         };
 233                 };
 234
 235                 ao_cec_pins: ao_cec {
 236                         mux {
 237                                 groups = "ao_cec";
 238                                 function = "cec_ao";
 239                                 bias-disable;
 240                         };
 241                 };
 242
 243                 ee_cec_pins: ee_cec {
 244                         mux {
 245                                 groups = "ee_cec";
 246                                 function = "cec_ao";
 247                                 bias-disable;
 248                         };
 249                 };
 250         };
 251 };
 252
 253 &cec_AO {
 254         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 255         clock-names = "core";
 256 };
 257
 258 &clkc_AO {
 259         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
 260         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 261         clock-names = "xtal", "mpeg-clk";
 262 };
 263
 264 &gpio_intc {
 265         compatible = "amlogic,meson-gpio-intc",
 266                      "amlogic,meson-gxl-gpio-intc";
 267         status = "okay";
 268 };
 269
 270 &hdmi_tx {
 271         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 272         resets = <&reset RESET_HDMITX_CAPB3>,
 273                  <&reset RESET_HDMI_SYSTEM_RESET>,
 274                  <&reset RESET_HDMI_TX>;
 275         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 276         clocks = <&clkc CLKID_HDMI_PCLK>,
 277                  <&clkc CLKID_CLK81>,
 278                  <&clkc CLKID_GCLK_VENCI_INT0>;
 279         clock-names = "isfr", "iahb", "venci";
 280 };
 281
 282 &sysctrl {
 283         clkc: clock-controller {
 284                 compatible = "amlogic,gxl-clkc";
 285                 #clock-cells = <1>;
 286                 clocks = <&xtal>;
 287                 clock-names = "xtal";
 288         };
 289 };
 290
 291 &hwrng {
 292         clocks = <&clkc CLKID_RNG0>;
 293         clock-names = "core";
 294 };
 295
 296 &i2c_A {
 297         clocks = <&clkc CLKID_I2C>;
 298 };
 299
 300 &i2c_AO {
 301         clocks = <&clkc CLKID_AO_I2C>;
 302 };
 303
 304 &i2c_B {
 305         clocks = <&clkc CLKID_I2C>;
 306 };
 307
 308 &i2c_C {
 309         clocks = <&clkc CLKID_I2C>;
 310 };
 311
 312 &periphs {
 313         pinctrl_periphs: pinctrl@4b0 {
 314                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 315                 #address-cells = <2>;
 316                 #size-cells = <2>;
 317                 ranges;
 318
 319                 gpio: bank@4b0 {
 320                         reg = <0x0 0x004b0 0x0 0x28>,
 321                               <0x0 0x004e8 0x0 0x14>,
 322                               <0x0 0x00520 0x0 0x14>,
 323                               <0x0 0x00430 0x0 0x40>;
 324                         reg-names = "mux", "pull", "pull-enable", "gpio";
 325                         gpio-controller;
 326                         #gpio-cells = <2>;
 327                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
 328                 };
 329
 330                 emmc_pins: emmc {
 331                         mux-0 {
 332                                 groups = "emmc_nand_d07",
 333                                        "emmc_cmd";
 334                                 function = "emmc";
 335                                 bias-pull-up;
 336                         };
 337
 338                         mux-1 {
 339                                 groups = "emmc_clk";
 340                                 function = "emmc";
 341                                 bias-disable;
 342                         };
 343                 };
 344
 345                 emmc_ds_pins: emmc-ds {
 346                         mux {
 347                                 groups = "emmc_ds";
 348                                 function = "emmc";
 349                                 bias-pull-down;
 350                         };
 351                 };
 352
 353                 emmc_clk_gate_pins: emmc_clk_gate {
 354                         mux {
 355                                 groups = "BOOT_8";
 356                                 function = "gpio_periphs";
 357                                 bias-pull-down;
 358                         };
 359                 };
 360
 361                 nor_pins: nor {
 362                         mux {
 363                                 groups = "nor_d",
 364                                        "nor_q",
 365                                        "nor_c",
 366                                        "nor_cs";
 367                                 function = "nor";
 368                                 bias-disable;
 369                         };
 370                 };
 371
 372                 spi_pins: spi-pins {
 373                         mux {
 374                                 groups = "spi_miso",
 375                                         "spi_mosi",
 376                                         "spi_sclk";
 377                                 function = "spi";
 378                                 bias-disable;
 379                         };
 380                 };
 381
 382                 spi_ss0_pins: spi-ss0 {
 383                         mux {
 384                                 groups = "spi_ss0";
 385                                 function = "spi";
 386                                 bias-disable;
 387                         };
 388                 };
 389
 390                 sdcard_pins: sdcard {
 391                         mux-0 {
 392                                 groups = "sdcard_d0",
 393                                        "sdcard_d1",
 394                                        "sdcard_d2",
 395                                        "sdcard_d3",
 396                                        "sdcard_cmd";
 397                                 function = "sdcard";
 398                                 bias-pull-up;
 399                         };
 400
 401                         mux-1 {
 402                                 groups = "sdcard_clk";
 403                                 function = "sdcard";
 404                                 bias-disable;
 405                         };
 406                 };
 407
 408                 sdcard_clk_gate_pins: sdcard_clk_gate {
 409                         mux {
 410                                 groups = "CARD_2";
 411                                 function = "gpio_periphs";
 412                                 bias-pull-down;
 413                         };
 414                 };
 415
 416                 sdio_pins: sdio {
 417                         mux-0 {
 418                                 groups = "sdio_d0",
 419                                        "sdio_d1",
 420                                        "sdio_d2",
 421                                        "sdio_d3",
 422                                        "sdio_cmd";
 423                                 function = "sdio";
 424                                 bias-pull-up;
 425                         };
 426
 427                         mux-1 {
 428                                 groups = "sdio_clk";
 429                                 function = "sdio";
 430                                 bias-disable;
 431                         };
 432                 };
 433
 434                 sdio_clk_gate_pins: sdio_clk_gate {
 435                         mux {
 436                                 groups = "GPIOX_4";
 437                                 function = "gpio_periphs";
 438                                 bias-pull-down;
 439                         };
 440                 };
 441
 442                 sdio_irq_pins: sdio_irq {
 443                         mux {
 444                                 groups = "sdio_irq";
 445                                 function = "sdio";
 446                                 bias-disable;
 447                         };
 448                 };
 449
 450                 uart_a_pins: uart_a {
 451                         mux {
 452                                 groups = "uart_tx_a",
 453                                        "uart_rx_a";
 454                                 function = "uart_a";
 455                                 bias-disable;
 456                         };
 457                 };
 458
 459                 uart_a_cts_rts_pins: uart_a_cts_rts {
 460                         mux {
 461                                 groups = "uart_cts_a",
 462                                        "uart_rts_a";
 463                                 function = "uart_a";
 464                                 bias-disable;
 465                         };
 466                 };
 467
 468                 uart_b_pins: uart_b {
 469                         mux {
 470                                 groups = "uart_tx_b",
 471                                        "uart_rx_b";
 472                                 function = "uart_b";
 473                                 bias-disable;
 474                         };
 475                 };
 476
 477                 uart_b_cts_rts_pins: uart_b_cts_rts {
 478                         mux {
 479                                 groups = "uart_cts_b",
 480                                        "uart_rts_b";
 481                                 function = "uart_b";
 482                                 bias-disable;
 483                         };
 484                 };
 485
 486                 uart_c_pins: uart_c {
 487                         mux {
 488                                 groups = "uart_tx_c",
 489                                        "uart_rx_c";
 490                                 function = "uart_c";
 491                                 bias-disable;
 492                         };
 493                 };
 494
 495                 uart_c_cts_rts_pins: uart_c_cts_rts {
 496                         mux {
 497                                 groups = "uart_cts_c",
 498                                        "uart_rts_c";
 499                                 function = "uart_c";
 500                                 bias-disable;
 501                         };
 502                 };
 503
 504                 i2c_a_pins: i2c_a {
 505                         mux {
 506                                 groups = "i2c_sck_a",
 507                                      "i2c_sda_a";
 508                                 function = "i2c_a";
 509                                 bias-disable;
 510                         };
 511                 };
 512
 513                 i2c_b_pins: i2c_b {
 514                         mux {
 515                                 groups = "i2c_sck_b",
 516                                       "i2c_sda_b";
 517                                 function = "i2c_b";
 518                                 bias-disable;
 519                         };
 520                 };
 521
 522                 i2c_c_pins: i2c_c {
 523                         mux {
 524                                 groups = "i2c_sck_c",
 525                                       "i2c_sda_c";
 526                                 function = "i2c_c";
 527                                 bias-disable;
 528                         };
 529                 };
 530
 531                 eth_pins: eth_c {
 532                         mux {
 533                                 groups = "eth_mdio",
 534                                        "eth_mdc",
 535                                        "eth_clk_rx_clk",
 536                                        "eth_rx_dv",
 537                                        "eth_rxd0",
 538                                        "eth_rxd1",
 539                                        "eth_rxd2",
 540                                        "eth_rxd3",
 541                                        "eth_rgmii_tx_clk",
 542                                        "eth_tx_en",
 543                                        "eth_txd0",
 544                                        "eth_txd1",
 545                                        "eth_txd2",
 546                                        "eth_txd3";
 547                                 function = "eth";
 548                                 bias-disable;
 549                         };
 550                 };
 551
 552                 eth_link_led_pins: eth_link_led {
 553                         mux {
 554                                 groups = "eth_link_led";
 555                                 function = "eth_led";
 556                                 bias-disable;
 557                         };
 558                 };
 559
 560                 eth_act_led_pins: eth_act_led {
 561                         mux {
 562                                 groups = "eth_act_led";
 563                                 function = "eth_led";
 564                         };
 565                 };
 566
 567                 pwm_a_pins: pwm_a {
 568                         mux {
 569                                 groups = "pwm_a";
 570                                 function = "pwm_a";
 571                                 bias-disable;
 572                         };
 573                 };
 574
 575                 pwm_b_pins: pwm_b {
 576                         mux {
 577                                 groups = "pwm_b";
 578                                 function = "pwm_b";
 579                                 bias-disable;
 580                         };
 581                 };
 582
 583                 pwm_c_pins: pwm_c {
 584                         mux {
 585                                 groups = "pwm_c";
 586                                 function = "pwm_c";
 587                                 bias-disable;
 588                         };
 589                 };
 590
 591                 pwm_d_pins: pwm_d {
 592                         mux {
 593                                 groups = "pwm_d";
 594                                 function = "pwm_d";
 595                                 bias-disable;
 596                         };
 597                 };
 598
 599                 pwm_e_pins: pwm_e {
 600                         mux {
 601                                 groups = "pwm_e";
 602                                 function = "pwm_e";
 603                                 bias-disable;
 604                         };
 605                 };
 606
 607                 pwm_f_clk_pins: pwm_f_clk {
 608                         mux {
 609                                 groups = "pwm_f_clk";
 610                                 function = "pwm_f";
 611                                 bias-disable;
 612                         };
 613                 };
 614
 615                 pwm_f_x_pins: pwm_f_x {
 616                         mux {
 617                                 groups = "pwm_f_x";
 618                                 function = "pwm_f";
 619                                 bias-disable;
 620                         };
 621                 };
 622
 623                 hdmi_hpd_pins: hdmi_hpd {
 624                         mux {
 625                                 groups = "hdmi_hpd";
 626                                 function = "hdmi_hpd";
 627                                 bias-disable;
 628                         };
 629                 };
 630
 631                 hdmi_i2c_pins: hdmi_i2c {
 632                         mux {
 633                                 groups = "hdmi_sda", "hdmi_scl";
 634                                 function = "hdmi_i2c";
 635                                 bias-disable;
 636                         };
 637                 };
 638
 639                 i2s_am_clk_pins: i2s_am_clk {
 640                         mux {
 641                                 groups = "i2s_am_clk";
 642                                 function = "i2s_out";
 643                                 bias-disable;
 644                         };
 645                 };
 646
 647                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 648                         mux {
 649                                 groups = "i2s_out_ao_clk";
 650                                 function = "i2s_out";
 651                                 bias-disable;
 652                         };
 653                 };
 654
 655                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 656                         mux {
 657                                 groups = "i2s_out_lr_clk";
 658                                 function = "i2s_out";
 659                                 bias-disable;
 660                         };
 661                 };
 662
 663                 i2s_out_ch01_pins: i2s_out_ch01 {
 664                         mux {
 665                                 groups = "i2s_out_ch01";
 666                                 function = "i2s_out";
 667                                 bias-disable;
 668                         };
 669                 };
 670                 i2sout_ch23_z_pins: i2sout_ch23_z {
 671                         mux {
 672                                 groups = "i2sout_ch23_z";
 673                                 function = "i2s_out";
 674                                 bias-disable;
 675                         };
 676                 };
 677
 678                 i2sout_ch45_z_pins: i2sout_ch45_z {
 679                         mux {
 680                                 groups = "i2sout_ch45_z";
 681                                 function = "i2s_out";
 682                                 bias-disable;
 683                         };
 684                 };
 685
 686                 i2sout_ch67_z_pins: i2sout_ch67_z {
 687                         mux {
 688                                 groups = "i2sout_ch67_z";
 689                                 function = "i2s_out";
 690                                 bias-disable;
 691                         };
 692                 };
 693
 694                 spdif_out_h_pins: spdif_out_ao_h {
 695                         mux {
 696                                 groups = "spdif_out_h";
 697                                 function = "spdif_out";
 698                                 bias-disable;
 699                         };
 700                 };
 701         };
 702
 703         eth-phy-mux@55c {
 704                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 705                 #address-cells = <1>;
 706                 #size-cells = <0>;
 707                 reg = <0x0 0x55c 0x0 0x4>;
 708                 mux-mask = <0xffffffff>;
 709                 mdio-parent-bus = <&mdio0>;
 710
 711                 internal_mdio: mdio@e40908ff {
 712                         reg = <0xe40908ff>;
 713                         #address-cells = <1>;
 714                         #size-cells = <0>;
 715
 716                         internal_phy: ethernet-phy@8 {
 717                                 compatible = "ethernet-phy-id0181.4400";
 718                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 719                                 reg = <8>;
 720                                 max-speed = <100>;
 721                         };
 722                 };
 723
 724                 external_mdio: mdio@2009087f {
 725                         reg = <0x2009087f>;
 726                         #address-cells = <1>;
 727                         #size-cells = <0>;
 728                 };
 729         };
 730 };
 731
 732 &pwrc_vpu {
 733         resets = <&reset RESET_VIU>,
 734                  <&reset RESET_VENC>,
 735                  <&reset RESET_VCBUS>,
 736                  <&reset RESET_BT656>,
 737                  <&reset RESET_DVIN_RESET>,
 738                  <&reset RESET_RDMA>,
 739                  <&reset RESET_VENCI>,
 740                  <&reset RESET_VENCP>,
 741                  <&reset RESET_VDAC>,
 742                  <&reset RESET_VDI6>,
 743                  <&reset RESET_VENCL>,
 744                  <&reset RESET_VID_LOCK>;
 745         clocks = <&clkc CLKID_VPU>,
 746                  <&clkc CLKID_VAPB>;
 747         clock-names = "vpu", "vapb";
 748         /*
 749          * VPU clocking is provided by two identical clock paths
 750          * VPU_0 and VPU_1 muxed to a single clock by a glitch
 751          * free mux to safely change frequency while running.
 752          * Same for VAPB but with a final gate after the glitch free mux.
 753          */
 754         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
 755                           <&clkc CLKID_VPU_0>,
 756                           <&clkc CLKID_VPU>, /* Glitch free mux */
 757                           <&clkc CLKID_VAPB_0_SEL>,
 758                           <&clkc CLKID_VAPB_0>,
 759                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
 760         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 761                                  <0>, /* Do Nothing */
 762                                  <&clkc CLKID_VPU_0>,
 763                                  <&clkc CLKID_FCLK_DIV4>,
 764                                  <0>, /* Do Nothing */
 765                                  <&clkc CLKID_VAPB_0>;
 766         assigned-clock-rates = <0>, /* Do Nothing */
 767                                <666666666>,
 768                                <0>, /* Do Nothing */
 769                                <0>, /* Do Nothing */
 770                                <250000000>,
 771                                <0>; /* Do Nothing */
 772 };
 773
 774 &saradc {
 775         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 776         clocks = <&xtal>,
 777                  <&clkc CLKID_SAR_ADC>,
 778                  <&clkc CLKID_SAR_ADC_CLK>,
 779                  <&clkc CLKID_SAR_ADC_SEL>;
 780         clock-names = "clkin", "core", "adc_clk", "adc_sel";
 781 };
 782
 783 &sd_emmc_a {
 784         clocks = <&clkc CLKID_SD_EMMC_A>,
 785                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 786                  <&clkc CLKID_FCLK_DIV2>;
 787         clock-names = "core", "clkin0", "clkin1";
 788         resets = <&reset RESET_SD_EMMC_A>;
 789 };
 790
 791 &sd_emmc_b {
 792         clocks = <&clkc CLKID_SD_EMMC_B>,
 793                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 794                  <&clkc CLKID_FCLK_DIV2>;
 795         clock-names = "core", "clkin0", "clkin1";
 796         resets = <&reset RESET_SD_EMMC_B>;
 797 };
 798
 799 &sd_emmc_c {
 800         clocks = <&clkc CLKID_SD_EMMC_C>,
 801                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 802                  <&clkc CLKID_FCLK_DIV2>;
 803         clock-names = "core", "clkin0", "clkin1";
 804         resets = <&reset RESET_SD_EMMC_C>;
 805 };
 806
 807 &simplefb_hdmi {
 808         clocks = <&clkc CLKID_HDMI_PCLK>,
 809                  <&clkc CLKID_CLK81>,
 810                  <&clkc CLKID_GCLK_VENCI_INT0>;
 811 };
 812
 813 &spicc {
 814         clocks = <&clkc CLKID_SPICC>;
 815         clock-names = "core";
 816         resets = <&reset RESET_PERIPHS_SPICC>;
 817         num-cs = <1>;
 818 };
 819
 820 &spifc {
 821         clocks = <&clkc CLKID_SPI>;
 822 };
 823
 824 &uart_A {
 825         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 826         clock-names = "xtal", "pclk", "baud";
 827 };
 828
 829 &uart_AO {
 830         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
 831         clock-names = "xtal", "pclk", "baud";
 832 };
 833
 834 &uart_AO_B {
 835         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
 836         clock-names = "xtal", "pclk", "baud";
 837 };
 838
 839 &uart_B {
 840         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 841         clock-names = "xtal", "pclk", "baud";
 842 };
 843
 844 &uart_C {
 845         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 846         clock-names = "xtal", "pclk", "baud";
 847 };
 848
 849 &vpu {
 850         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 851         power-domains = <&pwrc_vpu>;
 852 };
 853
 854 &vdec {
 855         compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
 856         clocks = <&clkc CLKID_DOS_PARSER>,
 857                  <&clkc CLKID_DOS>,
 858                  <&clkc CLKID_VDEC_1>,
 859                  <&clkc CLKID_VDEC_HEVC>;
 860         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
 861         resets = <&reset RESET_PARSER>;
 862         reset-names = "esparser";
 863 };