2 * DTS file for AMD Seattle SoC
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
8 compatible = "amd,seattle";
9 interrupt-parent = <&gic0>;
13 gic0: interrupt-controller@e1101000 {
14 compatible = "arm,gic-400", "arm,cortex-a15-gic";
16 #interrupt-cells = <3>;
19 reg = <0x0 0xe1110000 0 0x1000>,
20 <0x0 0xe112f000 0 0x2000>,
21 <0x0 0xe1140000 0 0x10000>,
22 <0x0 0xe1160000 0 0x10000>;
23 interrupts = <1 9 0xf04>;
24 ranges = <0 0 0 0xe1100000 0 0x100000>;
26 compatible = "arm,gic-v2m-frame";
28 reg = <0x0 0x00080000 0 0x1000>;
33 compatible = "arm,armv8-timer";
34 interrupts = <1 13 0xff04>,
41 compatible = "arm,armv8-pmuv3";
53 compatible = "simple-bus";
58 /* DDR range is 40-bit addressing */
59 dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
61 /include/ "amd-seattle-clks.dtsi"
63 sata0: sata@e0300000 {
64 compatible = "snps,dwc-ahci";
65 reg = <0 0xe0300000 0 0x800>;
66 interrupts = <0 355 4>;
67 clocks = <&sataclk_333mhz>;
73 compatible = "snps,designware-i2c";
74 reg = <0 0xe1000000 0 0x1000>;
75 interrupts = <0 357 4>;
76 clocks = <&uartspiclk_100mhz>;
79 serial0: serial@e1010000 {
80 compatible = "arm,pl011", "arm,primecell";
81 reg = <0 0xe1010000 0 0x1000>;
82 interrupts = <0 328 4>;
83 clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
84 clock-names = "uartclk", "apb_pclk";
89 compatible = "arm,pl022", "arm,primecell";
91 reg = <0 0xe1020000 0 0x1000>;
93 interrupts = <0 330 4>;
94 clocks = <&uartspiclk_100mhz>;
95 clock-names = "apb_pclk";
100 compatible = "arm,pl022", "arm,primecell";
102 reg = <0 0xe1030000 0 0x1000>;
104 interrupts = <0 329 4>;
105 clocks = <&uartspiclk_100mhz>;
106 clock-names = "apb_pclk";
108 #address-cells = <1>;
112 gpio0: gpio@e1040000 {
114 compatible = "arm,pl061", "arm,primecell";
116 reg = <0 0xe1040000 0 0x1000>;
118 interrupts = <0 359 4>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 clocks = <&uartspiclk_100mhz>;
122 clock-names = "apb_pclk";
125 gpio1: gpio@e1050000 {
127 compatible = "arm,pl061", "arm,primecell";
129 reg = <0 0xe1050000 0 0x1000>;
131 interrupts = <0 358 4>;
132 clocks = <&uartspiclk_100mhz>;
133 clock-names = "apb_pclk";
138 compatible = "amd,ccp-seattle-v1a";
139 reg = <0 0xe0100000 0 0x10000>;
140 interrupts = <0 3 4>;
144 pcie0: pcie@f0000000 {
145 compatible = "pci-host-ecam-generic";
146 #address-cells = <3>;
148 #interrupt-cells = <1>;
150 bus-range = <0 0x7f>;
151 msi-parent = <&v2m0>;
152 reg = <0 0xf0000000 0 0x10000000>;
154 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
156 <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
157 <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
158 <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
159 <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
162 dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
164 /* I/O Memory (size=64K) */
165 <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
166 /* 32-bit MMIO (size=2G) */
167 <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
168 /* 64-bit MMIO (size= 124G) */
169 <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;