1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
45 compatible = "arm,cortex-a57";
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
61 compatible = "arm,cortex-a57";
63 enable-method = "psci";
65 i-cache-size = <0xC000>;
66 i-cache-line-size = <64>;
68 d-cache-size = <0x8000>;
69 d-cache-line-size = <64>;
76 compatible = "arm,cortex-a57";
78 enable-method = "psci";
80 i-cache-size = <0xC000>;
81 i-cache-line-size = <64>;
83 d-cache-size = <0x8000>;
84 d-cache-line-size = <64>;
91 compatible = "arm,cortex-a57";
93 enable-method = "psci";
95 i-cache-size = <0xC000>;
96 i-cache-line-size = <64>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <256>;
106 compatible = "arm,cortex-a57";
108 enable-method = "psci";
110 i-cache-size = <0xC000>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>;
113 d-cache-size = <0x8000>;
114 d-cache-line-size = <64>;
115 d-cache-sets = <256>;
121 compatible = "arm,cortex-a57";
123 enable-method = "psci";
125 i-cache-size = <0xC000>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <256>;
128 d-cache-size = <0x8000>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <256>;
136 compatible = "arm,cortex-a57";
138 enable-method = "psci";
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <0x8000>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <256>;
151 compatible = "arm,cortex-a57";
153 enable-method = "psci";
155 i-cache-size = <0xC000>;
156 i-cache-line-size = <64>;
157 i-cache-sets = <256>;
158 d-cache-size = <0x8000>;
159 d-cache-line-size = <64>;
160 d-cache-sets = <256>;
166 cache-size = <0x100000>;
167 cache-line-size = <64>;
170 next-level-cache = <&L3>;
174 cache-size = <0x100000>;
175 cache-line-size = <64>;
178 next-level-cache = <&L3>;
182 cache-size = <0x100000>;
183 cache-line-size = <64>;
186 next-level-cache = <&L3>;
190 cache-size = <0x100000>;
191 cache-line-size = <64>;
194 next-level-cache = <&L3>;
199 cache-size = <0x800000>;
200 cache-line-size = <64>;
206 compatible = "arm,cortex-a57-pmu";
207 interrupts = <0x0 0x7 0x4>,
215 interrupt-affinity = <&CPU0>,