arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2022, Intel Corporation
   4  */
   5
   6 #include "socfpga_stratix10.dtsi"
   7
   8 / {
   9         model = "SOCFPGA Stratix 10 SWVP";
  10         compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15
  16                 timer0 = &timer0;
  17                 timer1 = &timer1;
  18                 timer2 = &timer2;
  19                 timer3 = &timer3;
  20
  21                 ethernet0 = &gmac0;
  22                 ethernet1 = &gmac1;
  23                 ethernet2 = &gmac2;
  24         };
  25
  26         chosen {
  27                 stdout-path = "serial1:115200n8";
  28                 linux,initrd-start = <0x10000000>;
  29                 linux,initrd-end = <0x125c8324>;
  30         };
  31
  32         memory@80000000 {
  33                 device_type = "memory";
  34                 reg = <0x0 0x0 0x0 0x80000000>;
  35         };
  36 };
  37
  38 &cpu0 {
  39         enable-method = "spin-table";
  40         cpu-release-addr = <0x0 0x0000fff8>;
  41 };
  42
  43 &cpu1 {
  44         enable-method = "spin-table";
  45         cpu-release-addr = <0x0 0x0000fff8>;
  46 };
  47
  48 &cpu2 {
  49         enable-method = "spin-table";
  50         cpu-release-addr = <0x0 0x0000fff8>;
  51 };
  52
  53 &cpu3 {
  54         enable-method = "spin-table";
  55         cpu-release-addr = <0x0 0x0000fff8>;
  56 };
  57
  58 &osc1 {
  59         clock-frequency = <25000000>;
  60 };
  61
  62 &gmac0 {
  63         status = "okay";
  64         phy-mode = "rgmii";
  65         phy-addr = <0xffffffff>;
  66         snps,max-mtu = <0x0>;
  67 };
  68
  69 &gmac1 {
  70         status = "okay";
  71         phy-mode = "rgmii";
  72         phy-addr = <0xffffffff>;
  73 };
  74
  75 &gmac2 {
  76         status = "okay";
  77         phy-mode = "rgmii";
  78         phy-addr = <0xffffffff>;
  79 };
  80
  81 &mmc {
  82         status = "okay";
  83         altr,dw-mshc-ciu-div = <0x3>;
  84         altr,dw-mshc-sdr-timing = <0x0 0x3>;
  85         cap-sd-highspeed;
  86         cap-mmc-highspeed;
  87         broken-cd;
  88         bus-width = <4>;
  89 };
  90
  91 &uart0 {
  92         status = "okay";
  93 };
  94
  95 &uart1 {
  96         status = "okay";
  97 };
  98
  99 &usb0 {
 100         clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
 101         status = "okay";
 102 };
 103
 104 &usb1 {
 105         clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
 106         status = "okay";
 107 };
 108
 109 &rst {
 110         altr,modrst-offset = <0x20>;
 111 };
 112
 113 &sysmgr {
 114         reg = <0xffd12000 0x1000>;
 115         interrupts = <0x0 0x10 0x4>;
 116         cpu1-start-addr = <0xffd06230>;
 117 };