2 * Copyright Altera Corporation (C) 2015. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
32 compatible = "arm,cortex-a53", "arm,armv8";
34 enable-method = "psci";
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
46 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
61 compatible = "arm,armv8-pmuv3";
62 interrupts = <0 170 4>,
66 interrupt-affinity = <&cpu0>,
70 interrupt-parent = <&intc>;
74 compatible = "arm,psci-0.2";
79 compatible = "arm,gic-400", "arm,cortex-a15-gic";
80 #interrupt-cells = <3>;
82 reg = <0x0 0xfffc1000 0x0 0x1000>,
83 <0x0 0xfffc2000 0x0 0x2000>,
84 <0x0 0xfffc4000 0x0 0x2000>,
85 <0x0 0xfffc6000 0x0 0x2000>;
91 compatible = "simple-bus";
93 interrupt-parent = <&intc>;
94 ranges = <0 0 0 0xffffffff>;
96 clkmgr: clock-controller@ffd10000 {
97 compatible = "intel,stratix10-clkmgr";
98 reg = <0xffd10000 0x1000>;
103 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
105 compatible = "fixed-clock";
108 cb_intosc_ls_clk: cb-intosc-ls-clk {
110 compatible = "fixed-clock";
113 f2s_free_clk: f2s-free-clk {
115 compatible = "fixed-clock";
120 compatible = "fixed-clock";
125 compatible = "fixed-clock";
126 clock-frequency = <200000000>;
130 gmac0: ethernet@ff800000 {
131 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
132 reg = <0xff800000 0x2000>;
133 interrupts = <0 90 4>;
134 interrupt-names = "macirq";
135 mac-address = [00 00 00 00 00 00];
136 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
137 reset-names = "stmmaceth", "stmmaceth-ocp";
138 clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
139 clock-names = "stmmaceth";
140 tx-fifo-depth = <16384>;
141 rx-fifo-depth = <16384>;
142 snps,multicast-filter-bins = <256>;
143 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
147 gmac1: ethernet@ff802000 {
148 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
149 reg = <0xff802000 0x2000>;
150 interrupts = <0 91 4>;
151 interrupt-names = "macirq";
152 mac-address = [00 00 00 00 00 00];
153 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
154 reset-names = "stmmaceth", "stmmaceth-ocp";
155 clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
156 clock-names = "stmmaceth";
157 tx-fifo-depth = <16384>;
158 rx-fifo-depth = <16384>;
159 snps,multicast-filter-bins = <256>;
160 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
164 gmac2: ethernet@ff804000 {
165 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
166 reg = <0xff804000 0x2000>;
167 interrupts = <0 92 4>;
168 interrupt-names = "macirq";
169 mac-address = [00 00 00 00 00 00];
170 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
171 reset-names = "stmmaceth", "stmmaceth-ocp";
172 clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
173 clock-names = "stmmaceth";
174 tx-fifo-depth = <16384>;
175 rx-fifo-depth = <16384>;
176 snps,multicast-filter-bins = <256>;
177 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
181 gpio0: gpio@ffc03200 {
182 #address-cells = <1>;
184 compatible = "snps,dw-apb-gpio";
185 reg = <0xffc03200 0x100>;
186 resets = <&rst GPIO0_RESET>;
189 porta: gpio-controller@0 {
190 compatible = "snps,dw-apb-gpio-port";
193 snps,nr-gpios = <24>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 interrupts = <0 110 4>;
201 gpio1: gpio@ffc03300 {
202 #address-cells = <1>;
204 compatible = "snps,dw-apb-gpio";
205 reg = <0xffc03300 0x100>;
206 resets = <&rst GPIO1_RESET>;
209 portb: gpio-controller@0 {
210 compatible = "snps,dw-apb-gpio-port";
213 snps,nr-gpios = <24>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 interrupts = <0 111 4>;
222 #address-cells = <1>;
224 compatible = "snps,designware-i2c";
225 reg = <0xffc02800 0x100>;
226 interrupts = <0 103 4>;
227 resets = <&rst I2C0_RESET>;
228 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
233 #address-cells = <1>;
235 compatible = "snps,designware-i2c";
236 reg = <0xffc02900 0x100>;
237 interrupts = <0 104 4>;
238 resets = <&rst I2C1_RESET>;
239 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
244 #address-cells = <1>;
246 compatible = "snps,designware-i2c";
247 reg = <0xffc02a00 0x100>;
248 interrupts = <0 105 4>;
249 resets = <&rst I2C2_RESET>;
250 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
255 #address-cells = <1>;
257 compatible = "snps,designware-i2c";
258 reg = <0xffc02b00 0x100>;
259 interrupts = <0 106 4>;
260 resets = <&rst I2C3_RESET>;
261 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
266 #address-cells = <1>;
268 compatible = "snps,designware-i2c";
269 reg = <0xffc02c00 0x100>;
270 interrupts = <0 107 4>;
271 resets = <&rst I2C4_RESET>;
272 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
276 mmc: dwmmc0@ff808000 {
277 #address-cells = <1>;
279 compatible = "altr,socfpga-dw-mshc";
280 reg = <0xff808000 0x1000>;
281 interrupts = <0 96 4>;
282 fifo-depth = <0x400>;
283 resets = <&rst SDMMC_RESET>;
284 reset-names = "reset";
285 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
286 <&clkmgr STRATIX10_SDMMC_CLK>;
287 clock-names = "biu", "ciu";
291 ocram: sram@ffe00000 {
292 compatible = "mmio-sram";
293 reg = <0xffe00000 0x100000>;
296 pdma: pdma@ffda0000 {
297 compatible = "arm,pl330", "arm,primecell";
298 reg = <0xffda0000 0x1000>;
299 interrupts = <0 81 4>,
310 #dma-requests = <32>;
311 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
312 clock-names = "apb_pclk";
315 rst: rstmgr@ffd11000 {
317 compatible = "altr,rst-mgr";
318 reg = <0xffd11000 0x1000>;
319 altr,modrst-offset = <0x20>;
323 compatible = "snps,dw-apb-ssi";
324 #address-cells = <1>;
326 reg = <0xffda4000 0x1000>;
327 interrupts = <0 99 4>;
328 resets = <&rst SPIM0_RESET>;
331 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
336 compatible = "snps,dw-apb-ssi";
337 #address-cells = <1>;
339 reg = <0xffda5000 0x1000>;
340 interrupts = <0 100 4>;
341 resets = <&rst SPIM1_RESET>;
344 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
348 sysmgr: sysmgr@ffd12000 {
349 compatible = "altr,sys-mgr", "syscon";
350 reg = <0xffd12000 0x228>;
355 compatible = "arm,armv8-timer";
356 interrupts = <1 13 0xf08>,
362 timer0: timer0@ffc03000 {
363 compatible = "snps,dw-apb-timer";
364 interrupts = <0 113 4>;
365 reg = <0xffc03000 0x100>;
366 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
367 clock-names = "timer";
370 timer1: timer1@ffc03100 {
371 compatible = "snps,dw-apb-timer";
372 interrupts = <0 114 4>;
373 reg = <0xffc03100 0x100>;
374 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
375 clock-names = "timer";
378 timer2: timer2@ffd00000 {
379 compatible = "snps,dw-apb-timer";
380 interrupts = <0 115 4>;
381 reg = <0xffd00000 0x100>;
382 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
383 clock-names = "timer";
386 timer3: timer3@ffd00100 {
387 compatible = "snps,dw-apb-timer";
388 interrupts = <0 116 4>;
389 reg = <0xffd00100 0x100>;
390 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
391 clock-names = "timer";
394 uart0: serial0@ffc02000 {
395 compatible = "snps,dw-apb-uart";
396 reg = <0xffc02000 0x100>;
397 interrupts = <0 108 4>;
400 resets = <&rst UART0_RESET>;
401 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
405 uart1: serial1@ffc02100 {
406 compatible = "snps,dw-apb-uart";
407 reg = <0xffc02100 0x100>;
408 interrupts = <0 109 4>;
411 resets = <&rst UART1_RESET>;
412 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
418 compatible = "usb-nop-xceiv";
423 compatible = "snps,dwc2";
424 reg = <0xffb00000 0x40000>;
425 interrupts = <0 93 4>;
427 phy-names = "usb2-phy";
428 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
429 reset-names = "dwc2", "dwc2-ecc";
430 clocks = <&clkmgr STRATIX10_USB_CLK>;
435 compatible = "snps,dwc2";
436 reg = <0xffb40000 0x40000>;
437 interrupts = <0 94 4>;
439 phy-names = "usb2-phy";
440 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
441 reset-names = "dwc2", "dwc2-ecc";
442 clocks = <&clkmgr STRATIX10_USB_CLK>;
446 watchdog0: watchdog@ffd00200 {
447 compatible = "snps,dw-wdt";
448 reg = <0xffd00200 0x100>;
449 interrupts = <0 117 4>;
450 resets = <&rst WATCHDOG0_RESET>;
451 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
455 watchdog1: watchdog@ffd00300 {
456 compatible = "snps,dw-wdt";
457 reg = <0xffd00300 0x100>;
458 interrupts = <0 118 4>;
459 resets = <&rst WATCHDOG1_RESET>;
460 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
464 watchdog2: watchdog@ffd00400 {
465 compatible = "snps,dw-wdt";
466 reg = <0xffd00400 0x100>;
467 interrupts = <0 125 4>;
468 resets = <&rst WATCHDOG2_RESET>;
469 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
473 watchdog3: watchdog@ffd00500 {
474 compatible = "snps,dw-wdt";
475 reg = <0xffd00500 0x100>;
476 interrupts = <0 126 4>;
477 resets = <&rst WATCHDOG3_RESET>;
478 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
483 compatible = "altr,socfpga-s10-ecc-manager";
484 interrupts = <0 15 4>, <0 95 4>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
489 compatible = "altr,sdram-edac-s10";
490 interrupts = <16 4>, <48 4>;
495 compatible = "cdns,qspi-nor";
496 #address-cells = <1>;
498 reg = <0xff8d2000 0x100>,
499 <0xff900000 0x100000>;
500 interrupts = <0 3 4>;
501 cdns,fifo-depth = <128>;
502 cdns,fifo-width = <4>;
503 cdns,trigger-address = <0x00000000>;
504 clocks = <&qspi_clk>;