1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright Altera Corporation (C) 2015. All rights reserved.
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
21 service_reserved: svcbuffer@0 {
22 compatible = "shared-dma-pool";
23 reg = <0x0 0x0 0x0 0x1000000>;
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
63 compatible = "arm,armv8-pmuv3";
64 interrupts = <0 170 4>,
68 interrupt-affinity = <&cpu0>,
72 interrupt-parent = <&intc>;
76 compatible = "arm,psci-0.2";
80 intc: interrupt-controller@fffc1000 {
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0xfffc1000 0x0 0x1000>,
85 <0x0 0xfffc2000 0x0 0x2000>,
86 <0x0 0xfffc4000 0x0 0x2000>,
87 <0x0 0xfffc6000 0x0 0x2000>;
93 compatible = "simple-bus";
95 interrupt-parent = <&intc>;
96 ranges = <0 0 0 0xffffffff>;
99 #address-cells = <0x1>;
102 compatible = "fpga-region";
103 fpga-mgr = <&fpga_mgr>;
106 clkmgr: clock-controller@ffd10000 {
107 compatible = "intel,stratix10-clkmgr";
108 reg = <0xffd10000 0x1000>;
113 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
115 compatible = "fixed-clock";
118 cb_intosc_ls_clk: cb-intosc-ls-clk {
120 compatible = "fixed-clock";
123 f2s_free_clk: f2s-free-clk {
125 compatible = "fixed-clock";
130 compatible = "fixed-clock";
135 compatible = "fixed-clock";
136 clock-frequency = <200000000>;
140 gmac0: ethernet@ff800000 {
141 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
142 reg = <0xff800000 0x2000>;
143 interrupts = <0 90 4>;
144 interrupt-names = "macirq";
145 mac-address = [00 00 00 00 00 00];
146 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
147 reset-names = "stmmaceth", "stmmaceth-ocp";
148 clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
149 clock-names = "stmmaceth";
150 tx-fifo-depth = <16384>;
151 rx-fifo-depth = <16384>;
152 snps,multicast-filter-bins = <256>;
154 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
158 gmac1: ethernet@ff802000 {
159 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
160 reg = <0xff802000 0x2000>;
161 interrupts = <0 91 4>;
162 interrupt-names = "macirq";
163 mac-address = [00 00 00 00 00 00];
164 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
165 reset-names = "stmmaceth", "stmmaceth-ocp";
166 clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
167 clock-names = "stmmaceth";
168 tx-fifo-depth = <16384>;
169 rx-fifo-depth = <16384>;
170 snps,multicast-filter-bins = <256>;
172 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
176 gmac2: ethernet@ff804000 {
177 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
178 reg = <0xff804000 0x2000>;
179 interrupts = <0 92 4>;
180 interrupt-names = "macirq";
181 mac-address = [00 00 00 00 00 00];
182 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
183 reset-names = "stmmaceth", "stmmaceth-ocp";
184 clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
185 clock-names = "stmmaceth";
186 tx-fifo-depth = <16384>;
187 rx-fifo-depth = <16384>;
188 snps,multicast-filter-bins = <256>;
190 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
194 gpio0: gpio@ffc03200 {
195 #address-cells = <1>;
197 compatible = "snps,dw-apb-gpio";
198 reg = <0xffc03200 0x100>;
199 resets = <&rst GPIO0_RESET>;
202 porta: gpio-controller@0 {
203 compatible = "snps,dw-apb-gpio-port";
206 snps,nr-gpios = <24>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 interrupts = <0 110 4>;
214 gpio1: gpio@ffc03300 {
215 #address-cells = <1>;
217 compatible = "snps,dw-apb-gpio";
218 reg = <0xffc03300 0x100>;
219 resets = <&rst GPIO1_RESET>;
222 portb: gpio-controller@0 {
223 compatible = "snps,dw-apb-gpio-port";
226 snps,nr-gpios = <24>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 interrupts = <0 111 4>;
235 #address-cells = <1>;
237 compatible = "snps,designware-i2c";
238 reg = <0xffc02800 0x100>;
239 interrupts = <0 103 4>;
240 resets = <&rst I2C0_RESET>;
241 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
246 #address-cells = <1>;
248 compatible = "snps,designware-i2c";
249 reg = <0xffc02900 0x100>;
250 interrupts = <0 104 4>;
251 resets = <&rst I2C1_RESET>;
252 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
257 #address-cells = <1>;
259 compatible = "snps,designware-i2c";
260 reg = <0xffc02a00 0x100>;
261 interrupts = <0 105 4>;
262 resets = <&rst I2C2_RESET>;
263 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
268 #address-cells = <1>;
270 compatible = "snps,designware-i2c";
271 reg = <0xffc02b00 0x100>;
272 interrupts = <0 106 4>;
273 resets = <&rst I2C3_RESET>;
274 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
279 #address-cells = <1>;
281 compatible = "snps,designware-i2c";
282 reg = <0xffc02c00 0x100>;
283 interrupts = <0 107 4>;
284 resets = <&rst I2C4_RESET>;
285 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
289 mmc: dwmmc0@ff808000 {
290 #address-cells = <1>;
292 compatible = "altr,socfpga-dw-mshc";
293 reg = <0xff808000 0x1000>;
294 interrupts = <0 96 4>;
295 fifo-depth = <0x400>;
296 resets = <&rst SDMMC_RESET>;
297 reset-names = "reset";
298 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
299 <&clkmgr STRATIX10_SDMMC_CLK>;
300 clock-names = "biu", "ciu";
305 nand: nand-controller@ffb90000 {
306 #address-cells = <1>;
308 compatible = "altr,socfpga-denali-nand";
309 reg = <0xffb90000 0x10000>,
311 reg-names = "nand_data", "denali_reg";
312 interrupts = <0 97 4>;
313 clocks = <&clkmgr STRATIX10_NAND_CLK>,
314 <&clkmgr STRATIX10_NAND_X_CLK>,
315 <&clkmgr STRATIX10_NAND_ECC_CLK>;
316 clock-names = "nand", "nand_x", "ecc";
317 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
321 ocram: sram@ffe00000 {
322 compatible = "mmio-sram";
323 reg = <0xffe00000 0x100000>;
326 pdma: pdma@ffda0000 {
327 compatible = "arm,pl330", "arm,primecell";
328 reg = <0xffda0000 0x1000>;
329 interrupts = <0 81 4>,
340 #dma-requests = <32>;
341 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
342 clock-names = "apb_pclk";
343 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
344 reset-names = "dma", "dma-ocp";
347 rst: rstmgr@ffd11000 {
349 compatible = "altr,stratix10-rst-mgr";
350 reg = <0xffd11000 0x1000>;
353 smmu: iommu@fa000000 {
354 compatible = "arm,mmu-500", "arm,smmu-v2";
355 reg = <0xfa000000 0x40000>;
356 #global-interrupts = <2>;
358 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
359 clock-names = "iommu";
360 interrupt-parent = <&intc>;
361 interrupts = <0 128 4>, /* Global Secure Fault */
362 <0 129 4>, /* Global Non-secure Fault */
363 /* Non-secure Context Interrupts (32) */
364 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
365 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
366 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
367 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
368 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
369 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
370 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
371 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
372 stream-match-mask = <0x7ff0>;
377 compatible = "snps,dw-apb-ssi";
378 #address-cells = <1>;
380 reg = <0xffda4000 0x1000>;
381 interrupts = <0 99 4>;
382 resets = <&rst SPIM0_RESET>;
385 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
390 compatible = "snps,dw-apb-ssi";
391 #address-cells = <1>;
393 reg = <0xffda5000 0x1000>;
394 interrupts = <0 100 4>;
395 resets = <&rst SPIM1_RESET>;
398 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
402 sysmgr: sysmgr@ffd12000 {
403 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
404 reg = <0xffd12000 0x228>;
409 compatible = "arm,armv8-timer";
410 interrupts = <1 13 0xf08>,
416 timer0: timer0@ffc03000 {
417 compatible = "snps,dw-apb-timer";
418 interrupts = <0 113 4>;
419 reg = <0xffc03000 0x100>;
420 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
421 clock-names = "timer";
424 timer1: timer1@ffc03100 {
425 compatible = "snps,dw-apb-timer";
426 interrupts = <0 114 4>;
427 reg = <0xffc03100 0x100>;
428 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
429 clock-names = "timer";
432 timer2: timer2@ffd00000 {
433 compatible = "snps,dw-apb-timer";
434 interrupts = <0 115 4>;
435 reg = <0xffd00000 0x100>;
436 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
437 clock-names = "timer";
440 timer3: timer3@ffd00100 {
441 compatible = "snps,dw-apb-timer";
442 interrupts = <0 116 4>;
443 reg = <0xffd00100 0x100>;
444 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
445 clock-names = "timer";
448 uart0: serial@ffc02000 {
449 compatible = "snps,dw-apb-uart";
450 reg = <0xffc02000 0x100>;
451 interrupts = <0 108 4>;
454 resets = <&rst UART0_RESET>;
455 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
459 uart1: serial@ffc02100 {
460 compatible = "snps,dw-apb-uart";
461 reg = <0xffc02100 0x100>;
462 interrupts = <0 109 4>;
465 resets = <&rst UART1_RESET>;
466 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
472 compatible = "usb-nop-xceiv";
477 compatible = "snps,dwc2";
478 reg = <0xffb00000 0x40000>;
479 interrupts = <0 93 4>;
481 phy-names = "usb2-phy";
482 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
483 reset-names = "dwc2", "dwc2-ecc";
484 clocks = <&clkmgr STRATIX10_USB_CLK>;
490 compatible = "snps,dwc2";
491 reg = <0xffb40000 0x40000>;
492 interrupts = <0 94 4>;
494 phy-names = "usb2-phy";
495 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
496 reset-names = "dwc2", "dwc2-ecc";
497 clocks = <&clkmgr STRATIX10_USB_CLK>;
502 watchdog0: watchdog@ffd00200 {
503 compatible = "snps,dw-wdt";
504 reg = <0xffd00200 0x100>;
505 interrupts = <0 117 4>;
506 resets = <&rst WATCHDOG0_RESET>;
507 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
511 watchdog1: watchdog@ffd00300 {
512 compatible = "snps,dw-wdt";
513 reg = <0xffd00300 0x100>;
514 interrupts = <0 118 4>;
515 resets = <&rst WATCHDOG1_RESET>;
516 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
520 watchdog2: watchdog@ffd00400 {
521 compatible = "snps,dw-wdt";
522 reg = <0xffd00400 0x100>;
523 interrupts = <0 125 4>;
524 resets = <&rst WATCHDOG2_RESET>;
525 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
529 watchdog3: watchdog@ffd00500 {
530 compatible = "snps,dw-wdt";
531 reg = <0xffd00500 0x100>;
532 interrupts = <0 126 4>;
533 resets = <&rst WATCHDOG3_RESET>;
534 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
539 compatible = "altr,sdr-ctl", "syscon";
540 reg = <0xf8011100 0xc0>;
544 compatible = "altr,socfpga-s10-ecc-manager",
545 "altr,socfpga-a10-ecc-manager";
546 altr,sysmgr-syscon = <&sysmgr>;
547 #address-cells = <1>;
549 interrupts = <0 15 4>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
555 compatible = "altr,sdram-edac-s10";
556 altr,sdr-syscon = <&sdr>;
561 compatible = "altr,socfpga-s10-ocram-ecc",
562 "altr,socfpga-a10-ocram-ecc";
563 reg = <0xff8cc000 0x100>;
564 altr,ecc-parent = <&ocram>;
569 compatible = "altr,socfpga-s10-usb-ecc",
570 "altr,socfpga-usb-ecc";
571 reg = <0xff8c4000 0x100>;
572 altr,ecc-parent = <&usb0>;
576 emac0-rx-ecc@ff8c0000 {
577 compatible = "altr,socfpga-s10-eth-mac-ecc",
578 "altr,socfpga-eth-mac-ecc";
579 reg = <0xff8c0000 0x100>;
580 altr,ecc-parent = <&gmac0>;
584 emac0-tx-ecc@ff8c0400 {
585 compatible = "altr,socfpga-s10-eth-mac-ecc",
586 "altr,socfpga-eth-mac-ecc";
587 reg = <0xff8c0400 0x100>;
588 altr,ecc-parent = <&gmac0>;
595 compatible = "cdns,qspi-nor";
596 #address-cells = <1>;
598 reg = <0xff8d2000 0x100>,
599 <0xff900000 0x100000>;
600 interrupts = <0 3 4>;
601 cdns,fifo-depth = <128>;
602 cdns,fifo-width = <4>;
603 cdns,trigger-address = <0x00000000>;
604 clocks = <&qspi_clk>;
611 compatible = "intel,stratix10-svc";
613 memory-region = <&service_reserved>;
616 compatible = "intel,stratix10-soc-fpga-mgr";