1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2020 Arm Ltd.
3 // based on the H6 dtsi, which is:
4 // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun6i-rtc.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
14 interrupt-parent = <&gic>;
23 compatible = "arm,cortex-a53";
26 enable-method = "psci";
27 clocks = <&ccu CLK_CPUX>;
31 compatible = "arm,cortex-a53";
34 enable-method = "psci";
35 clocks = <&ccu CLK_CPUX>;
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 clocks = <&ccu CLK_CPUX>;
47 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 clocks = <&ccu CLK_CPUX>;
61 * 256 KiB reserved for Trusted Firmware-A (BL31).
62 * This is added by BL31 itself, but some bootloaders fail
63 * to propagate this into the DTB handed to kernels.
66 reg = <0x0 0x40000000 0x0 0x40000>;
73 compatible = "fixed-clock";
74 clock-frequency = <24000000>;
75 clock-output-names = "osc24M";
79 compatible = "arm,cortex-a53-pmu";
80 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 compatible = "arm,psci-0.2";
93 compatible = "arm,armv8-timer";
94 arm,no-tick-in-suspend;
95 interrupts = <GIC_PPI 13
96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
106 compatible = "simple-bus";
107 #address-cells = <1>;
109 ranges = <0x0 0x0 0x0 0x40000000>;
111 syscon: syscon@3000000 {
112 compatible = "allwinner,sun50i-h616-system-control";
113 reg = <0x03000000 0x1000>;
114 #address-cells = <1>;
119 compatible = "mmio-sram";
120 reg = <0x00028000 0x30000>;
121 #address-cells = <1>;
123 ranges = <0 0x00028000 0x30000>;
128 compatible = "allwinner,sun50i-h616-ccu";
129 reg = <0x03001000 0x1000>;
130 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
131 clock-names = "hosc", "losc", "iosc";
137 compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
138 reg = <0x03006000 0x1000>;
139 #address-cells = <1>;
143 watchdog: watchdog@30090a0 {
144 compatible = "allwinner,sun50i-h616-wdt",
145 "allwinner,sun6i-a31-wdt";
146 reg = <0x030090a0 0x20>;
147 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
151 pio: pinctrl@300b000 {
152 compatible = "allwinner,sun50i-h616-pinctrl";
153 reg = <0x0300b000 0x400>;
154 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
163 clock-names = "apb", "hosc", "losc";
166 interrupt-controller;
167 #interrupt-cells = <3>;
169 ext_rgmii_pins: rgmii-pins {
170 pins = "PI0", "PI1", "PI2", "PI3", "PI4",
171 "PI5", "PI7", "PI8", "PI9", "PI10",
172 "PI11", "PI12", "PI13", "PI14", "PI15",
175 drive-strength = <40>;
178 i2c0_pins: i2c0-pins {
183 i2c3_ph_pins: i2c3-ph-pins {
188 ir_rx_pin: ir-rx-pin {
193 mmc0_pins: mmc0-pins {
194 pins = "PF0", "PF1", "PF2", "PF3",
197 drive-strength = <30>;
202 mmc1_pins: mmc1-pins {
203 pins = "PG0", "PG1", "PG2", "PG3",
206 drive-strength = <30>;
210 mmc2_pins: mmc2-pins {
211 pins = "PC0", "PC1", "PC5", "PC6",
212 "PC8", "PC9", "PC10", "PC11",
213 "PC13", "PC14", "PC15", "PC16";
215 drive-strength = <30>;
220 spi0_pins: spi0-pins {
221 pins = "PC0", "PC2", "PC4";
226 spi0_cs0_pin: spi0-cs0-pin {
232 spi1_pins: spi1-pins {
233 pins = "PH6", "PH7", "PH8";
238 spi1_cs0_pin: spi1-cs0-pin {
243 uart0_ph_pins: uart0-ph-pins {
249 uart1_pins: uart1-pins {
255 uart1_rts_cts_pins: uart1-rts-cts-pins {
261 gic: interrupt-controller@3021000 {
262 compatible = "arm,gic-400";
263 reg = <0x03021000 0x1000>,
267 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
268 interrupt-controller;
269 #interrupt-cells = <3>;
273 compatible = "allwinner,sun50i-h616-mmc",
274 "allwinner,sun50i-a100-mmc";
275 reg = <0x04020000 0x1000>;
276 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
277 clock-names = "ahb", "mmc";
278 resets = <&ccu RST_BUS_MMC0>;
280 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&mmc0_pins>;
284 max-frequency = <150000000>;
289 #address-cells = <1>;
294 compatible = "allwinner,sun50i-h616-mmc",
295 "allwinner,sun50i-a100-mmc";
296 reg = <0x04021000 0x1000>;
297 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
298 clock-names = "ahb", "mmc";
299 resets = <&ccu RST_BUS_MMC1>;
301 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&mmc1_pins>;
305 max-frequency = <150000000>;
310 #address-cells = <1>;
315 compatible = "allwinner,sun50i-h616-emmc",
316 "allwinner,sun50i-a100-emmc";
317 reg = <0x04022000 0x1000>;
318 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
319 clock-names = "ahb", "mmc";
320 resets = <&ccu RST_BUS_MMC2>;
322 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&mmc2_pins>;
326 max-frequency = <150000000>;
331 #address-cells = <1>;
335 uart0: serial@5000000 {
336 compatible = "snps,dw-apb-uart";
337 reg = <0x05000000 0x400>;
338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&ccu CLK_BUS_UART0>;
342 resets = <&ccu RST_BUS_UART0>;
346 uart1: serial@5000400 {
347 compatible = "snps,dw-apb-uart";
348 reg = <0x05000400 0x400>;
349 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&ccu CLK_BUS_UART1>;
353 resets = <&ccu RST_BUS_UART1>;
357 uart2: serial@5000800 {
358 compatible = "snps,dw-apb-uart";
359 reg = <0x05000800 0x400>;
360 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&ccu CLK_BUS_UART2>;
364 resets = <&ccu RST_BUS_UART2>;
368 uart3: serial@5000c00 {
369 compatible = "snps,dw-apb-uart";
370 reg = <0x05000c00 0x400>;
371 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&ccu CLK_BUS_UART3>;
375 resets = <&ccu RST_BUS_UART3>;
379 uart4: serial@5001000 {
380 compatible = "snps,dw-apb-uart";
381 reg = <0x05001000 0x400>;
382 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&ccu CLK_BUS_UART4>;
386 resets = <&ccu RST_BUS_UART4>;
390 uart5: serial@5001400 {
391 compatible = "snps,dw-apb-uart";
392 reg = <0x05001400 0x400>;
393 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&ccu CLK_BUS_UART5>;
397 resets = <&ccu RST_BUS_UART5>;
402 compatible = "allwinner,sun50i-h616-i2c",
403 "allwinner,sun8i-v536-i2c",
404 "allwinner,sun6i-a31-i2c";
405 reg = <0x05002000 0x400>;
406 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&ccu CLK_BUS_I2C0>;
408 resets = <&ccu RST_BUS_I2C0>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c0_pins>;
412 #address-cells = <1>;
417 compatible = "allwinner,sun50i-h616-i2c",
418 "allwinner,sun8i-v536-i2c",
419 "allwinner,sun6i-a31-i2c";
420 reg = <0x05002400 0x400>;
421 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&ccu CLK_BUS_I2C1>;
423 resets = <&ccu RST_BUS_I2C1>;
425 #address-cells = <1>;
430 compatible = "allwinner,sun50i-h616-i2c",
431 "allwinner,sun8i-v536-i2c",
432 "allwinner,sun6i-a31-i2c";
433 reg = <0x05002800 0x400>;
434 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&ccu CLK_BUS_I2C2>;
436 resets = <&ccu RST_BUS_I2C2>;
438 #address-cells = <1>;
443 compatible = "allwinner,sun50i-h616-i2c",
444 "allwinner,sun8i-v536-i2c",
445 "allwinner,sun6i-a31-i2c";
446 reg = <0x05002c00 0x400>;
447 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&ccu CLK_BUS_I2C3>;
449 resets = <&ccu RST_BUS_I2C3>;
451 #address-cells = <1>;
456 compatible = "allwinner,sun50i-h616-i2c",
457 "allwinner,sun8i-v536-i2c",
458 "allwinner,sun6i-a31-i2c";
459 reg = <0x05003000 0x400>;
460 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&ccu CLK_BUS_I2C4>;
462 resets = <&ccu RST_BUS_I2C4>;
464 #address-cells = <1>;
469 compatible = "allwinner,sun50i-h616-spi",
470 "allwinner,sun8i-h3-spi";
471 reg = <0x05010000 0x1000>;
472 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
474 clock-names = "ahb", "mod";
475 resets = <&ccu RST_BUS_SPI0>;
477 #address-cells = <1>;
482 compatible = "allwinner,sun50i-h616-spi",
483 "allwinner,sun8i-h3-spi";
484 reg = <0x05011000 0x1000>;
485 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
487 clock-names = "ahb", "mod";
488 resets = <&ccu RST_BUS_SPI1>;
490 #address-cells = <1>;
494 emac0: ethernet@5020000 {
495 compatible = "allwinner,sun50i-h616-emac0",
496 "allwinner,sun50i-a64-emac";
497 reg = <0x05020000 0x10000>;
498 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
499 interrupt-names = "macirq";
500 clocks = <&ccu CLK_BUS_EMAC0>;
501 clock-names = "stmmaceth";
502 resets = <&ccu RST_BUS_EMAC0>;
503 reset-names = "stmmaceth";
508 compatible = "snps,dwmac-mdio";
509 #address-cells = <1>;
514 usbotg: usb@5100000 {
515 compatible = "allwinner,sun50i-h616-musb",
516 "allwinner,sun8i-h3-musb";
517 reg = <0x05100000 0x0400>;
518 clocks = <&ccu CLK_BUS_OTG>;
519 resets = <&ccu RST_BUS_OTG>;
520 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
521 interrupt-names = "mc";
524 extcon = <&usbphy 0>;
528 usbphy: phy@5100400 {
529 compatible = "allwinner,sun50i-h616-usb-phy";
530 reg = <0x05100400 0x24>,
535 reg-names = "phy_ctrl",
540 clocks = <&ccu CLK_USB_PHY0>,
544 <&ccu CLK_BUS_EHCI2>;
545 clock-names = "usb0_phy",
550 resets = <&ccu RST_USB_PHY0>,
554 reset-names = "usb0_reset",
563 compatible = "allwinner,sun50i-h616-ehci",
565 reg = <0x05101000 0x100>;
566 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&ccu CLK_BUS_OHCI0>,
568 <&ccu CLK_BUS_EHCI0>,
569 <&ccu CLK_USB_OHCI0>;
570 resets = <&ccu RST_BUS_OHCI0>,
571 <&ccu RST_BUS_EHCI0>;
578 compatible = "allwinner,sun50i-h616-ohci",
580 reg = <0x05101400 0x100>;
581 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&ccu CLK_BUS_OHCI0>,
583 <&ccu CLK_USB_OHCI0>;
584 resets = <&ccu RST_BUS_OHCI0>;
591 compatible = "allwinner,sun50i-h616-ehci",
593 reg = <0x05200000 0x100>;
594 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&ccu CLK_BUS_OHCI1>,
596 <&ccu CLK_BUS_EHCI1>,
597 <&ccu CLK_USB_OHCI1>;
598 resets = <&ccu RST_BUS_OHCI1>,
599 <&ccu RST_BUS_EHCI1>;
606 compatible = "allwinner,sun50i-h616-ohci",
608 reg = <0x05200400 0x100>;
609 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&ccu CLK_BUS_OHCI1>,
611 <&ccu CLK_USB_OHCI1>;
612 resets = <&ccu RST_BUS_OHCI1>;
619 compatible = "allwinner,sun50i-h616-ehci",
621 reg = <0x05310000 0x100>;
622 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&ccu CLK_BUS_OHCI2>,
624 <&ccu CLK_BUS_EHCI2>,
625 <&ccu CLK_USB_OHCI2>;
626 resets = <&ccu RST_BUS_OHCI2>,
627 <&ccu RST_BUS_EHCI2>;
634 compatible = "allwinner,sun50i-h616-ohci",
636 reg = <0x05310400 0x100>;
637 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&ccu CLK_BUS_OHCI2>,
639 <&ccu CLK_USB_OHCI2>;
640 resets = <&ccu RST_BUS_OHCI2>;
647 compatible = "allwinner,sun50i-h616-ehci",
649 reg = <0x05311000 0x100>;
650 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&ccu CLK_BUS_OHCI3>,
652 <&ccu CLK_BUS_EHCI3>,
653 <&ccu CLK_USB_OHCI3>;
654 resets = <&ccu RST_BUS_OHCI3>,
655 <&ccu RST_BUS_EHCI3>;
662 compatible = "allwinner,sun50i-h616-ohci",
664 reg = <0x05311400 0x100>;
665 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&ccu CLK_BUS_OHCI3>,
667 <&ccu CLK_USB_OHCI3>;
668 resets = <&ccu RST_BUS_OHCI3>;
675 compatible = "allwinner,sun50i-h616-rtc";
676 reg = <0x07000000 0x400>;
677 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
679 <&ccu CLK_PLL_SYSTEM_32K>;
680 clock-names = "bus", "hosc",
685 r_ccu: clock@7010000 {
686 compatible = "allwinner,sun50i-h616-r-ccu";
687 reg = <0x07010000 0x210>;
688 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
689 <&ccu CLK_PLL_PERIPH0>;
690 clock-names = "hosc", "losc", "iosc", "pll-periph";
695 r_pio: pinctrl@7022000 {
696 compatible = "allwinner,sun50i-h616-r-pinctrl";
697 reg = <0x07022000 0x400>;
698 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
700 clock-names = "apb", "hosc", "losc";
705 r_i2c_pins: r-i2c-pins {
710 r_rsb_pins: r-rsb-pins {
717 compatible = "allwinner,sun50i-h616-ir",
718 "allwinner,sun6i-a31-ir";
719 reg = <0x07040000 0x400>;
720 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&r_ccu CLK_R_APB1_IR>,
723 clock-names = "apb", "ir";
724 resets = <&r_ccu RST_R_APB1_IR>;
725 pinctrl-names = "default";
726 pinctrl-0 = <&ir_rx_pin>;
731 compatible = "allwinner,sun50i-h616-i2c",
732 "allwinner,sun8i-v536-i2c",
733 "allwinner,sun6i-a31-i2c";
734 reg = <0x07081400 0x400>;
735 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&r_ccu CLK_R_APB2_I2C>;
737 resets = <&r_ccu RST_R_APB2_I2C>;
739 #address-cells = <1>;
744 compatible = "allwinner,sun50i-h616-rsb",
745 "allwinner,sun8i-a23-rsb";
746 reg = <0x07083000 0x400>;
747 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&r_ccu CLK_R_APB2_RSB>;
749 clock-frequency = <3000000>;
750 resets = <&r_ccu RST_R_APB2_RSB>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&r_rsb_pins>;
754 #address-cells = <1>;