arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
   8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
   9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  11
  12 / {
  13         interrupt-parent = <&gic>;
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu0: cpu@0 {
  22                         compatible = "arm,cortex-a53", "arm,armv8";
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         enable-method = "psci";
  26                 };
  27
  28                 cpu1: cpu@1 {
  29                         compatible = "arm,cortex-a53", "arm,armv8";
  30                         device_type = "cpu";
  31                         reg = <1>;
  32                         enable-method = "psci";
  33                 };
  34
  35                 cpu2: cpu@2 {
  36                         compatible = "arm,cortex-a53", "arm,armv8";
  37                         device_type = "cpu";
  38                         reg = <2>;
  39                         enable-method = "psci";
  40                 };
  41
  42                 cpu3: cpu@3 {
  43                         compatible = "arm,cortex-a53", "arm,armv8";
  44                         device_type = "cpu";
  45                         reg = <3>;
  46                         enable-method = "psci";
  47                 };
  48         };
  49
  50         iosc: internal-osc-clk {
  51                 #clock-cells = <0>;
  52                 compatible = "fixed-clock";
  53                 clock-frequency = <16000000>;
  54                 clock-accuracy = <300000000>;
  55                 clock-output-names = "iosc";
  56         };
  57
  58         osc24M: osc24M_clk {
  59                 #clock-cells = <0>;
  60                 compatible = "fixed-clock";
  61                 clock-frequency = <24000000>;
  62                 clock-output-names = "osc24M";
  63         };
  64
  65         osc32k: osc32k_clk {
  66                 #clock-cells = <0>;
  67                 compatible = "fixed-clock";
  68                 clock-frequency = <32768>;
  69                 clock-output-names = "osc32k";
  70         };
  71
  72         pmu {
  73                 compatible = "arm,cortex-a53-pmu";
  74                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  77                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  78                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  79         };
  80
  81         psci {
  82                 compatible = "arm,psci-0.2";
  83                 method = "smc";
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv8-timer";
  88                 interrupts = <GIC_PPI 13
  89                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  90                              <GIC_PPI 14
  91                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  92                              <GIC_PPI 11
  93                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  94                              <GIC_PPI 10
  95                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  96         };
  97
  98         soc {
  99                 compatible = "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 ccu: clock@3001000 {
 105                         compatible = "allwinner,sun50i-h6-ccu";
 106                         reg = <0x03001000 0x1000>;
 107                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
 108                         clock-names = "hosc", "losc", "iosc";
 109                         #clock-cells = <1>;
 110                         #reset-cells = <1>;
 111                 };
 112
 113                 pio: pinctrl@300b000 {
 114                         compatible = "allwinner,sun50i-h6-pinctrl";
 115                         reg = <0x0300b000 0x400>;
 116                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 118                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 119                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 120                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
 121                         clock-names = "apb", "hosc", "losc";
 122                         gpio-controller;
 123                         #gpio-cells = <3>;
 124                         interrupt-controller;
 125                         #interrupt-cells = <3>;
 126
 127                         mmc0_pins: mmc0-pins {
 128                                 pins = "PF0", "PF1", "PF2", "PF3",
 129                                        "PF4", "PF5";
 130                                 function = "mmc0";
 131                                 drive-strength = <30>;
 132                                 bias-pull-up;
 133                         };
 134
 135                         mmc2_pins: mmc2-pins {
 136                                 pins = "PC1", "PC4", "PC5", "PC6",
 137                                        "PC7", "PC8", "PC9", "PC10",
 138                                        "PC11", "PC12", "PC13", "PC14";
 139                                 function = "mmc2";
 140                                 drive-strength = <30>;
 141                                 bias-pull-up;
 142                         };
 143
 144                         uart0_ph_pins: uart0-ph {
 145                                 pins = "PH0", "PH1";
 146                                 function = "uart0";
 147                         };
 148                 };
 149
 150                 gic: interrupt-controller@3021000 {
 151                         compatible = "arm,gic-400";
 152                         reg = <0x03021000 0x1000>,
 153                               <0x03022000 0x2000>,
 154                               <0x03024000 0x2000>,
 155                               <0x03026000 0x2000>;
 156                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 157                         interrupt-controller;
 158                         #interrupt-cells = <3>;
 159                 };
 160
 161                 mmc0: mmc@4020000 {
 162                         compatible = "allwinner,sun50i-h6-mmc",
 163                                      "allwinner,sun50i-a64-mmc";
 164                         reg = <0x04020000 0x1000>;
 165                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 166                         clock-names = "ahb", "mmc";
 167                         resets = <&ccu RST_BUS_MMC0>;
 168                         reset-names = "ahb";
 169                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 170                         status = "disabled";
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                 };
 174
 175                 mmc1: mmc@4021000 {
 176                         compatible = "allwinner,sun50i-h6-mmc",
 177                                      "allwinner,sun50i-a64-mmc";
 178                         reg = <0x04021000 0x1000>;
 179                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 180                         clock-names = "ahb", "mmc";
 181                         resets = <&ccu RST_BUS_MMC1>;
 182                         reset-names = "ahb";
 183                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 184                         status = "disabled";
 185                         #address-cells = <1>;
 186                         #size-cells = <0>;
 187                 };
 188
 189                 mmc2: mmc@4022000 {
 190                         compatible = "allwinner,sun50i-h6-emmc",
 191                                      "allwinner,sun50i-a64-emmc";
 192                         reg = <0x04022000 0x1000>;
 193                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 194                         clock-names = "ahb", "mmc";
 195                         resets = <&ccu RST_BUS_MMC2>;
 196                         reset-names = "ahb";
 197                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 198                         status = "disabled";
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                 };
 202
 203                 uart0: serial@5000000 {
 204                         compatible = "snps,dw-apb-uart";
 205                         reg = <0x05000000 0x400>;
 206                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 207                         reg-shift = <2>;
 208                         reg-io-width = <4>;
 209                         clocks = <&ccu CLK_BUS_UART0>;
 210                         resets = <&ccu RST_BUS_UART0>;
 211                         status = "disabled";
 212                 };
 213
 214                 uart1: serial@5000400 {
 215                         compatible = "snps,dw-apb-uart";
 216                         reg = <0x05000400 0x400>;
 217                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 218                         reg-shift = <2>;
 219                         reg-io-width = <4>;
 220                         clocks = <&ccu CLK_BUS_UART1>;
 221                         resets = <&ccu RST_BUS_UART1>;
 222                         status = "disabled";
 223                 };
 224
 225                 uart2: serial@5000800 {
 226                         compatible = "snps,dw-apb-uart";
 227                         reg = <0x05000800 0x400>;
 228                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 229                         reg-shift = <2>;
 230                         reg-io-width = <4>;
 231                         clocks = <&ccu CLK_BUS_UART2>;
 232                         resets = <&ccu RST_BUS_UART2>;
 233                         status = "disabled";
 234                 };
 235
 236                 uart3: serial@5000c00 {
 237                         compatible = "snps,dw-apb-uart";
 238                         reg = <0x05000c00 0x400>;
 239                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 240                         reg-shift = <2>;
 241                         reg-io-width = <4>;
 242                         clocks = <&ccu CLK_BUS_UART3>;
 243                         resets = <&ccu RST_BUS_UART3>;
 244                         status = "disabled";
 245                 };
 246
 247                 r_ccu: clock@7010000 {
 248                         compatible = "allwinner,sun50i-h6-r-ccu";
 249                         reg = <0x07010000 0x400>;
 250                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 251                                  <&ccu CLK_PLL_PERIPH0>;
 252                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 253                         #clock-cells = <1>;
 254                         #reset-cells = <1>;
 255                 };
 256
 257                 r_intc: interrupt-controller@7021000 {
 258                         compatible = "allwinner,sun50i-h6-r-intc",
 259                                      "allwinner,sun6i-a31-r-intc";
 260                         interrupt-controller;
 261                         #interrupt-cells = <2>;
 262                         reg = <0x07021000 0x400>;
 263                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 264                 };
 265
 266                 r_pio: pinctrl@7022000 {
 267                         compatible = "allwinner,sun50i-h6-r-pinctrl";
 268                         reg = <0x07022000 0x400>;
 269                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 270                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
 272                         clock-names = "apb", "hosc", "losc";
 273                         gpio-controller;
 274                         #gpio-cells = <3>;
 275                         interrupt-controller;
 276                         #interrupt-cells = <3>;
 277
 278                         r_i2c_pins: r-i2c {
 279                                 pins = "PL0", "PL1";
 280                                 function = "s_i2c";
 281                         };
 282                 };
 283
 284                 r_i2c: i2c@7081400 {
 285                         compatible = "allwinner,sun6i-a31-i2c";
 286                         reg = <0x07081400 0x400>;
 287                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&r_ccu CLK_R_APB2_I2C>;
 289                         resets = <&r_ccu RST_R_APB2_I2C>;
 290                         pinctrl-names = "default";
 291                         pinctrl-0 = <&r_i2c_pins>;
 292                         status = "disabled";
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                 };
 296         };
 297 };