2 * Copyright (C) 2016 ARM Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <arm/sunxi-h3-h5.dtsi>
51 compatible = "arm,cortex-a53";
54 enable-method = "psci";
58 compatible = "arm,cortex-a53";
61 enable-method = "psci";
65 compatible = "arm,cortex-a53";
68 enable-method = "psci";
72 compatible = "arm,cortex-a53";
75 enable-method = "psci";
80 compatible = "arm,cortex-a53-pmu";
81 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
85 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
89 compatible = "arm,psci-0.2";
94 compatible = "arm,armv8-timer";
95 interrupts = <GIC_PPI 13
96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
106 syscon: system-control@1c00000 {
107 compatible = "allwinner,sun50i-h5-system-control";
108 reg = <0x01c00000 0x1000>;
109 #address-cells = <1>;
113 sram_c1: sram@18000 {
114 compatible = "mmio-sram";
115 reg = <0x00018000 0x1c000>;
116 #address-cells = <1>;
118 ranges = <0 0x00018000 0x1c000>;
120 ve_sram: sram-section@0 {
121 compatible = "allwinner,sun50i-h5-sram-c1",
122 "allwinner,sun4i-a10-sram-c1";
123 reg = <0x000000 0x1c000>;
128 video-codec@1c0e000 {
129 compatible = "allwinner,sun50i-h5-video-engine";
130 reg = <0x01c0e000 0x1000>;
131 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
133 clock-names = "ahb", "mod", "ram";
134 resets = <&ccu RST_BUS_VE>;
135 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
136 allwinner,sram = <&ve_sram 1>;
140 compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
141 reg = <0x01e80000 0x30000>;
143 * While the datasheet lists an interrupt for the
144 * PMU, the actual silicon does not have the PMU
145 * block. Reads all return zero, and writes are
148 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-names = "gp",
170 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
171 clock-names = "bus", "core";
172 resets = <&ccu RST_BUS_GPU>;
174 assigned-clocks = <&ccu CLK_GPU>;
175 assigned-clock-rates = <384000000>;
181 compatible = "allwinner,sun50i-h5-ccu";
185 compatible = "allwinner,sun50i-h5-de2-clk";
189 compatible = "allwinner,sun50i-h5-mmc",
190 "allwinner,sun50i-a64-mmc";
191 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
192 clock-names = "ahb", "mmc";
196 compatible = "allwinner,sun50i-h5-mmc",
197 "allwinner,sun50i-a64-mmc";
198 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
199 clock-names = "ahb", "mmc";
203 compatible = "allwinner,sun50i-h5-emmc",
204 "allwinner,sun50i-a64-emmc";
205 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
206 clock-names = "ahb", "mmc";
210 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
213 compatible = "allwinner,sun50i-h5-pinctrl";
217 compatible = "allwinner,sun50i-h5-rtc";
221 compatible = "allwinner,sun50i-h5-sid";