2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/reset/sun8i-r-ccu.h>
54 interrupt-parent = <&gic>;
63 simplefb_lcd: framebuffer-lcd {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "mixer0-lcd0";
67 clocks = <&ccu CLK_TCON0>,
68 <&display_clocks CLK_MIXER0>;
72 simplefb_hdmi: framebuffer-hdmi {
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "mixer1-lcd1-hdmi";
76 clocks = <&display_clocks CLK_MIXER1>,
77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
87 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
94 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
101 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
108 compatible = "arm,cortex-a53", "arm,armv8";
111 enable-method = "psci";
117 compatible = "fixed-clock";
118 clock-frequency = <24000000>;
119 clock-output-names = "osc24M";
124 compatible = "fixed-clock";
125 clock-frequency = <32768>;
126 clock-output-names = "osc32k";
129 iosc: internal-osc-clk {
131 compatible = "fixed-clock";
132 clock-frequency = <16000000>;
133 clock-accuracy = <300000000>;
134 clock-output-names = "iosc";
138 compatible = "arm,psci-0.2";
143 compatible = "simple-audio-card";
144 simple-audio-card,name = "On-board SPDIF";
146 simple-audio-card,cpu {
147 sound-dai = <&spdif>;
150 simple-audio-card,codec {
151 sound-dai = <&spdif_out>;
155 spdif_out: spdif-out {
156 #sound-dai-cells = <0>;
157 compatible = "linux,spdif-dit";
161 compatible = "arm,armv8-timer";
162 interrupts = <GIC_PPI 13
163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
173 compatible = "simple-bus";
174 #address-cells = <1>;
179 compatible = "allwinner,sun50i-a64-de2";
180 reg = <0x1000000 0x400000>;
181 allwinner,sram = <&de2_sram 1>;
182 #address-cells = <1>;
184 ranges = <0 0x1000000 0x400000>;
186 display_clocks: clock@0 {
187 compatible = "allwinner,sun50i-a64-de2-clk";
188 reg = <0x0 0x100000>;
189 clocks = <&ccu CLK_DE>,
193 resets = <&ccu RST_BUS_DE>;
199 syscon: syscon@1c00000 {
200 compatible = "allwinner,sun50i-a64-system-control";
201 reg = <0x01c00000 0x1000>;
202 #address-cells = <1>;
207 compatible = "mmio-sram";
208 reg = <0x00018000 0x28000>;
209 #address-cells = <1>;
211 ranges = <0 0x00018000 0x28000>;
213 de2_sram: sram-section@0 {
214 compatible = "allwinner,sun50i-a64-sram-c";
215 reg = <0x0000 0x28000>;
220 dma: dma-controller@1c02000 {
221 compatible = "allwinner,sun50i-a64-dma";
222 reg = <0x01c02000 0x1000>;
223 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&ccu CLK_BUS_DMA>;
227 resets = <&ccu RST_BUS_DMA>;
232 compatible = "allwinner,sun50i-a64-mmc";
233 reg = <0x01c0f000 0x1000>;
234 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
235 clock-names = "ahb", "mmc";
236 resets = <&ccu RST_BUS_MMC0>;
238 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
239 max-frequency = <150000000>;
241 #address-cells = <1>;
246 compatible = "allwinner,sun50i-a64-mmc";
247 reg = <0x01c10000 0x1000>;
248 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
249 clock-names = "ahb", "mmc";
250 resets = <&ccu RST_BUS_MMC1>;
252 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
253 max-frequency = <150000000>;
255 #address-cells = <1>;
260 compatible = "allwinner,sun50i-a64-emmc";
261 reg = <0x01c11000 0x1000>;
262 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
263 clock-names = "ahb", "mmc";
264 resets = <&ccu RST_BUS_MMC2>;
266 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
267 max-frequency = <150000000>;
269 #address-cells = <1>;
273 usb_otg: usb@1c19000 {
274 compatible = "allwinner,sun8i-a33-musb";
275 reg = <0x01c19000 0x0400>;
276 clocks = <&ccu CLK_BUS_OTG>;
277 resets = <&ccu RST_BUS_OTG>;
278 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "mc";
282 extcon = <&usbphy 0>;
286 usbphy: phy@1c19400 {
287 compatible = "allwinner,sun50i-a64-usb-phy";
288 reg = <0x01c19400 0x14>,
291 reg-names = "phy_ctrl",
294 clocks = <&ccu CLK_USB_PHY0>,
296 clock-names = "usb0_phy",
298 resets = <&ccu RST_USB_PHY0>,
300 reset-names = "usb0_reset",
307 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
308 reg = <0x01c1a000 0x100>;
309 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&ccu CLK_BUS_OHCI0>,
311 <&ccu CLK_BUS_EHCI0>,
312 <&ccu CLK_USB_OHCI0>;
313 resets = <&ccu RST_BUS_OHCI0>,
314 <&ccu RST_BUS_EHCI0>;
321 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
322 reg = <0x01c1a400 0x100>;
323 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_OHCI0>,
325 <&ccu CLK_USB_OHCI0>;
326 resets = <&ccu RST_BUS_OHCI0>;
333 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
334 reg = <0x01c1b000 0x100>;
335 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&ccu CLK_BUS_OHCI1>,
337 <&ccu CLK_BUS_EHCI1>,
338 <&ccu CLK_USB_OHCI1>;
339 resets = <&ccu RST_BUS_OHCI1>,
340 <&ccu RST_BUS_EHCI1>;
347 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
348 reg = <0x01c1b400 0x100>;
349 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&ccu CLK_BUS_OHCI1>,
351 <&ccu CLK_USB_OHCI1>;
352 resets = <&ccu RST_BUS_OHCI1>;
359 compatible = "allwinner,sun50i-a64-ccu";
360 reg = <0x01c20000 0x400>;
361 clocks = <&osc24M>, <&osc32k>;
362 clock-names = "hosc", "losc";
367 pio: pinctrl@1c20800 {
368 compatible = "allwinner,sun50i-a64-pinctrl";
369 reg = <0x01c20800 0x400>;
370 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
374 clock-names = "apb", "hosc", "losc";
377 interrupt-controller;
378 #interrupt-cells = <3>;
380 i2c0_pins: i2c0_pins {
385 i2c1_pins: i2c1_pins {
390 mmc0_pins: mmc0-pins {
391 pins = "PF0", "PF1", "PF2", "PF3",
394 drive-strength = <30>;
398 mmc1_pins: mmc1-pins {
399 pins = "PG0", "PG1", "PG2", "PG3",
402 drive-strength = <30>;
406 mmc2_pins: mmc2-pins {
407 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
408 "PC10","PC11", "PC12", "PC13",
409 "PC14", "PC15", "PC16";
411 drive-strength = <30>;
420 rmii_pins: rmii_pins {
421 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
422 "PD18", "PD19", "PD20", "PD22", "PD23";
424 drive-strength = <40>;
427 rgmii_pins: rgmii_pins {
428 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
429 "PD13", "PD15", "PD16", "PD17", "PD18",
430 "PD19", "PD20", "PD21", "PD22", "PD23";
432 drive-strength = <40>;
435 spdif_tx_pin: spdif {
441 pins = "PC0", "PC1", "PC2", "PC3";
446 pins = "PD0", "PD1", "PD2", "PD3";
450 uart0_pins_a: uart0 {
455 uart1_pins: uart1_pins {
460 uart1_rts_cts_pins: uart1_rts_cts_pins {
465 uart2_pins: uart2-pins {
470 uart3_pins: uart3-pins {
475 uart4_pins: uart4-pins {
480 uart4_rts_cts_pins: uart4-rts-cts-pins {
486 spdif: spdif@1c21000 {
487 #sound-dai-cells = <0>;
488 compatible = "allwinner,sun50i-a64-spdif",
489 "allwinner,sun8i-h3-spdif";
490 reg = <0x01c21000 0x400>;
491 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
493 resets = <&ccu RST_BUS_SPDIF>;
494 clock-names = "apb", "spdif";
497 pinctrl-names = "default";
498 pinctrl-0 = <&spdif_tx_pin>;
503 #sound-dai-cells = <0>;
504 compatible = "allwinner,sun50i-a64-i2s",
505 "allwinner,sun8i-h3-i2s";
506 reg = <0x01c22000 0x400>;
507 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
509 clock-names = "apb", "mod";
510 resets = <&ccu RST_BUS_I2S0>;
511 dma-names = "rx", "tx";
512 dmas = <&dma 3>, <&dma 3>;
517 #sound-dai-cells = <0>;
518 compatible = "allwinner,sun50i-a64-i2s",
519 "allwinner,sun8i-h3-i2s";
520 reg = <0x01c22400 0x400>;
521 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
523 clock-names = "apb", "mod";
524 resets = <&ccu RST_BUS_I2S1>;
525 dma-names = "rx", "tx";
526 dmas = <&dma 4>, <&dma 4>;
530 uart0: serial@1c28000 {
531 compatible = "snps,dw-apb-uart";
532 reg = <0x01c28000 0x400>;
533 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&ccu CLK_BUS_UART0>;
537 resets = <&ccu RST_BUS_UART0>;
541 uart1: serial@1c28400 {
542 compatible = "snps,dw-apb-uart";
543 reg = <0x01c28400 0x400>;
544 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&ccu CLK_BUS_UART1>;
548 resets = <&ccu RST_BUS_UART1>;
552 uart2: serial@1c28800 {
553 compatible = "snps,dw-apb-uart";
554 reg = <0x01c28800 0x400>;
555 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&ccu CLK_BUS_UART2>;
559 resets = <&ccu RST_BUS_UART2>;
563 uart3: serial@1c28c00 {
564 compatible = "snps,dw-apb-uart";
565 reg = <0x01c28c00 0x400>;
566 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&ccu CLK_BUS_UART3>;
570 resets = <&ccu RST_BUS_UART3>;
574 uart4: serial@1c29000 {
575 compatible = "snps,dw-apb-uart";
576 reg = <0x01c29000 0x400>;
577 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&ccu CLK_BUS_UART4>;
581 resets = <&ccu RST_BUS_UART4>;
586 compatible = "allwinner,sun6i-a31-i2c";
587 reg = <0x01c2ac00 0x400>;
588 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&ccu CLK_BUS_I2C0>;
590 resets = <&ccu RST_BUS_I2C0>;
592 #address-cells = <1>;
597 compatible = "allwinner,sun6i-a31-i2c";
598 reg = <0x01c2b000 0x400>;
599 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&ccu CLK_BUS_I2C1>;
601 resets = <&ccu RST_BUS_I2C1>;
603 #address-cells = <1>;
608 compatible = "allwinner,sun6i-a31-i2c";
609 reg = <0x01c2b400 0x400>;
610 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&ccu CLK_BUS_I2C2>;
612 resets = <&ccu RST_BUS_I2C2>;
614 #address-cells = <1>;
620 compatible = "allwinner,sun8i-h3-spi";
621 reg = <0x01c68000 0x1000>;
622 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
624 clock-names = "ahb", "mod";
625 dmas = <&dma 23>, <&dma 23>;
626 dma-names = "rx", "tx";
627 pinctrl-names = "default";
628 pinctrl-0 = <&spi0_pins>;
629 resets = <&ccu RST_BUS_SPI0>;
632 #address-cells = <1>;
637 compatible = "allwinner,sun8i-h3-spi";
638 reg = <0x01c69000 0x1000>;
639 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
641 clock-names = "ahb", "mod";
642 dmas = <&dma 24>, <&dma 24>;
643 dma-names = "rx", "tx";
644 pinctrl-names = "default";
645 pinctrl-0 = <&spi1_pins>;
646 resets = <&ccu RST_BUS_SPI1>;
649 #address-cells = <1>;
653 emac: ethernet@1c30000 {
654 compatible = "allwinner,sun50i-a64-emac";
656 reg = <0x01c30000 0x10000>;
657 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
658 interrupt-names = "macirq";
659 resets = <&ccu RST_BUS_EMAC>;
660 reset-names = "stmmaceth";
661 clocks = <&ccu CLK_BUS_EMAC>;
662 clock-names = "stmmaceth";
666 compatible = "snps,dwmac-mdio";
667 #address-cells = <1>;
672 gic: interrupt-controller@1c81000 {
673 compatible = "arm,gic-400";
674 reg = <0x01c81000 0x1000>,
678 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
679 interrupt-controller;
680 #interrupt-cells = <3>;
684 compatible = "allwinner,sun50i-a64-pwm",
685 "allwinner,sun5i-a13-pwm";
686 reg = <0x01c21400 0x400>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&pwm_pin>;
695 compatible = "allwinner,sun6i-a31-rtc";
696 reg = <0x01f00000 0x54>;
697 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
699 clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
704 r_intc: interrupt-controller@1f00c00 {
705 compatible = "allwinner,sun50i-a64-r-intc",
706 "allwinner,sun6i-a31-r-intc";
707 interrupt-controller;
708 #interrupt-cells = <2>;
709 reg = <0x01f00c00 0x400>;
710 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
713 r_ccu: clock@1f01400 {
714 compatible = "allwinner,sun50i-a64-r-ccu";
715 reg = <0x01f01400 0x100>;
716 clocks = <&osc24M>, <&osc32k>, <&iosc>,
718 clock-names = "hosc", "losc", "iosc", "pll-periph";
724 compatible = "allwinner,sun50i-a64-i2c",
725 "allwinner,sun6i-a31-i2c";
726 reg = <0x01f02400 0x400>;
727 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&r_ccu CLK_APB0_I2C>;
729 resets = <&r_ccu RST_APB0_I2C>;
731 #address-cells = <1>;
736 compatible = "allwinner,sun50i-a64-pwm",
737 "allwinner,sun5i-a13-pwm";
738 reg = <0x01f03800 0x400>;
740 pinctrl-names = "default";
741 pinctrl-0 = <&r_pwm_pin>;
746 r_pio: pinctrl@1f02c00 {
747 compatible = "allwinner,sun50i-a64-r-pinctrl";
748 reg = <0x01f02c00 0x400>;
749 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
751 clock-names = "apb", "hosc", "losc";
754 interrupt-controller;
755 #interrupt-cells = <3>;
757 r_i2c_pins_a: i2c-a {
774 compatible = "allwinner,sun8i-a23-rsb";
775 reg = <0x01f03400 0x400>;
776 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
778 clock-frequency = <3000000>;
780 pinctrl-names = "default";
781 pinctrl-0 = <&r_rsb_pins>;
783 #address-cells = <1>;
787 wdt0: watchdog@1c20ca0 {
788 compatible = "allwinner,sun50i-a64-wdt",
789 "allwinner,sun6i-a31-wdt";
790 reg = <0x01c20ca0 0x20>;
791 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;